Mercurial > repos > blastem
annotate segacd.c @ 2056:27bbfcb7850a segacd
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 19 Jan 2022 00:08:01 -0800 |
parents | c4d066d798c4 |
children | 88deea42caf0 |
rev | line source |
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1 #include <stdlib.h> |
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2 #include <string.h> |
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3 #include "segacd.h" |
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4 #include "genesis.h" |
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5 #include "util.h" |
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6 |
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7 #define SCD_MCLKS 50000000 |
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8 #define SCD_PERIPH_RESET_CLKS (SCD_MCLKS / 10) |
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9 #define TIMER_TICK_CLKS 1536 |
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10 |
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11 enum { |
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12 GA_SUB_CPU_CTRL, |
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13 GA_MEM_MODE, |
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14 GA_CDC_CTRL, |
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15 GA_CDC_REG_DATA, |
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16 GA_CDC_HOST_DATA, |
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17 GA_CDC_DMA_ADDR, |
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18 GA_STOP_WATCH, |
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19 GA_COMM_FLAG, |
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20 GA_COMM_CMD0, |
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21 GA_COMM_CMD1, |
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22 GA_COMM_CMD2, |
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23 GA_COMM_CMD3, |
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24 GA_COMM_CMD4, |
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25 GA_COMM_CMD5, |
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26 GA_COMM_CMD6, |
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27 GA_COMM_CMD7, |
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28 GA_COMM_STATUS0, |
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29 GA_COMM_STATUS1, |
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30 GA_COMM_STATUS2, |
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31 GA_COMM_STATUS3, |
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32 GA_COMM_STATUS4, |
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33 GA_COMM_STATUS5, |
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34 GA_COMM_STATUS6, |
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35 GA_COMM_STATUS7, |
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36 GA_TIMER, |
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37 GA_INT_MASK, |
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38 GA_CDD_FADER, |
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39 GA_CDD_CTRL, |
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40 |
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41 GA_HINT_VECTOR = GA_CDC_REG_DATA |
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42 }; |
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43 //GA_SUB_CPU_CTRL |
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44 #define BIT_IEN2 0x8000 |
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45 #define BIT_IFL2 0x0100 |
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46 #define BIT_LEDG 0x0100 |
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47 #define BIT_LEDR 0x0080 |
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48 #define BIT_SBRQ 0x0002 |
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49 #define BIT_SRES 0x0001 |
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50 #define BIT_PRES 0x0001 |
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51 //GA_MEM_MODE |
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52 #define MASK_PROG_BANK 0x00C0 |
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53 #define MASK_PRIORITY 0x0018 |
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54 #define BIT_MEM_MODE 0x0004 |
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55 #define BIT_DMNA 0x0002 |
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56 #define BIT_RET 0x0001 |
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57 //GA_INT_MASK |
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58 #define BIT_MASK_IEN1 0x0002 |
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59 #define BIT_MASK_IEN2 0x0004 |
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60 #define BIT_MASK_IEN3 0x0008 |
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61 #define BIT_MASK_IEN4 0x0010 |
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62 #define BIT_MASK_IEN5 0x0020 |
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63 #define BIT_MASK_IEN6 0x0040 |
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64 |
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65 static void *prog_ram_wp_write16(uint32_t address, void *vcontext, uint16_t value) |
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66 { |
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67 m68k_context *m68k = vcontext; |
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68 segacd_context *cd = m68k->system; |
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69 if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 17) + 8)))) { |
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70 cd->prog_ram[address >> 1] = value; |
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71 m68k_invalidate_code_range(m68k, address, address + 2); |
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72 } |
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73 return vcontext; |
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74 } |
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75 |
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76 static void *prog_ram_wp_write8(uint32_t address, void *vcontext, uint8_t value) |
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77 { |
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78 m68k_context *m68k = vcontext; |
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79 segacd_context *cd = m68k->system; |
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80 if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 17) + 8)))) { |
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81 ((uint8_t *)cd->prog_ram)[address ^ 1] = value; |
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82 m68k_invalidate_code_range(m68k, address, address + 1); |
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83 } |
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84 return vcontext; |
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85 } |
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86 |
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87 static uint16_t word_ram_2M_read16(uint32_t address, void *vcontext) |
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88 { |
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89 return 0; |
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90 } |
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91 |
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92 static uint8_t word_ram_2M_read8(uint32_t address, void *vcontext) |
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93 { |
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94 return 0; |
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95 } |
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96 |
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97 static void *word_ram_2M_write16(uint32_t address, void *vcontext, uint16_t value) |
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98 { |
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99 return vcontext; |
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100 } |
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101 |
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102 static void *word_ram_2M_write8(uint32_t address, void *vcontext, uint8_t value) |
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103 { |
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104 return vcontext; |
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105 } |
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106 |
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107 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext) |
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108 { |
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109 return 0; |
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110 } |
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111 |
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112 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext) |
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113 { |
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114 return 0; |
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115 } |
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116 |
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117 static void *word_ram_1M_write16(uint32_t address, void *vcontext, uint16_t value) |
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118 { |
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119 return vcontext; |
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120 } |
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121 |
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122 static void *word_ram_1M_write8(uint32_t address, void *vcontext, uint8_t value) |
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123 { |
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124 return vcontext; |
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125 } |
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126 |
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127 |
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128 static uint16_t unmapped_prog_read16(uint32_t address, void *vcontext) |
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129 { |
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130 return 0xFFFF; |
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131 } |
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132 |
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133 static uint8_t unmapped_prog_read8(uint32_t address, void *vcontext) |
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134 { |
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135 return 0xFF; |
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136 } |
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137 |
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138 static void *unmapped_prog_write16(uint32_t address, void *vcontext, uint16_t value) |
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139 { |
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140 return vcontext; |
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141 } |
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142 |
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143 static void *unmapped_prog_write8(uint32_t address, void *vcontext, uint8_t value) |
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144 { |
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145 return vcontext; |
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146 } |
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147 |
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148 static uint8_t pcm_read8(uint32_t address, void *vcontext) |
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149 { |
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150 return 0; |
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151 } |
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152 |
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153 static uint16_t pcm_read16(uint32_t address, void *vcontext) |
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154 { |
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155 return 0xFF00 | pcm_read8(address+1, vcontext); |
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156 } |
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157 |
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158 static void *pcm_write8(uint32_t address, void *vcontext, uint8_t value) |
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159 { |
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160 return vcontext; |
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161 } |
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162 |
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163 static void *pcm_write16(uint32_t address, void *vcontext, uint16_t value) |
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164 { |
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165 return pcm_write8(address+1, vcontext, value); |
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166 } |
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167 |
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168 |
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169 static void timers_run(segacd_context *cd, uint32_t cycle) |
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170 { |
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171 uint32_t ticks = (cycle - cd->stopwatch_cycle) / TIMER_TICK_CLKS; |
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172 cd->stopwatch_cycle += ticks * TIMER_TICK_CLKS; |
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173 cd->gate_array[GA_STOP_WATCH] += ticks; |
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174 cd->gate_array[GA_STOP_WATCH] &= 0xFFF; |
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175 if (!cd->timer_value) { |
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176 --ticks; |
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177 cd->timer_value = cd->gate_array[GA_TIMER]; |
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178 } |
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179 if (cd->timer_value) { |
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180 while (ticks >= (cd->timer_value + 1)) { |
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181 ticks -= cd->timer_value + 1; |
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182 cd->timer_value = cd->gate_array[GA_TIMER]; |
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183 cd->timer_pending = 1; |
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184 } |
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185 cd->timer_value -= ticks; |
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186 if (!cd->timer_value) { |
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187 cd->timer_pending = 1; |
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188 } |
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189 } |
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190 } |
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191 |
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192 static uint32_t next_timer_int(segacd_context *cd) |
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193 { |
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194 if (cd->timer_pending) { |
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195 return cd->stopwatch_cycle; |
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196 } |
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197 if (cd->timer_value) { |
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198 return cd->stopwatch_cycle + TIMER_TICK_CLKS * cd->timer_value; |
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199 } |
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200 if (cd->gate_array[GA_TIMER]) { |
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201 return cd->stopwatch_cycle + TIMER_TICK_CLKS * (cd->gate_array[GA_TIMER] + 1); |
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202 } |
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203 return CYCLE_NEVER; |
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204 } |
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205 |
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206 static void calculate_target_cycle(m68k_context * context) |
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207 { |
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208 segacd_context *cd = context->system; |
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209 context->int_cycle = CYCLE_NEVER; |
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210 uint8_t mask = context->status & 0x7; |
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211 if (mask < 3) { |
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212 uint32_t next_timer; |
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213 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN3) { |
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214 uint32_t next_timer_cycle = next_timer_int(cd); |
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215 if (next_timer_cycle < context->int_cycle) { |
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216 context->int_cycle = next_timer_cycle; |
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217 context->int_num = 3; |
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218 } |
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219 } |
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220 if (mask < 2) { |
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221 if (cd->int2_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) { |
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222 context->int_cycle = cd->int2_cycle; |
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223 context->int_num = 2; |
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224 } |
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225 } |
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226 } |
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227 if (context->int_cycle > context->current_cycle && context->int_pending == INT_PENDING_SR_CHANGE) { |
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228 context->int_pending = INT_PENDING_NONE; |
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229 } |
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230 if (context->current_cycle >= context->sync_cycle) { |
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231 context->should_return = 1; |
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232 context->target_cycle = context->current_cycle; |
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233 return; |
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234 } |
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235 if (context->status & M68K_STATUS_TRACE || context->trace_pending) { |
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236 context->target_cycle = context->current_cycle; |
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237 return; |
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238 } |
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239 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle; |
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240 } |
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241 |
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242 static uint16_t sub_gate_read16(uint32_t address, void *vcontext) |
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243 { |
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244 m68k_context *m68k = vcontext; |
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245 segacd_context *cd = m68k->system; |
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246 uint32_t reg = address >> 1; |
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247 switch (reg) |
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248 { |
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249 case GA_SUB_CPU_CTRL: { |
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250 uint16_t value = cd->gate_array[reg] & 0xFFFE; |
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251 if (cd->periph_reset_cycle == CYCLE_NEVER || (m68k->current_cycle - cd->periph_reset_cycle) > SCD_PERIPH_RESET_CLKS) { |
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252 value |= BIT_PRES; |
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253 } |
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254 return value; |
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255 } |
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256 case GA_MEM_MODE: |
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257 return cd->gate_array[reg] & 0xFF1F; |
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258 case GA_STOP_WATCH: |
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259 case GA_TIMER: |
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260 timers_run(cd, m68k->current_cycle); |
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261 return cd->gate_array[reg]; |
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262 default: |
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263 return cd->gate_array[reg]; |
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264 } |
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265 } |
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266 |
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267 static uint8_t sub_gate_read8(uint32_t address, void *vcontext) |
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268 { |
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269 uint16_t val = sub_gate_read16(address, vcontext); |
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270 return address & 1 ? val : val >> 8; |
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271 } |
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272 |
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273 static void *sub_gate_write16(uint32_t address, void *vcontext, uint16_t value) |
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274 { |
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275 m68k_context *m68k = vcontext; |
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276 segacd_context *cd = m68k->system; |
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277 uint32_t reg = address >> 1; |
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278 switch (reg) |
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279 { |
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280 case GA_SUB_CPU_CTRL: |
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281 cd->gate_array[reg] &= 0xF0; |
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282 cd->gate_array[reg] |= value & (BIT_LEDG|BIT_LEDR); |
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283 if (value & BIT_PRES) { |
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284 cd->periph_reset_cycle = m68k->current_cycle; |
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285 } |
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286 break; |
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287 case GA_MEM_MODE: { |
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288 uint16_t changed = value ^ cd->gate_array[reg]; |
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289 genesis_context *gen = cd->genesis; |
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290 if (changed & BIT_MEM_MODE) { |
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291 //FIXME: ram banks are supposed to be interleaved when in 2M mode |
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292 cd->gate_array[reg] &= ~BIT_DMNA; |
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293 if (value & BIT_MEM_MODE) { |
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294 //switch to 1M mode |
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295 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = (value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram; |
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296 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
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297 m68k->mem_pointers[0] = NULL; |
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298 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 0x10000; |
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299 } else { |
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300 //switch to 2M mode |
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301 if (value & BIT_RET) { |
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302 //Main CPU will have word ram |
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303 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram; |
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304 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000; |
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305 m68k->mem_pointers[0] = NULL; |
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306 m68k->mem_pointers[1] = NULL; |
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307 } else { |
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308 //sub cpu will have word ram |
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309 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; |
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310 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
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311 m68k->mem_pointers[0] = cd->word_ram; |
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312 m68k->mem_pointers[1] = NULL; |
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313 } |
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314 } |
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315 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
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316 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
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317 } else if (changed & BIT_RET) { |
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318 cd->gate_array[reg] &= ~BIT_DMNA; |
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319 if (value & BIT_MEM_MODE) { |
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320 //swapping banks in 1M mode |
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321 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = (value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram; |
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322 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 0x10000; |
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323 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
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324 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
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325 } else if (value & BIT_RET) { |
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326 //giving word ram to main CPU in 2M mode |
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327 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram; |
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328 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000; |
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329 m68k->mem_pointers[0] = NULL; |
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330 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
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331 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
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332 } |
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333 } |
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334 cd->gate_array[reg] &= 0xFFC2; |
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335 cd->gate_array[reg] |= value & (BIT_RET|BIT_MEM_MODE|MASK_PRIORITY); |
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336 break; |
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337 } |
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338 case GA_STOP_WATCH: |
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339 //docs say you should only write zero to reset |
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340 //unclear what happens when other values are written |
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341 timers_run(cd, m68k->current_cycle); |
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342 cd->gate_array[reg] = value & 0xFFF; |
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343 break; |
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344 case GA_COMM_FLAG: |
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345 cd->gate_array[reg] &= 0xFF00; |
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346 cd->gate_array[reg] |= value & 0xFF; |
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347 break; |
2054
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348 case GA_COMM_STATUS0: |
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349 case GA_COMM_STATUS1: |
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350 case GA_COMM_STATUS2: |
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351 case GA_COMM_STATUS3: |
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352 case GA_COMM_STATUS4: |
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353 case GA_COMM_STATUS5: |
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354 case GA_COMM_STATUS6: |
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355 case GA_COMM_STATUS7: |
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356 //no effects for these other than saving the value |
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357 cd->gate_array[reg] = value; |
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358 break; |
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359 case GA_TIMER: |
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360 timers_run(cd, m68k->current_cycle); |
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361 cd->gate_array[reg] = value & 0xFF; |
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362 calculate_target_cycle(m68k); |
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363 break; |
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364 case GA_INT_MASK: |
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365 cd->gate_array[reg] = value & (BIT_MASK_IEN6|BIT_MASK_IEN5|BIT_MASK_IEN4|BIT_MASK_IEN3|BIT_MASK_IEN2|BIT_MASK_IEN1); |
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366 calculate_target_cycle(m68k); |
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367 break; |
1502
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368 default: |
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369 printf("Unhandled gate array write %X:%X\n", address, value); |
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370 } |
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371 return vcontext; |
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372 } |
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373 |
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374 static void *sub_gate_write8(uint32_t address, void *vcontext, uint8_t value) |
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375 { |
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376 m68k_context *m68k = vcontext; |
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377 segacd_context *cd = m68k->system; |
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378 uint32_t reg = (address & 0x1FF) >> 1; |
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379 uint16_t value16; |
2056
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380 switch (address >> 1) |
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381 { |
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382 case GA_CDC_HOST_DATA: |
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383 case GA_CDC_DMA_ADDR: |
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384 case GA_STOP_WATCH: |
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385 case GA_COMM_FLAG: |
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386 case GA_CDD_FADER: |
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387 //these registers treat all writes as word-wide |
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388 value16 = value | (value << 8); |
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389 break; |
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390 default: |
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391 if (address & 1) { |
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392 value16 = cd->gate_array[reg] & 0xFF00 | value; |
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393 } else { |
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394 value16 = cd->gate_array[reg] & 0xFF | (value << 8); |
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|
395 } |
1502
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396 } |
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397 return sub_gate_write16(address, vcontext, value16); |
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398 } |
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399 |
2054
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|
400 static uint8_t can_main_access_prog(segacd_context *cd) |
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diff
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|
401 { |
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diff
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|
402 //TODO: use actual busack |
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|
403 return cd->busreq || !cd->reset; |
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|
404 } |
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|
405 |
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|
406 static void scd_peripherals_run(segacd_context *cd, uint32_t cycle) |
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|
407 { |
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|
408 timers_run(cd, cycle); |
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409 } |
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|
410 |
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|
411 static m68k_context *sync_components(m68k_context * context, uint32_t address) |
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diff
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|
412 { |
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|
413 segacd_context *cd = context->system; |
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|
414 scd_peripherals_run(cd, context->current_cycle); |
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|
415 calculate_target_cycle(context); |
8ee7ecbf3f21
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|
416 return context; |
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417 } |
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418 |
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419 void scd_run(segacd_context *cd, uint32_t cycle) |
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420 { |
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421 uint8_t m68k_run = !can_main_access_prog(cd); |
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422 if (m68k_run) { |
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423 cd->m68k->sync_cycle = cycle; |
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424 if (cd->need_reset) { |
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425 cd->need_reset = 0; |
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426 m68k_reset(cd->m68k); |
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427 } else { |
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428 calculate_target_cycle(cd->m68k); |
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429 resume_68k(cd->m68k); |
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430 } |
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431 } else { |
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432 cd->m68k->current_cycle = cycle; |
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433 } |
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434 scd_peripherals_run(cd, cycle); |
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435 } |
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436 |
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437 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen) |
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438 { |
2055
c4d066d798c4
Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
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439 return ((uint64_t)cycle) * ((uint64_t)SCD_MCLKS) / ((uint64_t)gen->normal_clock); |
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440 } |
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441 |
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442 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction) |
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443 { |
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444 deduction = gen_cycle_to_scd(deduction, cd->genesis); |
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445 cd->m68k->current_cycle -= deduction; |
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446 cd->stopwatch_cycle -= deduction; |
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447 if (deduction >= cd->int2_cycle) { |
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448 cd->int2_cycle = 0; |
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449 } else if (cd->int2_cycle != CYCLE_NEVER) { |
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450 cd->int2_cycle -= deduction; |
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451 } |
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452 if (deduction >= cd->periph_reset_cycle) { |
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453 cd->periph_reset_cycle = CYCLE_NEVER; |
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454 } else if (cd->periph_reset_cycle != CYCLE_NEVER) { |
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455 cd->periph_reset_cycle -= deduction; |
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456 } |
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457 } |
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458 |
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459 static uint16_t main_gate_read16(uint32_t address, void *vcontext) |
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460 { |
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461 m68k_context *m68k = vcontext; |
2054
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462 genesis_context *gen = m68k->system; |
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463 segacd_context *cd = gen->expansion; |
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464 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen); |
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465 scd_run(cd, scd_cycle); |
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466 uint32_t offset = (address & 0x1FF) >> 1; |
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467 switch (offset) |
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468 { |
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469 case GA_SUB_CPU_CTRL: { |
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470 uint16_t value = 0; |
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471 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2) { |
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472 value |= BIT_IEN2; |
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473 } |
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474 if (cd->int2_cycle != CYCLE_NEVER) { |
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475 value |= BIT_IFL2; |
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476 } |
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477 if (can_main_access_prog(cd)) { |
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478 value |= BIT_SBRQ; |
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479 } |
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480 if (cd->reset) { |
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481 value |= BIT_SRES; |
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482 } |
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483 return value; |
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484 } |
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485 case GA_MEM_MODE: |
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|
486 //Main CPU can't read priority mode bits |
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487 return cd->gate_array[offset] & 0xFFE7; |
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488 case GA_HINT_VECTOR: |
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489 return cd->rom_mut[0x72/2]; |
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490 case GA_CDC_DMA_ADDR: |
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491 //TODO: open bus maybe? |
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492 return 0xFFFF; |
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493 default: |
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494 if (offset < GA_TIMER) { |
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495 return cd->gate_array[offset]; |
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496 } |
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497 //TODO: open bus maybe? |
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498 return 0xFFFF; |
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|
499 } |
1502
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|
500 } |
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|
501 |
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502 static uint8_t main_gate_read8(uint32_t address, void *vcontext) |
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503 { |
2054
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504 uint16_t val = main_gate_read16(address & 0xFE, vcontext); |
1502
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505 return address & 1 ? val : val >> 8; |
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|
506 } |
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|
507 |
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508 static void *main_gate_write16(uint32_t address, void *vcontext, uint16_t value) |
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|
509 { |
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510 m68k_context *m68k = vcontext; |
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511 genesis_context *gen = m68k->system; |
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512 segacd_context *cd = gen->expansion; |
2054
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513 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen); |
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514 scd_run(cd, scd_cycle); |
1502
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515 uint32_t reg = (address & 0x1FF) >> 1; |
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|
516 switch (reg) |
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|
517 { |
2054
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|
518 case GA_SUB_CPU_CTRL: { |
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diff
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|
519 uint8_t old_access = can_main_access_prog(cd); |
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|
520 cd->busreq = value & BIT_SBRQ; |
8ee7ecbf3f21
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521 uint8_t old_reset = cd->reset; |
8ee7ecbf3f21
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diff
changeset
|
522 cd->reset = value & BIT_SRES; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
523 if (cd->reset && !old_reset) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
524 cd->need_reset = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
525 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
526 cd->gate_array[reg] &= 0x7FFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
527 cd->gate_array[reg] |= value & 0x8000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
528 uint8_t new_access = can_main_access_prog(cd); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
529 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
530 if (new_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
531 if (!old_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
532 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
533 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
534 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
535 } else if (old_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
536 m68k->mem_pointers[cd->memptr_start_index] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
537 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
538 m68k_invalidate_code_range(cd->m68k, bank * 0x20000, (bank + 1) * 0x20000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
539 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
540 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
541 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
542 case GA_MEM_MODE: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
543 uint16_t changed = cd->gate_array[reg] ^ value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
544 //Main CPU can't write priority mode bits, MODE or RET |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
545 cd->gate_array[reg] &= 0x001D; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
546 cd->gate_array[reg] |= value & 0xFFC0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
547 if ((cd->gate_array[reg] & BIT_MEM_MODE)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
548 //1M mode |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
549 if (!(value & BIT_DMNA)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
550 cd->gate_array[reg] |= BIT_DMNA; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
551 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
552 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
553 cd->gate_array[reg] |= value & BIT_DMNA; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
554 //2M mode |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
555 if (changed & value & BIT_DMNA) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
556 m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
557 m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
558 cd->m68k->mem_pointers[0] = cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
559 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
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1504
diff
changeset
|
560 m68k_invalidate_code_range(m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
561 m68k_invalidate_code_range(cd->m68k, 0x080000, 0x0C0000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
562 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
563 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
564 if (changed & MASK_PROG_BANK) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
565 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3; |
2055
c4d066d798c4
Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents:
2054
diff
changeset
|
566 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
567 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
568 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
569 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
570 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
571 case GA_HINT_VECTOR: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
572 cd->rom_mut[0x72/2] = value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
573 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
574 case GA_COMM_FLAG: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
575 //Main CPU can only write the upper byte; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
576 cd->gate_array[reg] &= 0xFF; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
577 cd->gate_array[reg] |= value & 0xFF00; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
578 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
579 case GA_COMM_CMD0: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
580 case GA_COMM_CMD1: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
581 case GA_COMM_CMD2: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
582 case GA_COMM_CMD3: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
583 case GA_COMM_CMD4: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
584 case GA_COMM_CMD5: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
585 case GA_COMM_CMD6: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
586 case GA_COMM_CMD7: |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
587 //no effects for these other than saving the value |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
588 cd->gate_array[reg] = value; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
589 break; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
590 default: |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
591 printf("Unhandled gate array write %X:%X\n", address, value); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
592 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
593 return vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
594 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
595 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
596 static void *main_gate_write8(uint32_t address, void *vcontext, uint8_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
597 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
598 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
599 genesis_context *gen = m68k->system; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
600 segacd_context *cd = gen->expansion; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
601 uint32_t reg = (address & 0x1FF) >> 1; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
602 uint16_t value16; |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
603 switch (reg >> 1) |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
604 { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
605 case GA_HINT_VECTOR: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
606 case GA_COMM_FLAG: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
607 //writes to these regs are always treated as word wide |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
608 value16 = value | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
609 break; |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
610 default: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
611 if (address & 1) { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
612 value16 = cd->gate_array[reg] & 0xFF00 | value; |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
613 } else { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
614 value16 = cd->gate_array[reg] & 0xFF | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
615 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
616 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
617 return main_gate_write16(address, vcontext, value16); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
618 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
619 |
2564b6ba2e12
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parents:
1467
diff
changeset
|
620 segacd_context *alloc_configure_segacd(system_media *media, uint32_t opts, uint8_t force_region, rom_info *info) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
621 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
622 static memmap_chunk sub_cpu_map[] = { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
623 {0x000000, 0x00FEFF, 0xFFFFFF, .flags=MMAP_READ | MMAP_CODE, .write_16 = prog_ram_wp_write16, .write_8 = prog_ram_wp_write8}, |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
624 {0x00FF00, 0x07FFFF, 0xFFFFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE}, |
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625 {0x080000, 0x0BFFFF, 0x03FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 0, |
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626 .read_16 = word_ram_2M_read16, .write_16 = word_ram_2M_write16, .read_8 = word_ram_2M_read8, .write_8 = word_ram_2M_write8}, |
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627 {0x0C0000, 0x0DFFFF, 0x01FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 1, |
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628 .read_16 = word_ram_1M_read16, .write_16 = word_ram_1M_write16, .read_8 = word_ram_1M_read8, .write_8 = word_ram_1M_write8}, |
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629 {0xFE0000, 0xFEFFFF, 0x003FFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_ONLY_ODD}, |
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630 {0xFF0000, 0xFF7FFF, 0x003FFF, .read_16 = pcm_read16, .write_16 = pcm_write16, .read_8 = pcm_read8, .write_8 = pcm_write8}, |
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631 {0xFF8000, 0xFF81FF, 0x0001FF, .read_16 = sub_gate_read16, .write_16 = sub_gate_write16, .read_8 = sub_gate_read8, .write_8 = sub_gate_write8} |
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632 }; |
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633 |
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634 segacd_context *cd = calloc(sizeof(segacd_context), 1); |
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635 FILE *f = fopen("cdbios.bin", "rb"); |
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636 if (!f) { |
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637 fatal_error("Failed to open CD firmware for reading"); |
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638 } |
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639 long firmware_size = file_size(f); |
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640 uint32_t adjusted_size = nearest_pow2(firmware_size); |
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641 cd->rom = malloc(adjusted_size); |
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642 if (firmware_size != fread(cd->rom, 1, firmware_size, f)) { |
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643 fatal_error("Failed to read CD firmware"); |
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644 } |
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645 cd->rom_mut = malloc(adjusted_size); |
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646 byteswap_rom(adjusted_size, cd->rom); |
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647 memcpy(cd->rom_mut, cd->rom, adjusted_size); |
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648 cd->rom_mut[0x72/2] = 0xFFFF; |
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649 |
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650 //memset(info, 0, sizeof(*info)); |
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651 //tern_node *db = get_rom_db(); |
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652 //*info = configure_rom(db, media->buffer, media->size, media->chain ? media->chain->buffer : NULL, media->chain ? media->chain->size : 0, NULL, 0); |
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653 |
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654 cd->prog_ram = malloc(512*1024); |
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655 cd->word_ram = malloc(256*1024); |
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656 cd->pcm_ram = malloc(64*1024); |
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657 //TODO: Load state from file |
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658 cd->bram = malloc(8*1024); |
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659 |
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660 |
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661 sub_cpu_map[0].buffer = sub_cpu_map[1].buffer = cd->prog_ram; |
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662 sub_cpu_map[4].buffer = cd->bram; |
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663 m68k_options *mopts = malloc(sizeof(m68k_options)); |
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664 init_m68k_opts(mopts, sub_cpu_map, sizeof(sub_cpu_map) / sizeof(*sub_cpu_map), 4, sync_components); |
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665 cd->m68k = init_68k_context(mopts, NULL); |
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666 cd->m68k->system = cd; |
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667 cd->int2_cycle = CYCLE_NEVER; |
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668 cd->busreq = 1; |
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669 cd->busack = 1; |
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670 cd->need_reset = 1; |
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671 cd->reset = 1; //active low, so reset is not active on start |
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672 cd->memptr_start_index = 0; |
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673 cd->gate_array[1] = 1; |
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674 cd->gate_array[0x1B] = 0x100; |
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675 |
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676 return cd; |
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677 } |
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678 |
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679 memmap_chunk *segacd_main_cpu_map(segacd_context *cd, uint8_t cart_boot, uint32_t *num_chunks) |
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680 { |
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681 static memmap_chunk main_cpu_map[] = { |
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682 {0x000000, 0x01FFFF, 0x01FFFF, .flags=MMAP_READ}, |
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683 {0x020000, 0x03FFFF, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 0, |
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684 .read_16 = unmapped_prog_read16, .write_16 = unmapped_prog_write16, .read_8 = unmapped_prog_read8, .write_8 = unmapped_prog_write8}, |
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685 {0x040000, 0x05FFFF, 0x01FFFF, .flags=MMAP_READ}, //first ROM alias |
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686 //TODO: additional ROM/prog RAM aliases |
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687 {0x200000, 0x21FFFF, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 1}, |
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688 {0x220000, 0x23FFFF, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 2}, |
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689 {0xA12000, 0xA12FFF, 0xFFFFFF, .read_16 = main_gate_read16, .write_16 = main_gate_write16, .read_8 = main_gate_read8, .write_8 = main_gate_write8} |
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690 }; |
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691 for (int i = 0; i < sizeof(main_cpu_map) / sizeof(*main_cpu_map); i++) |
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692 { |
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693 if (main_cpu_map[i].start < 0x800000) { |
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694 if (cart_boot) { |
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695 main_cpu_map[i].start |= 0x400000; |
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696 main_cpu_map[i].end |= 0x400000; |
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697 } else { |
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698 main_cpu_map[i].start &= 0x3FFFFF; |
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699 main_cpu_map[i].end &= 0x3FFFFF; |
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700 } |
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701 } |
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702 } |
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703 //TODO: support BRAM cart |
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704 main_cpu_map[0].buffer = cd->rom_mut; |
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705 main_cpu_map[2].buffer = cd->rom; |
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706 main_cpu_map[1].buffer = cd->prog_ram; |
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707 main_cpu_map[3].buffer = cd->word_ram; |
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708 main_cpu_map[4].buffer = cd->word_ram + 0x10000; |
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709 *num_chunks = sizeof(main_cpu_map) / sizeof(*main_cpu_map); |
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710 return main_cpu_map; |
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711 } |