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annotate svp.cpu @ 1615:28f80d1b343e

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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
author Michael Pavone <pavone@retrodev.com>
date Mon, 24 Sep 2018 19:09:16 -0700
parents c9639139aedf
children 5e04f9f8bd85
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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1 info
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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2 prefix svp_
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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3 opcode_size 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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4 body svp_run_op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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6 regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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7 internal 16 scratch1 x y scratch2 st pad pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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8 a 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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9 stack 16 stack0 stack1 stack2 stack3 stack4 stack5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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10 stackidx 8
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11 p 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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12 external 16 pm0 pm1 pm2 xst pm4 ext5 pmc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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13 pointers0 8 r0 r1 r2 r3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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14 pointers1 8 r4 r5 r6 r7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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15 iram 16 1024
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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16 ram0 16 256
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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17 ram1 16 256
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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18 zflag 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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19 nflag 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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20 rpl 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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21
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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22 flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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23 register st
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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24 Z 13 zero zflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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25 N 15 sign nflag
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26 R 0-2 none rpl
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27
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28 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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29 mov stack.stackidx dst
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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30 add 1 stackidx stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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31 switch stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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32 case 6
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33 mov 0 stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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34 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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35
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36 svp_push
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37 arg src 16
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38 add -1 stackidx stackidx
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39 switch stackidx
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40 case -1
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41 mov 5 stackidx
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42 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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43 mov src stack.stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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44
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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45 svp_ram_read
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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46 arg mode 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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47 arg banki 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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48 arg regi 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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49 local idx 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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50
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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51 switch banki
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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52 case 0
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53 meta bank ram0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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54 meta reg pointers0.regi
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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55
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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56 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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57 meta bank ram1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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58 meta reg pointers1.regi
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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59 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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60
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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61 mov reg idx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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62 switch mode
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63 case 0
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64 meta modestr ""
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65
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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66 case 1
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67 meta modestr +!
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68 add 1 reg reg
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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69
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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70 case 2
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71 #loop decremenet
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72 meta modestr -
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73 mov reg tmp
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents: 1613
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74
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
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75 if rpl
1613
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76 lsl 1 rpl rpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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77 sub 1 rpl rpl
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78 local mask 16
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79 not rpl mask
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80 and reg mask reg
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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81 sub 1 tmp tmp
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82 and rpl tmp tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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83 or rpl reg reg
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
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84 else
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents: 1613
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85 sub 1 reg reg
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents: 1613
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86 end
1613
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87
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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88 case 3
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89 #loop increment
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90 meta modestr +
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91
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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92 and 7 st rpl
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
93 if rpl
1613
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94 mov reg tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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95 lsl 1 rpl rpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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96 sub 1 rpl rpl
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97 local mask 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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98 not rpl mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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99 and reg mask reg
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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100 add 1 tmp tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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101 and rpl tmp tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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102 or rpl reg reg
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
103 else
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
104 sub 1 reg reg
1613
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105 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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106
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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107 and 255 idx idx
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108 meta val bank.idx
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109
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110 svp_read_ext
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111 arg regidxr 16
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112 switch regidxr
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113 case 7
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114 meta val a
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115
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116 default
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117 #TODO: PMAR stuff
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118 meta val external.regidxr
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119 end
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120
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121 svp_write_ext
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122 arg regidxw 16
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123 switch regidxw
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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124 case 7
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125 and 0xFFFF0000 a a
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126 or src a a
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127
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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128 default
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129 #TODO: PMAR stuff
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff changeset
130 mov src external.regidxw
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
131 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
132
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
133 svp_alu_op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
134 arg P 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
135 arg param 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137 switch P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
138 case 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
139 dis "sub %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
140 sub param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
142 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143 dis "cmp %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 cmp param a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 case 4
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 dis "add %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148 add param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
150 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 dis "and %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152 and param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 dis "or %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
156 or param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
157
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
158 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
159 dis "eor %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160 xor param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164 svp_check_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 arg fval 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 arg cond 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 local invert 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 switch cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 case 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 meta flag 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 meta flag zflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176 meta flag nflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 meta flag 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 end
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
181
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
182 if fval
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
183 meta istrue flag
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
184
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
185 else
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 lnot flag invert
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
187 meta istrue invert
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
188
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
191 PPP0000000000000 alu_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194 meta name "-"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195 svp_alu_op P 0xFFFF0000
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197 PPP0000000000RRR alu_r
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
201 lsl internal.R 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202 meta name internal.R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 PPP0000000000011 alu_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 svp_alu_op P a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 PPP0000000000101 alu_stack
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 svp_pop
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
216 meta name "stack"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 PPP0000000000111 alu_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 meta name p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 svp_alu_op P p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 PPP0000000001RRR alu_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 svp_read_ext R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 meta name val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
234 PPP0001B0000MMRR alu_ram
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 svp_ram_read M B R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 switch P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 case 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 dis "sub (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 sub tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 dis "cmp (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 cmp tmp a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 case 4
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 dis "add (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 add tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 dis "and (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 and tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 dis "or (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 dis "eor (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 xor tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
269 PPP0101B0000MMRR alu_ram_indirect
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
270 invalid P 0
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
271 invalid P 2
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
272 svp_ram_read M B R
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
273 svp_prog_ram_read scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
274 local tmp 32
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
275 lsl val 16 tmp
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
276
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
277 switch P
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
278 case 1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
279 dis "sub ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
280 sub tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
281
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
282 case 3
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
283 dis "cmp ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
284 cmp tmp a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
285
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
286 case 4
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
287 dis "add ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
288 add tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
289
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
290 case 5
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
291 dis "and ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
292 and tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
293
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
294 case 6
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
295 dis "or ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
296 or tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
297
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
298 case 7
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
299 dis "eor ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
300 xor tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
301 end
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
302
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
303 update_flags ZN
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
304
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 PPP0000000001111 alu_al
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309 lsl a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 meta name al
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
314 PPP0011JAAAAAAAA alu_ram_direct
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
315 invalid P 0
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
316 invalid P 2
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
317 if J
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
318 meta src ram1.A
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
319 else
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
320 meta src ram0.A
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
321 end
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
322 svp_alu_op P src
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
323
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
324 PPP0010000000000 alu_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
325 invalid P 0
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
326 invalid P 2
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
327 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
328 svp_alu_op P scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
329
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 1001000FCCCC0OOO cond_mod
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331 svp_check_cond F C
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
332 if istrue
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
333
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 switch O
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 case 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 asr a 1 a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 lsl a 1 a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 neg a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 abs a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 update_flags N
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 end
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
351 end
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 000000000DDD0SSS ld_int_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 dis "ld %s, %s" internal.D internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 mov internal.S internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
357 000000000DDD0101 ld_int_stack
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
358 dis "ld %s, stack" internal.D
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 meta dst internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
362 0000000000110101 ld_a_stack
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
363 dis "ld a, stack"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 lsl tmp 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
371 0000000001110101 ld_p_stack
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
372 dis "ld p, stack"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 lsl tmp 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
380 0000000001010SSS ld_stack_int
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
381 dis "ld stack, %s" internal.S
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 svp_push internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
384 0000000001010011 ld_stack_a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
385 dis "ld stack, a"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 svp_push tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
390 0000000001010111 ld_stack_p
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
391 dis "ld stack, p"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 svp_push tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 0000000000000000 ld_n1_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 #nop?
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 dis "ld -, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 0000000000000SSS ld_n1_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 #nop?
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 dis "nop??"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 0000000000110111 ld_a_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 dis "ld a, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 mov p a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 0000000001110011 ld_p_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 dis "ld p, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 mov a p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 0000000000110011 ld_a_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 dis "ld a, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 mov a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 0000000001110111 ld_p_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 dis "ld p, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 mov p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 000000000DDD0111 ld_int_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 mov tmp internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 dis "ld %s, p" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 000000000DDD0111 ld_int_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 mov tmp internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 dis "ld %s, a" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 0000000001110SSS ld_p_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 lsl internal.S 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 mov tmp p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 dis "ld p, %s" internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 0000000000110SSS ld_a_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 lsl internal.S 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 mov tmp a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 dis "ld a, %s" internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 000000000DDD0000 ld_int_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 dis "ld %s, -" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 mov 0xFFFF internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 0000000000110000 ld_a_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 dis "ld a, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 or 0xFFFF0000 a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 0000000001110000 ld_p_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 dis "ld p, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 or 0xFFFF0000 p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 000000000DDD1SSS ld_int_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 dis "ld %s, %s" internal.D val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 mov val internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 0000000000111SSS ld_a_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 dis "ld a, %s" val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 0000000001111SSS ld_p_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 dis "ld p, %s" val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 000000001DDD0SSS ld_ext_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480 meta src internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 dis "ld al, %s" src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 dis "ld %s, %s" external.D src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 000000001DDD0011 ld_ext_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 meta src tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 dis "ld al, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 dis "ld %s, a" external.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 000000001DDD0111 ld_ext_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 meta src tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 dis "ld al, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 dis "ld %s, p" external.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 000000001DDD1SSS ld_ext_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 meta src val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 dis "ld al, %s" src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 dis "ld %s, %s" external.D src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 0000001B0DDDMMPP ld_int_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 dis "ld %s, (%s%s)" internal.D reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 mov val internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 0000001B0011MMPP ld_a_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 dis "ld a, (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 0000001B0111MMPP ld_p_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 dis "ld p, (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
549 0000001B0101MMPP ld_stack_ram
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 svp_ram_read M B P
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
551 dis "ld stack, (%s%s)" reg modestr
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 svp_push val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
554 000010000DDD0000 ld_int_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
555 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
556 dis "ld %s, %X" internal.D scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
557 mov scratch1 internal.D
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
558
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
559 0000100000000000 ld_n1_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
560 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
561 dis "ld -, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
562
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
563 0000100000110000 ld_a_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
564 local tmp 32
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
565 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
566 dis "ld a, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
567 lsl 16 scratch1 tmp
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
568 and 0xFFFF a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
569 or tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
570
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
571 0000100001010000 ld_stack_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
572 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
573 dis "ld stack, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
574 svp_push scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
575
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
576 0000100001110000 ld_p_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
577 local tmp 32
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
578 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
579 dis "ld p, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
580 lsl 16 scratch1 tmp
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
581 and 0xFFFF p p
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
582 or tmp p p
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
583
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
584 000010001DDD0000 ld_ext_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
585 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
586 dis "ld %s, %X", external.D, scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
587 meta src scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
588 svp_write_ext D
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
589 switch D
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
590 case 7
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
591 dis "ld al, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
592
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
593 default
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
594 dis "ld %s, %X" external.D scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
595 end
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
596
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
597 0100100FCCCC0000 call_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
598 svp_check_cond F C
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
599 svp_op_fetch
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
601 if istrue
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 svp_push pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603 mov scratch1 pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 0100110FCCCC0000 bra_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 svp_check_cond F C
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 svp_op_fetch
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
609 if istrue
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 mov scratch1 pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 end
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
612
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
613 svp_prog_ram_read
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
614 arg src 16
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 cycles 1
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
616 cmp 1024 src
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 if >=U
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
619 add src src scratch1
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620 ocall read_16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 else
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
623 mov iram.src scratch1
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 end
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
625
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
626 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
627 svp_prog_ram_read pc
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 add 1 pc pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630 svp_run_op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 svp_op_fetch
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 dispatch scratch1