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annotate segacd.h @ 2148:2da377ea932f

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Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
author Michael Pavone <pavone@retrodev.com>
date Sat, 26 Mar 2022 20:14:41 -0700
parents 9caebcfeac72
children 4fbe1e7c4a73
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1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
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1 #ifndef SEGACD_H_
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2 #define SEGACD_H_
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3 #include <stdint.h>
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8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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4 #include "genesis.h"
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
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5 #include "cdd_mcu.h"
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cfd53c94fffb Initial stab at RF5C164 emulation
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6 #include "rf5c164.h"
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2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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7
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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8 typedef struct {
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parents: 1503
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9 m68k_context *m68k;
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parents: 1503
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10 system_media *media;
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parents: 1503
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11 genesis_context *genesis;
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cd057d6fe030 Initial stab at subcode emulation
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12 uint16_t gate_array[0xC0];
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parents: 1503
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13 uint16_t *rom; //unaltered ROM, needed for mirrored locations
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parents: 1503
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14 uint16_t *rom_mut; //ROM with low 16-bit of HINT vector modified by register write
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parents: 1503
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15 uint16_t *prog_ram;
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parents: 1503
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16 uint16_t *word_ram;
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parents: 1503
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17 uint8_t *pcm_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents: 1503
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18 uint8_t *bram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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19 uint32_t stopwatch_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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20 uint32_t int2_cycle;
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2066
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21 uint32_t graphics_int_cycle;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents: 1503
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22 uint32_t periph_reset_cycle;
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2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
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23 uint32_t last_refresh_cycle;
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8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
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parents: 2066
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24 uint32_t graphics_cycle;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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25 uint32_t base;
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8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2066
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26 uint32_t graphics_x;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
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27 uint32_t graphics_y;
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28 uint32_t graphics_dx;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
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parents: 2066
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29 uint32_t graphics_dy;
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30 uint16_t graphics_dst_x;
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31 uint8_t graphics_pixels[4];
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parents: 1503
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32 uint8_t timer_pending;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents: 1503
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33 uint8_t timer_value;
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parents: 1503
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34 uint8_t busreq;
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parents: 1503
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35 uint8_t busack;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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36 uint8_t reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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37 uint8_t need_reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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38 uint8_t memptr_start_index;
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
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39 rf5c164 pcm;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2054
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40 lc8951 cdc;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
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41 cdd_mcu cdd;
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2069
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42 cdd_fader fader;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2061
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43 uint8_t cdc_dst_low;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
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44 uint8_t cdc_int_ack;
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
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parents: 2066
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45 uint8_t graphics_step;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
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parents: 2066
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46 uint8_t graphics_dst_y;
2104
ff32a90260c9 Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents: 2081
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47 uint8_t enter_debugger;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
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48 uint8_t main_has_word2m;
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49 uint8_t main_swap_request;
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50 uint8_t bank_toggle;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents: 2119
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51 uint8_t sub_paused_wordram;
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2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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52 } segacd_context;
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53
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
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54 segacd_context *alloc_configure_segacd(system_media *media, uint32_t opts, uint8_t force_region, rom_info *info);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents: 1503
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55 memmap_chunk *segacd_main_cpu_map(segacd_context *cd, uint8_t cart_boot, uint32_t *num_chunks);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents: 1503
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56 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen);
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parents: 1503
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57 void scd_run(segacd_context *cd, uint32_t cycle);
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parents: 1503
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58 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction);
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2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
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59
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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60 #endif //SEGACD_H_