repos/blastem: runtime.S annotate

annotate runtime.S @ 165:62b152811bae

Fix certain address modes with lea when the destination is not a native register

author	Mike Pavone <pavone@retrodev.com>
date	Sat, 05 Jan 2013 22:59:51 -0800
parents	69ac23d42897
children	7504200cac86

rev	line source
17 de0085d4ea40 Add asssembly runtime code stub Mike Pavone <pavone@retrodev.com> parents: diff changeset	1
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	2 .global handle_cycle_limit
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	3 .global do_sync
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	4 handle_cycle_limit:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	5 cmp 84(%rsi), %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	6 jb skip_sync
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	7 do_sync:
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	8 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	9 mov %rsi, %rdi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	10 call sync_components
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	11 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	12 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	13 skip_sync:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	14 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	15
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	16 .global handle_cycle_limit_int
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	17 handle_cycle_limit_int:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	18 cmp 88(%rsi), %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	19 jb skip_int
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	20 push %rcx
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	21 /* call print_int_dbg */
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	22 /* swap USP and SSP if not already in supervisor mode */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	23 bt $5, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	24 jc already_supervisor
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	25 mov 72(%rsi), %edi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	26 mov %r15d, 72(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	27 mov %edi, %r15d
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	28 already_supervisor:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	29 /* save status register on stack */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	30 sub $2, %r15d
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	31 mov %r15d, %edi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	32 call get_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	33 call m68k_write_word
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	34 /* update status register */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	35 andb $0xF8, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	36 mov 92(%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	37 or $0x20, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	38 or %cl, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	39 /* save PC */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	40 sub $4, %r15d
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	41 mov %r15d, %edi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	42 pop %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	43 call m68k_write_long_lowfirst
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	44 /* calculate interrupt vector address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	45 mov 92(%rsi), %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	46 shl $2, %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	47 add $0x60, %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	48 call m68k_read_long_scratch1
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	49 call m68k_native_addr_and_sync
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	50 add $24, %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	51 /* discard function return address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	52 pop %rdi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	53 jmp *%rcx
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	54 ret
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	55 skip_int:
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	56 cmp 84(%rsi), %eax
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	57 jnb do_sync
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	58 ret
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	59
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	60 .global m68k_trap
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	61 m68k_trap:
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	62 push %rdi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	63 push %rcx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	64 /* swap USP and SSP if not already in supervisor mode */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	65 bt $5, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	66 jc already_supervisor_trap
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	67 mov 72(%rsi), %edi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	68 mov %r15d, 72(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	69 mov %edi, %r15d
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	70 already_supervisor_trap:
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	71 /* save status register on stack */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	72 sub $2, %r15d
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	73 mov %r15d, %edi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	74 call get_sr
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	75 call m68k_write_word
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	76 /* update status register */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	77 andb $0xF8, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	78 mov 92(%rsi), %cl
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	79 or $0x20, %cl
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	80 or %cl, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	81 /* save PC */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	82 sub $4, %r15d
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	83 mov %r15d, %edi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	84 pop %rcx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	85 call m68k_write_long_lowfirst
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	86 /* calculate interrupt vector address */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	87 pop %rcx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	88 shl $2, %ecx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	89 add $0x80, %ecx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	90 call m68k_read_long_scratch1
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	91 call m68k_native_addr_and_sync
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	92 add $24, %eax
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	93 jmp *%rcx
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	94
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	95 int_dbg_msg:
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	96 .asciz "Executing Interrupt!"
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	97 print_int_dbg:
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	98 call m68k_save_context
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	99 push %rsi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	100 lea int_dbg_msg(%rip), %rdi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	101 call puts
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	102 pop %rsi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	103 call m68k_load_context
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	104 ret
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	105
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	106 .global get_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	107 get_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	108 mov 5(%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	109 shl $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	110 mov (%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	111 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	112 or %bl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	113 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	114 or %dl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	115 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	116 or %bh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	117 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	118 or %dh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	119 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	120
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	121 .global set_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	122 set_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	123 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	124 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	125 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	126 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	127 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	128 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	129 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	130 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	131 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	132 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	133 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	134 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	135 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	136 mov %cl, (%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	137 shr $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	138 mov %cl, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	139 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	140
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	141 .global set_ccr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	142 set_ccr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	143 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	144 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	145 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	146 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	147 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	148 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	149 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	150 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	151 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	152 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	153 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	154 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	155 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	156 mov %cl, (%rsi)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	157 ret
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	158
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	159 do_vdp_port_write:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	160 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	161 mov %rcx, %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	162 call vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	163 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	164 call m68k_load_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	165 ret
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	166
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	167 do_vdp_port_read:
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	168 mov %ecx, %edi
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	169 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	170 call vdp_port_read
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	171 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	172 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	173 mov 136(%rsi), %cx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	174 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	175
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	176 do_io_write:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	177 call m68k_save_context
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	178 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	179 mov %ecx, %edx
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	180 call io_write
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	181 mov %rax, %rsi
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	182 call m68k_load_context
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	183 ret
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	184 do_io_read:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	185 mov %ecx, %edi
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	186 and $0x1FFFF, %edi
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	187 call m68k_save_context
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	188 call io_read
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	189 mov %rax, %rsi
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	190 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	191 mov 136(%rsi), %cl
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	192 ret
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	193
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	194 do_io_write_w:
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	195 call m68k_save_context
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	196 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	197 mov %ecx, %edx
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	198 call io_write_w
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	199 mov %rax, %rsi
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	200 call m68k_load_context
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	201 ret
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	202 do_io_read_w:
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	203 mov %ecx, %edi
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	204 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	205 call m68k_save_context
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	206 call io_read_w
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	207 mov %rax, %rsi
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	208 call m68k_load_context
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	209 mov 136(%rsi), %cx
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	210 ret
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	211
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	212 bad_access_msg:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	213 .asciz "Program tried to access illegal 68K address %X\n"
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	214
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	215 .global m68k_write_word
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	216 .global try_fifo_write
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	217 m68k_write_word:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	218 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	219 and $0xFFFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	220 cmp $0x400000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	221 jbe cart_w
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	222 cmp $0xE00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	223 jae workram_w
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	224 cmp $0xC00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	225 jae vdp_psg_w
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	226 cmp $0xA00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	227 jb not_io_w
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	228 cmp $0xA12000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	229 jae not_io_w
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	230 jmp do_io_write_w
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	231 not_io_w:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	232 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	233 workram_w:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	234 and $0xFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	235 mov %cx, (%r9, %rdi)
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	236 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	237 cart_w:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	238 mov %cx, (%r8, %rdi)
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	239 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	240 vdp_psg_w:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	241 test $0x2700E0, %edi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	242 jnz crash
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	243 and $0x1F, %edi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	244 cmp $4, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	245 jb try_fifo_write
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	246 jmp do_vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	247 try_fifo_write:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	248 push %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	249 push %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	250 /* fetch VDP context pointer from 68K context */
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	251 mov 128(%rsi), %rdx
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	252 /* check DMA flag */
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	253 bt $6, 19(%rdx)
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	254 jc fifo_fallback
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	255 /* get fifo_cur and compare it to fifo_end */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	256 mov (%rdx), %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	257 cmp %rbx, 8(%rdx)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	258 /* bail out if fifo is full */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	259 je fifo_fallback
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	260 /* populate FIFO entry */
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	261 mov %cx, 6(%rbx) /* value */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	262 mov 16(%rdx), %cx
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	263 mov %cx, 4(%rbx) /* address */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	264 mov 18(%rdx), %cl
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	265 mov %cl, 8(%rbx) /* cd */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	266 movb $0, 9(%rbx) /* partial */
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	267 mov %eax, %ecx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	268 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	269 sub %eax, %ecx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	270 mov %ecx, (%rbx) /* cycle */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	271 /* update fifo_cur and store back in 68K context */
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	272 add $12, %rbx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	273 mov %rbx, (%rdx)
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	274 /* update address register */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	275 movzbw 35(%rdx), %bx
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	276 add %bx, 16(%rdx)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	277 /* clear pending flag */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	278 andb $0xEF, 19(%rdx)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	279 pop %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	280 pop %rdx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	281 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	282 fifo_fallback:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	283 pop %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	284 pop %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	285 jmp do_vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	286 crash:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	287 mov %edi, %esi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	288 lea bad_access_msg(%rip), %rdi
160 69ac23d42897 Fix crash in printf from "crash" function due to lack of clearing rax Mike Pavone <pavone@retrodev.com> parents: 153 diff changeset	289 xor %rax, %rax
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	290 call printf
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	291 mov $1, %rdi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	292 call exit
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	293
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	294 .global m68k_write_byte
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	295 m68k_write_byte:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	296 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	297 and $0xFFFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	298 cmp $0x400000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	299 jbe cart_wb
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	300 cmp $0xE00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	301 jae workram_wb
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	302 cmp $0xC00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	303 jae vdp_psg_wb
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	304 cmp $0xA00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	305 jb not_io_wb
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	306 cmp $0xA12000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	307 jae not_io_wb
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	308 jmp do_io_write
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	309 not_io_wb:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	310 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	311 workram_wb:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	312 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	313 xor $1, %edi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	314 and $0xFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	315 mov %cl, (%r9, %rdi)
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	316 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	317 cart_wb:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	318 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	319 xor $1, %edi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	320 mov %cl, (%r8, %rdi)
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	321 ret
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	322 vdp_psg_wb:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	323 push %rdx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	324 mov %cl, %dl
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	325 and $0xFF, %cx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	326 shl $8, %dx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	327 or %dx, %cx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	328 pop %rdx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	329 jmp vdp_psg_w
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	330
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	331 .global m68k_write_long_lowfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	332 m68k_write_long_lowfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	333 push %rdi
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	334 push %rcx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	335 add $2, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	336 call m68k_write_word
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	337 pop %rcx
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	338 pop %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	339 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	340 jmp m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	341
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	342 .global m68k_write_long_highfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	343 m68k_write_long_highfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	344 push %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	345 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	346 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	347 call m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	348 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	349 pop %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	350 add $2, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	351 jmp m68k_write_word
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	352
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	353 inccycles:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	354 cmp %rbp, %rax
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	355 jnb do_limit
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	356 add $4, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	357 ret
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	358 do_limit:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	359 push %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	360 push %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	361 call handle_cycle_limit
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	362 pop %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	363 pop %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	364 add $4, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	365 ret
17 de0085d4ea40 Add asssembly runtime code stub Mike Pavone <pavone@retrodev.com> parents: diff changeset	366
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	367 .global m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	368 m68k_read_word_scratch1:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	369 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	370 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	371 cmp $0x400000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	372 jbe cart
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	373 cmp $0xE00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	374 jae workram
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	375 cmp $0xC00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	376 jae vdp_psg
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	377 cmp $0xA00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	378 jb not_io
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	379 cmp $0xA12000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	380 jae not_io
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	381 call do_io_read_w
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	382 ret
7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	383 not_io:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	384 xor %cx, %cx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	385 dec %cx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	386 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	387 workram:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	388 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	389 mov (%r9, %rcx), %cx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	390 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	391 vdp_psg:
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	392 test $0x2700E0, %ecx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	393 jnz crash
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	394 and $0x1F, %ecx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	395 jmp do_vdp_port_read
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	396 cart:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	397 mov (%r8, %rcx), %cx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	398 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	399
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	400 .global m68k_read_long_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	401 m68k_read_long_scratch1:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	402 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	403 call m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	404 mov %cx, %di
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	405 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	406 add $2, %ecx
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	407 push %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	408 call m68k_read_word_scratch1
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	409 pop %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	410 and $0xFFFF, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	411 shl $16, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	412 or %edi, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	413 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	414
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	415 .global m68k_read_byte_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	416 m68k_read_byte_scratch1:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	417 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	418 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	419 cmp $0x400000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	420 jbe cart_b
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	421 cmp $0xE00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	422 jae workram_b
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	423 cmp $0xC00000, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	424 jae vdp_psg_b
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	425 cmp $0xA00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	426 jb not_io_b
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	427 cmp $0xA12000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	428 jae not_io_b
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	429 jmp do_io_read
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	430 not_io_b:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	431 xor %cl, %cl
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	432 dec %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	433 ret
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	434 vdp_psg_b:
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	435 test $0x2700E0, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	436 jnz crash
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	437 and $0x1F, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	438 bt $0, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	439 jnc vdp_swap
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	440 jmp do_vdp_port_read
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	441 vdp_swap:
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	442 call do_vdp_port_read
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	443 shr $8, %cx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	444 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	445 workram_b:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	446 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	447 xor $1, %ecx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	448 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	449 mov (%r9, %rcx), %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	450 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	451 cart_b:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	452 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	453 xor $1, %ecx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	454 mov (%r8, %rcx), %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	455 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	456
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	457 .global m68k_modified_ret_addr
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	458 m68k_modified_ret_addr:
145 15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	459 add $16, %rsp
15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	460 call m68k_native_addr
15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	461 jmp *%rcx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	462
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	463 dyn_addr_msg:
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	464 .asciz "Program needs dynamically calculated native address\n"
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	465
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	466 .global m68k_native_addr_and_sync
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	467 m68k_native_addr_and_sync:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	468 call m68k_save_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	469 push %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	470 mov %rsi, %rdi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	471 call sync_components
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	472 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	473 push %rax
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	474 mov %rax, %rdi
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	475 call get_native_address_trans
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	476 mov %rax, %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	477 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	478 call m68k_load_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	479 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	480
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	481 .global m68k_native_addr
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	482 m68k_native_addr:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	483 call m68k_save_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	484 push %rsi
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	485 mov %rsi, %rdi
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	486 mov %ecx, %esi
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	487 call get_native_address_trans
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	488 mov %rax, %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	489 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	490 call m68k_load_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	491 ret
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	492
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	493 .global m68k_save_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	494 m68k_save_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	495 mov %bl, 1(%rsi) /* N Flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	496 mov %bh, 2(%rsi) /* V flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	497 mov %dl, 3(%rsi) /* Z flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	498 mov %dh, 4(%rsi) /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	499 mov %r10d, 8(%rsi) /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	500 mov %r11d, 12(%rsi) /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	501 mov %r12d, 16(%rsi) /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	502 mov %r13d, 40(%rsi) /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	503 mov %r14d, 44(%rsi) /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	504 mov %r15d, 68(%rsi) /* a7 */
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	505 mov %eax, 80(%rsi) /* current cycle count */
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	506 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	507
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	508 .global m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	509 m68k_load_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	510 mov 1(%rsi), %bl /* N Flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	511 mov 2(%rsi), %bh /* V flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	512 mov 3(%rsi), %dl /* Z flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	513 mov 4(%rsi), %dh /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	514 mov 8(%rsi), %r10d /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	515 mov 12(%rsi), %r11d /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	516 mov 16(%rsi), %r12d /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	517 mov 40(%rsi), %r13d /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	518 mov 44(%rsi), %r14d /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	519 mov 68(%rsi), %r15d /* a7 */
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	520 mov 76(%rsi), %ebp /* target cycle count */
7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	521 mov 80(%rsi), %eax /* current cycle count */
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	522 mov 96(%rsi), %r8d /* cartridge address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	523 mov 104(%rsi), %r9d /* work ram address */
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	524 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	525
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	526 .global m68k_start_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	527 m68k_start_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	528 call m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	529 jmp *%rdi

Mercurial > repos > blastem

annotate runtime.S @ 165:62b152811bae