Mercurial > repos > blastem
annotate z80_to_x86.c @ 252:63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
author | Mike Pavone <pavone@retrodev.com> |
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date | Mon, 29 Apr 2013 21:46:48 -0700 |
parents | 5f1b68cecfc7 |
children | 3b34deba4ca0 |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 void z80_read_byte(); |
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19 void z80_read_word(); |
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20 void z80_write_byte(); |
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21 void z80_write_word_highfirst(); |
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22 void z80_write_word_lowfirst(); |
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23 void z80_save_context(); |
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24 void z80_native_addr(); |
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25 void z80_do_sync(); |
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26 void z80_handle_cycle_limit_int(); |
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27 void z80_retrans_stub(); |
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28 |
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29 uint8_t z80_size(z80inst * inst) |
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30 { |
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31 uint8_t reg = (inst->reg & 0x1F); |
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32 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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33 return reg < Z80_BC ? SZ_B : SZ_W; |
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34 } |
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35 //TODO: Handle any necessary special cases |
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36 return SZ_B; |
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37 } |
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38 |
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39 uint8_t z80_high_reg(uint8_t reg) |
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40 { |
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41 switch(reg) |
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42 { |
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43 case Z80_C: |
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44 case Z80_BC: |
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45 return Z80_B; |
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46 case Z80_E: |
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47 case Z80_DE: |
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48 return Z80_D; |
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49 case Z80_L: |
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50 case Z80_HL: |
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51 return Z80_H; |
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52 case Z80_IXL: |
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53 case Z80_IX: |
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54 return Z80_IXH; |
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55 case Z80_IYL: |
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56 case Z80_IY: |
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57 return Z80_IYH; |
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58 default: |
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59 return Z80_UNUSED; |
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60 } |
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61 } |
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62 |
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63 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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64 { |
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65 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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66 } |
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67 |
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68 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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69 { |
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70 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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71 uint8_t * jmp_off = dst+1; |
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72 dst = jcc(dst, CC_NC, dst + 7); |
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73 dst = mov_ir(dst, address, SCRATCH2, SZ_W); |
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74 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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75 *jmp_off = dst - (jmp_off+1); |
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76 return dst; |
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77 } |
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78 |
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79 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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80 { |
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81 if (inst->reg == Z80_USE_IMMED) { |
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82 ea->mode = MODE_IMMED; |
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83 ea->disp = inst->immed; |
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84 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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85 ea->mode = MODE_UNUSED; |
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86 } else { |
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87 ea->mode = MODE_REG_DIRECT; |
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88 if (inst->reg == Z80_IYH) { |
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89 ea->base = opts->regs[Z80_IYL]; |
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90 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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91 } else { |
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92 ea->base = opts->regs[inst->reg]; |
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93 } |
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94 } |
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95 return dst; |
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96 } |
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98 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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99 { |
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100 if (inst->reg == Z80_IYH) { |
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101 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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102 } |
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103 return dst; |
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104 } |
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106 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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107 { |
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108 uint8_t size, reg, areg; |
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109 ea->mode = MODE_REG_DIRECT; |
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110 areg = read ? SCRATCH1 : SCRATCH2; |
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111 switch(inst->addr_mode & 0x1F) |
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112 { |
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113 case Z80_REG: |
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114 if (inst->ea_reg == Z80_IYH) { |
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115 ea->base = opts->regs[Z80_IYL]; |
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116 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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117 } else { |
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118 ea->base = opts->regs[inst->ea_reg]; |
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119 } |
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120 break; |
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121 case Z80_REG_INDIRECT: |
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122 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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123 size = z80_size(inst); |
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124 if (read) { |
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125 if (modify) { |
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126 dst = push_r(dst, SCRATCH1); |
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127 } |
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128 if (size == SZ_B) { |
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129 dst = call(dst, (uint8_t *)z80_read_byte); |
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130 } else { |
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131 dst = call(dst, (uint8_t *)z80_read_word); |
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132 } |
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133 if (modify) { |
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134 dst = pop_r(dst, SCRATCH2); |
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135 } |
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136 } |
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137 ea->base = SCRATCH1; |
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138 break; |
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139 case Z80_IMMED: |
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140 ea->mode = MODE_IMMED; |
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141 ea->disp = inst->immed; |
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142 break; |
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143 case Z80_IMMED_INDIRECT: |
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144 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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145 size = z80_size(inst); |
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146 if (read) { |
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147 if (modify) { |
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148 dst = push_r(dst, SCRATCH1); |
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149 } |
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150 if (size == SZ_B) { |
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151 dst = call(dst, (uint8_t *)z80_read_byte); |
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152 } else { |
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153 dst = call(dst, (uint8_t *)z80_read_word); |
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154 } |
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155 if (modify) { |
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156 dst = pop_r(dst, SCRATCH2); |
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157 } |
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158 } |
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159 ea->base = SCRATCH1; |
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160 break; |
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161 case Z80_IX_DISPLACE: |
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162 case Z80_IY_DISPLACE: |
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163 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
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164 dst = mov_rr(dst, reg, areg, SZ_W); |
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165 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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166 size = z80_size(inst); |
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167 if (read) { |
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168 if (modify) { |
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169 dst = push_r(dst, SCRATCH1); |
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170 } |
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171 if (size == SZ_B) { |
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172 dst = call(dst, (uint8_t *)z80_read_byte); |
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173 } else { |
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174 dst = call(dst, (uint8_t *)z80_read_word); |
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175 } |
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176 if (modify) { |
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177 dst = pop_r(dst, SCRATCH2); |
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178 } |
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179 } |
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180 break; |
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181 case Z80_UNUSED: |
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182 ea->mode = MODE_UNUSED; |
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183 break; |
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184 default: |
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185 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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186 exit(1); |
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187 } |
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188 return dst; |
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189 } |
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190 |
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191 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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192 { |
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193 if (inst->addr_mode == Z80_REG && inst->ea_reg == Z80_IYH) { |
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194 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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195 } |
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196 return dst; |
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197 } |
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198 |
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199 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
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200 { |
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201 if (z80_size(inst) == SZ_B) { |
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202 dst = call(dst, (uint8_t *)z80_write_byte); |
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203 } else { |
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204 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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205 } |
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206 return dst; |
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207 } |
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208 |
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209 enum { |
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210 DONT_READ=0, |
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211 READ |
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212 }; |
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213 |
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214 enum { |
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215 DONT_MODIFY=0, |
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216 MODIFY |
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217 }; |
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218 |
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219 uint8_t zf_off(uint8_t flag) |
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220 { |
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221 return offsetof(z80_context, flags) + flag; |
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222 } |
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223 |
241
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224 uint8_t zaf_off(uint8_t flag) |
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225 { |
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226 return offsetof(z80_context, alt_flags) + flag; |
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227 } |
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228 |
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229 uint8_t zar_off(uint8_t reg) |
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230 { |
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231 return offsetof(z80_context, alt_regs) + reg; |
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232 } |
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233 |
235
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234 void z80_print_regs_exit(z80_context * context) |
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235 { |
243
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236 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
235
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237 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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238 context->regs[Z80_D], context->regs[Z80_E], |
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239 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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240 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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241 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
243
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242 context->sp, context->im, context->iff1, context->iff2); |
241
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243 puts("--Alternate Regs--"); |
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244 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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245 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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246 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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247 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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248 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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249 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
235
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250 exit(0); |
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251 } |
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252 |
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253 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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254 { |
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255 uint32_t cycles; |
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256 x86_ea src_op, dst_op; |
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257 uint8_t size; |
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258 x86_z80_options *opts = context->options; |
250
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259 dst = z80_check_cycles_int(dst, address); |
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260 switch(inst->op) |
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261 { |
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262 case Z80_LD: |
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263 size = z80_size(inst); |
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264 switch (inst->addr_mode & 0x1F) |
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265 { |
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266 case Z80_REG: |
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267 case Z80_REG_INDIRECT: |
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268 cycles = size == SZ_B ? 4 : 6; |
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269 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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270 cycles += 4; |
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271 } |
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272 break; |
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273 case Z80_IMMED: |
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274 cycles = size == SZ_B ? 7 : 10; |
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275 break; |
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276 case Z80_IMMED_INDIRECT: |
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277 cycles = 10; |
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278 break; |
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279 case Z80_IX_DISPLACE: |
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280 case Z80_IY_DISPLACE: |
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281 cycles = 12; |
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282 break; |
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283 } |
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284 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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285 cycles += 4; |
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286 } |
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287 dst = zcycles(dst, cycles); |
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288 if (inst->addr_mode & Z80_DIR) { |
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289 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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290 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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291 } else { |
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292 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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293 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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294 } |
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295 if (src_op.mode == MODE_REG_DIRECT) { |
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296 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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297 } else { |
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298 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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299 } |
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300 dst = z80_save_reg(dst, inst, opts); |
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301 dst = z80_save_ea(dst, inst, opts); |
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302 if (inst->addr_mode & Z80_DIR) { |
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303 dst = z80_save_result(dst, inst); |
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304 } |
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305 break; |
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306 case Z80_PUSH: |
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307 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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308 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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309 if (inst->reg == Z80_AF) { |
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310 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH2, SZ_B); |
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311 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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312 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH2, SZ_B); |
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313 dst = shl_ir(dst, 2, SCRATCH2, SZ_B); |
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314 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH2, SZ_B); |
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315 dst = shl_ir(dst, 2, SCRATCH2, SZ_B); |
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316 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH2, SZ_B); |
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317 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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318 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH2, SZ_B); |
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319 dst = shl_ir(dst, 1, SCRATCH2, SZ_B); |
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320 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH2, SZ_B); |
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321 dst = shl_ir(dst, 8, SCRATCH2, SZ_W); |
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322 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); |
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323 } else { |
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324 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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325 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_W); |
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326 } |
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327 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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328 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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329 //no call to save_z80_reg needed since there's no chance we'll use the only |
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330 //the upper half of a register pair |
213
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331 break; |
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332 case Z80_POP: |
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333 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
235
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334 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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335 dst = call(dst, (uint8_t *)z80_read_word); |
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336 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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337 if (inst->reg == Z80_AF) { |
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338 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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339 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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340 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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341 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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342 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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343 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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344 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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345 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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346 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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347 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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348 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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349 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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350 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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351 } else { |
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352 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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353 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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354 } |
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355 //no call to save_z80_reg needed since there's no chance we'll use the only |
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356 //the upper half of a register pair |
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357 break; |
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358 case Z80_EX: |
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359 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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360 cycles = 4; |
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361 } else { |
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362 cycles = 8; |
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363 } |
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364 dst = zcycles(dst, cycles); |
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365 if (inst->addr_mode == Z80_REG) { |
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366 if(inst->reg == Z80_AF) { |
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367 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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368 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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369 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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370 |
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371 //Flags are currently word aligned, so we can move |
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372 //them efficiently a word at a time |
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373 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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374 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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375 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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376 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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377 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zf_off(f), SZ_W); |
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378 } |
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379 } else { |
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380 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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381 } |
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382 } else { |
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383 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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384 dst = call(dst, (uint8_t *)z80_read_byte); |
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385 dst = mov_rr(dst, opts->regs[inst->reg], SCRATCH2, SZ_B); |
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386 dst = mov_rr(dst, SCRATCH1, opts->regs[inst->reg], SZ_B); |
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387 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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388 dst = call(dst, (uint8_t *)z80_write_byte); |
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389 dst = zcycles(dst, 1); |
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390 uint8_t high_reg = z80_high_reg(inst->reg); |
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391 uint8_t use_reg; |
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392 //even though some of the upper halves can be used directly |
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393 //the limitations on mixing *H regs with the REX prefix |
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394 //prevent us from taking advantage of it |
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395 use_reg = opts->regs[inst->reg]; |
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396 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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397 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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398 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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399 dst = call(dst, (uint8_t *)z80_read_byte); |
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400 dst = mov_rr(dst, use_reg, SCRATCH2, SZ_B); |
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401 dst = mov_rr(dst, SCRATCH1, use_reg, SZ_B); |
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402 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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403 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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404 dst = call(dst, (uint8_t *)z80_write_byte); |
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405 //restore reg to normal rotation |
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406 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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407 dst = zcycles(dst, 2); |
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408 } |
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409 break; |
213
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410 case Z80_EXX: |
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411 dst = zcycles(dst, 4); |
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412 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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413 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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414 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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415 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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416 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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417 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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418 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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419 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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|
420 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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239
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changeset
|
421 break; |
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|
422 /*case Z80_LDI: |
213
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|
423 case Z80_LDIR: |
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changeset
|
424 case Z80_LDD: |
4d4559b04c59
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changeset
|
425 case Z80_LDDR: |
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changeset
|
426 case Z80_CPI: |
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diff
changeset
|
427 case Z80_CPIR: |
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diff
changeset
|
428 case Z80_CPD: |
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changeset
|
429 case Z80_CPDR: |
4d4559b04c59
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diff
changeset
|
430 break;*/ |
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changeset
|
431 case Z80_ADD: |
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changeset
|
432 cycles = 4; |
235
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433 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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changeset
|
434 cycles += 12; |
4d4559b04c59
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changeset
|
435 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
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changeset
|
436 cycles += 3; |
4d4559b04c59
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|
437 } else if(z80_size(inst) == SZ_W) { |
4d4559b04c59
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changeset
|
438 cycles += 4; |
4d4559b04c59
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changeset
|
439 } |
4d4559b04c59
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changeset
|
440 dst = zcycles(dst, cycles); |
4d4559b04c59
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changeset
|
441 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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changeset
|
442 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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changeset
|
443 if (src_op.mode == MODE_REG_DIRECT) { |
4d4559b04c59
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changeset
|
444 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
445 } else { |
4d4559b04c59
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diff
changeset
|
446 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
447 } |
4d4559b04c59
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diff
changeset
|
448 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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changeset
|
449 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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changeset
|
450 //TODO: Implement half-carry flag |
4d4559b04c59
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changeset
|
451 if (z80_size(inst) == SZ_B) { |
235
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452 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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453 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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changeset
|
454 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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changeset
|
455 } |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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diff
changeset
|
457 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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changeset
|
458 break; |
248
9c7a3db7bcd0
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|
459 case Z80_ADC: |
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changeset
|
460 cycles = 4; |
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changeset
|
461 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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462 cycles += 12; |
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247
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changeset
|
463 } else if(inst->addr_mode == Z80_IMMED) { |
9c7a3db7bcd0
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247
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changeset
|
464 cycles += 3; |
9c7a3db7bcd0
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changeset
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465 } else if(z80_size(inst) == SZ_W) { |
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changeset
|
466 cycles += 4; |
9c7a3db7bcd0
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changeset
|
467 } |
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Implement ADC and SBC in Z80 core (untested)
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247
diff
changeset
|
468 dst = zcycles(dst, cycles); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
diff
changeset
|
469 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
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changeset
|
470 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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Implement ADC and SBC in Z80 core (untested)
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247
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changeset
|
471 if (src_op.mode == MODE_REG_DIRECT) { |
9c7a3db7bcd0
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247
diff
changeset
|
472 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
473 } else { |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
diff
changeset
|
474 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
475 } |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
476 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
9c7a3db7bcd0
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changeset
|
477 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
478 //TODO: Implement half-carry flag |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
479 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
480 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
481 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
482 dst = z80_save_reg(dst, inst, opts); |
9c7a3db7bcd0
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changeset
|
483 dst = z80_save_ea(dst, inst, opts); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
484 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
485 case Z80_SUB: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
486 cycles = 4; |
235
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213
diff
changeset
|
487 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
488 cycles += 12; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
489 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
490 cycles += 3; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 dst = zcycles(dst, cycles); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 if (src_op.mode == MODE_REG_DIRECT) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
497 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
498 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
500 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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changeset
|
501 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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Get Z80 core working for simple programs
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213
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changeset
|
502 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
503 //TODO: Implement half-carry flag |
235
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213
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changeset
|
504 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
505 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
506 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
507 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
508 break; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
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changeset
|
509 case Z80_SBC: |
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Implement ADC and SBC in Z80 core (untested)
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510 cycles = 4; |
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511 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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512 cycles += 12; |
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513 } else if(inst->addr_mode == Z80_IMMED) { |
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514 cycles += 3; |
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515 } else if(z80_size(inst) == SZ_W) { |
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516 cycles += 4; |
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517 } |
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518 dst = zcycles(dst, cycles); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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519 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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520 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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521 if (src_op.mode == MODE_REG_DIRECT) { |
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522 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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523 } else { |
9c7a3db7bcd0
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524 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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525 } |
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526 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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527 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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528 //TODO: Implement half-carry flag |
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529 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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530 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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531 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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532 dst = z80_save_reg(dst, inst, opts); |
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533 dst = z80_save_ea(dst, inst, opts); |
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534 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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535 case Z80_AND: |
236
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536 cycles = 4; |
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537 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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538 cycles += 12; |
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539 } else if(inst->addr_mode == Z80_IMMED) { |
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540 cycles += 3; |
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541 } else if(z80_size(inst) == SZ_W) { |
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542 cycles += 4; |
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543 } |
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544 dst = zcycles(dst, cycles); |
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545 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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546 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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547 if (src_op.mode == MODE_REG_DIRECT) { |
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548 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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549 } else { |
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235
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changeset
|
550 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
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551 } |
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552 //TODO: Cleanup flags |
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553 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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554 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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235
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555 //TODO: Implement half-carry flag |
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556 if (z80_size(inst) == SZ_B) { |
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235
diff
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|
557 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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235
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558 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
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559 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
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|
560 } |
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|
561 dst = z80_save_reg(dst, inst, opts); |
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changeset
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562 dst = z80_save_ea(dst, inst, opts); |
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563 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
564 case Z80_OR: |
236
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diff
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|
565 cycles = 4; |
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235
diff
changeset
|
566 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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235
diff
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|
567 cycles += 12; |
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235
diff
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|
568 } else if(inst->addr_mode == Z80_IMMED) { |
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235
diff
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|
569 cycles += 3; |
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235
diff
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|
570 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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235
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571 cycles += 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
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|
572 } |
19fb3523a9e5
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|
573 dst = zcycles(dst, cycles); |
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235
diff
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|
574 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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Mike Pavone <pavone@retrodev.com>
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235
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|
575 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
576 if (src_op.mode == MODE_REG_DIRECT) { |
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577 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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235
diff
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|
578 } else { |
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235
diff
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|
579 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
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|
580 } |
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235
diff
changeset
|
581 //TODO: Cleanup flags |
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235
diff
changeset
|
582 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
19fb3523a9e5
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parents:
235
diff
changeset
|
583 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
19fb3523a9e5
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parents:
235
diff
changeset
|
584 //TODO: Implement half-carry flag |
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235
diff
changeset
|
585 if (z80_size(inst) == SZ_B) { |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
586 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
19fb3523a9e5
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235
diff
changeset
|
587 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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parents:
235
diff
changeset
|
588 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
19fb3523a9e5
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235
diff
changeset
|
589 } |
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235
diff
changeset
|
590 dst = z80_save_reg(dst, inst, opts); |
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235
diff
changeset
|
591 dst = z80_save_ea(dst, inst, opts); |
19fb3523a9e5
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parents:
235
diff
changeset
|
592 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
593 case Z80_XOR: |
236
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
594 cycles = 4; |
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parents:
235
diff
changeset
|
595 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
596 cycles += 12; |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
597 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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235
diff
changeset
|
598 cycles += 3; |
19fb3523a9e5
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235
diff
changeset
|
599 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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235
diff
changeset
|
600 cycles += 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
601 } |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
602 dst = zcycles(dst, cycles); |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
603 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
604 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
605 if (src_op.mode == MODE_REG_DIRECT) { |
19fb3523a9e5
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235
diff
changeset
|
606 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
607 } else { |
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235
diff
changeset
|
608 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
changeset
|
609 } |
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235
diff
changeset
|
610 //TODO: Cleanup flags |
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235
diff
changeset
|
611 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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235
diff
changeset
|
612 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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235
diff
changeset
|
613 //TODO: Implement half-carry flag |
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235
diff
changeset
|
614 if (z80_size(inst) == SZ_B) { |
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235
diff
changeset
|
615 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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235
diff
changeset
|
616 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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617 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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618 } |
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619 dst = z80_save_reg(dst, inst, opts); |
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620 dst = z80_save_ea(dst, inst, opts); |
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621 break; |
242 | 622 case Z80_CP: |
623 cycles = 4; | |
624 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
625 cycles += 12; | |
626 } else if(inst->addr_mode == Z80_IMMED) { | |
627 cycles += 3; | |
628 } | |
629 dst = zcycles(dst, cycles); | |
630 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
631 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
632 if (src_op.mode == MODE_REG_DIRECT) { | |
633 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
634 } else { | |
635 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
636 } | |
637 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
638 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
639 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
640 //TODO: Implement half-carry flag | |
641 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
642 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
643 dst = z80_save_reg(dst, inst, opts); | |
644 dst = z80_save_ea(dst, inst, opts); | |
645 break; | |
213
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646 case Z80_INC: |
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647 cycles = 4; |
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648 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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649 cycles += 6; |
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650 } else if(z80_size(inst) == SZ_W) { |
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651 cycles += 2; |
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652 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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653 cycles += 4; |
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654 } |
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655 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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656 if (dst_op.mode == MODE_UNUSED) { |
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657 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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658 } |
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659 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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660 if (z80_size(inst) == SZ_B) { |
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661 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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662 //TODO: Implement half-carry flag |
235
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663 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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664 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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665 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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666 } |
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667 dst = z80_save_reg(dst, inst, opts); |
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668 dst = z80_save_ea(dst, inst, opts); |
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669 break; |
236
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670 case Z80_DEC: |
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671 cycles = 4; |
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672 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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673 cycles += 6; |
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674 } else if(z80_size(inst) == SZ_W) { |
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675 cycles += 2; |
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676 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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677 cycles += 4; |
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678 } |
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679 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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680 if (dst_op.mode == MODE_UNUSED) { |
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681 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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682 } |
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683 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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684 if (z80_size(inst) == SZ_B) { |
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685 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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686 //TODO: Implement half-carry flag |
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687 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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688 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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689 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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690 } |
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691 dst = z80_save_reg(dst, inst, opts); |
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692 dst = z80_save_ea(dst, inst, opts); |
213
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693 break; |
236
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694 /*case Z80_DAA: |
213
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695 case Z80_CPL: |
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696 case Z80_NEG: |
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697 case Z80_CCF: |
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698 case Z80_SCF:*/ |
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699 case Z80_NOP: |
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700 if (inst->immed == 42) { |
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701 dst = call(dst, (uint8_t *)z80_save_context); |
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702 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
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703 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
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704 } else { |
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705 dst = zcycles(dst, 4 * inst->immed); |
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|
706 } |
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|
707 break; |
243
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708 //case Z80_HALT: |
213
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|
709 case Z80_DI: |
243
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|
710 dst = zcycles(dst, 4); |
2f069a0b487e
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242
diff
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|
711 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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|
712 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
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248
diff
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|
713 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
2f069a0b487e
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242
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|
714 break; |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
715 case Z80_EI: |
243
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|
716 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
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|
717 dst = zcycles(dst, 4); |
2f069a0b487e
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242
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|
718 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
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242
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|
719 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
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248
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|
720 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
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242
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|
721 break; |
213
4d4559b04c59
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diff
changeset
|
722 case Z80_IM: |
243
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242
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|
723 dst = zcycles(dst, 4); |
2f069a0b487e
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242
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|
724 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
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242
diff
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|
725 break; |
247
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246
diff
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|
726 case Z80_RLC: |
682e505f5757
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246
diff
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|
727 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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|
728 dst = zcycles(dst, cycles); |
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246
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|
729 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
730 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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diff
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|
731 dst = zcycles(dst, 1); |
682e505f5757
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246
diff
changeset
|
732 } else { |
682e505f5757
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246
diff
changeset
|
733 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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246
diff
changeset
|
734 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
735 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
736 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
737 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
738 //TODO: Implement half-carry flag |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
739 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
740 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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246
diff
changeset
|
741 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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246
diff
changeset
|
742 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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parents:
246
diff
changeset
|
743 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
744 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
745 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
746 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
747 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
748 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 case Z80_RL: |
247
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Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
750 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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246
diff
changeset
|
751 dst = zcycles(dst, cycles); |
682e505f5757
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parents:
246
diff
changeset
|
752 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
753 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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parents:
246
diff
changeset
|
754 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
755 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
756 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
757 } |
682e505f5757
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246
diff
changeset
|
758 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
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246
diff
changeset
|
759 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
760 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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246
diff
changeset
|
761 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
762 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
763 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
764 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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246
diff
changeset
|
765 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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246
diff
changeset
|
766 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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246
diff
changeset
|
767 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
768 dst = z80_save_result(dst, inst); |
682e505f5757
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246
diff
changeset
|
769 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
770 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
771 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
772 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
773 case Z80_RRC: |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
774 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
775 dst = zcycles(dst, cycles); |
682e505f5757
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246
diff
changeset
|
776 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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parents:
246
diff
changeset
|
777 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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246
diff
changeset
|
778 dst = zcycles(dst, 1); |
682e505f5757
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246
diff
changeset
|
779 } else { |
682e505f5757
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246
diff
changeset
|
780 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
781 } |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
782 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
783 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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246
diff
changeset
|
784 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
785 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
786 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
787 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
788 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
789 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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246
diff
changeset
|
790 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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parents:
246
diff
changeset
|
791 dst = z80_save_result(dst, inst); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
792 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
793 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
794 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
795 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 case Z80_RR: |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
797 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
798 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
799 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
800 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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parents:
246
diff
changeset
|
801 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
802 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
803 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
804 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
805 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
806 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
807 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
808 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
809 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
810 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
811 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
812 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
813 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
814 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
815 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
816 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
817 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
818 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
819 break; |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
820 /*case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 case Z80_SRA: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 case Z80_SLL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 case Z80_SRL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 case Z80_RLD: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
825 case Z80_RRD:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 case Z80_BIT: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
827 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
828 dst = zcycles(dst, cycles); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
829 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
830 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
831 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
832 dst = zcycles(dst, 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
833 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
834 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
835 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
836 break; |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
837 case Z80_SET: |
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|
838 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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839 dst = zcycles(dst, cycles); |
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840 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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841 if (inst->addr_mode != Z80_REG) { |
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842 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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diff
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|
843 dst = zcycles(dst, 1); |
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diff
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|
844 } |
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845 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
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|
846 if (inst->addr_mode != Z80_REG) { |
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|
847 dst = z80_save_result(dst, inst); |
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|
848 } |
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diff
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|
849 break; |
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|
850 case Z80_RES: |
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851 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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852 dst = zcycles(dst, cycles); |
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853 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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|
854 if (inst->addr_mode != Z80_REG) { |
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|
855 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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856 dst = zcycles(dst, 1); |
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|
857 } |
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|
858 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
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|
859 if (inst->addr_mode != Z80_REG) { |
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860 dst = z80_save_result(dst, inst); |
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|
861 } |
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|
862 break; |
236
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863 case Z80_JP: { |
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|
864 cycles = 4; |
239
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|
865 if (inst->addr_mode != Z80_REG) { |
236
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|
866 cycles += 6; |
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867 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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868 cycles += 4; |
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|
869 } |
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|
870 dst = zcycles(dst, cycles); |
239
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|
871 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
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872 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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873 if (!call_dst) { |
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874 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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|
875 //fake address to force large displacement |
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|
876 call_dst = dst + 256; |
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235
diff
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|
877 } |
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|
878 dst = jmp(dst, call_dst); |
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|
879 } else { |
239
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|
880 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
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|
881 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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|
882 } else { |
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|
883 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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|
884 } |
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|
885 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
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|
886 dst = jmp_r(dst, SCRATCH1); |
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|
887 } |
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|
888 break; |
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|
889 } |
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|
890 case Z80_JPCC: { |
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|
891 dst = zcycles(dst, 7);//T States: 4,3 |
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|
892 uint8_t cond = CC_Z; |
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|
893 switch (inst->reg) |
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235
diff
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|
894 { |
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|
895 case Z80_CC_NZ: |
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|
896 cond = CC_NZ; |
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|
897 case Z80_CC_Z: |
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|
898 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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235
diff
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|
899 break; |
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|
900 case Z80_CC_NC: |
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|
901 cond = CC_NZ; |
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|
902 case Z80_CC_C: |
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|
903 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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235
diff
changeset
|
904 break; |
238
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236
diff
changeset
|
905 case Z80_CC_PO: |
827ebce557bf
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236
diff
changeset
|
906 cond = CC_NZ; |
827ebce557bf
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236
diff
changeset
|
907 case Z80_CC_PE: |
827ebce557bf
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236
diff
changeset
|
908 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
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236
diff
changeset
|
909 break; |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
910 case Z80_CC_P: |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
911 case Z80_CC_M: |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
912 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
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236
diff
changeset
|
913 break; |
236
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235
diff
changeset
|
914 } |
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235
diff
changeset
|
915 uint8_t *no_jump_off = dst+1; |
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235
diff
changeset
|
916 dst = jcc(dst, cond, dst+2); |
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235
diff
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|
917 dst = zcycles(dst, 5);//T States: 5 |
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235
diff
changeset
|
918 uint16_t dest_addr = inst->immed; |
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235
diff
changeset
|
919 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
920 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
changeset
|
921 if (!call_dst) { |
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235
diff
changeset
|
922 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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235
diff
changeset
|
923 //fake address to force large displacement |
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235
diff
changeset
|
924 call_dst = dst + 256; |
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235
diff
changeset
|
925 } |
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diff
changeset
|
926 dst = jmp(dst, call_dst); |
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235
diff
changeset
|
927 } else { |
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235
diff
changeset
|
928 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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235
diff
changeset
|
929 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
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|
930 dst = jmp_r(dst, SCRATCH1); |
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235
diff
changeset
|
931 } |
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diff
changeset
|
932 *no_jump_off = dst - (no_jump_off+1); |
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235
diff
changeset
|
933 break; |
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235
diff
changeset
|
934 } |
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235
diff
changeset
|
935 case Z80_JR: { |
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235
diff
changeset
|
936 dst = zcycles(dst, 12);//T States: 4,3,5 |
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235
diff
changeset
|
937 uint16_t dest_addr = address + inst->immed + 2; |
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235
diff
changeset
|
938 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
939 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
changeset
|
940 if (!call_dst) { |
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235
diff
changeset
|
941 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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235
diff
changeset
|
942 //fake address to force large displacement |
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235
diff
changeset
|
943 call_dst = dst + 256; |
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235
diff
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|
944 } |
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235
diff
changeset
|
945 dst = jmp(dst, call_dst); |
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235
diff
changeset
|
946 } else { |
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235
diff
changeset
|
947 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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235
diff
changeset
|
948 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
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|
949 dst = jmp_r(dst, SCRATCH1); |
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235
diff
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|
950 } |
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951 break; |
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952 } |
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953 case Z80_JRCC: { |
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954 dst = zcycles(dst, 7);//T States: 4,3 |
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955 uint8_t cond = CC_Z; |
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956 switch (inst->reg) |
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957 { |
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958 case Z80_CC_NZ: |
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959 cond = CC_NZ; |
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960 case Z80_CC_Z: |
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961 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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962 break; |
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963 case Z80_CC_NC: |
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964 cond = CC_NZ; |
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965 case Z80_CC_C: |
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966 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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967 break; |
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968 } |
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969 uint8_t *no_jump_off = dst+1; |
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970 dst = jcc(dst, cond, dst+2); |
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971 dst = zcycles(dst, 5);//T States: 5 |
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972 uint16_t dest_addr = address + inst->immed + 2; |
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973 if (dest_addr < 0x4000) { |
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974 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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975 if (!call_dst) { |
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976 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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977 //fake address to force large displacement |
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978 call_dst = dst + 256; |
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979 } |
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980 dst = jmp(dst, call_dst); |
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981 } else { |
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982 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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983 dst = call(dst, (uint8_t *)z80_native_addr); |
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984 dst = jmp_r(dst, SCRATCH1); |
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985 } |
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986 *no_jump_off = dst - (no_jump_off+1); |
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987 break; |
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988 } |
239
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989 case Z80_DJNZ: |
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990 dst = zcycles(dst, 8);//T States: 5,3 |
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991 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
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992 uint8_t *no_jump_off = dst+1; |
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993 dst = jcc(dst, CC_Z, dst+2); |
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994 dst = zcycles(dst, 5);//T States: 5 |
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995 uint16_t dest_addr = address + inst->immed + 2; |
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996 if (dest_addr < 0x4000) { |
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997 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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998 if (!call_dst) { |
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999 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1000 //fake address to force large displacement |
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1001 call_dst = dst + 256; |
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1002 } |
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1003 dst = jmp(dst, call_dst); |
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1004 } else { |
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1005 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1006 dst = call(dst, (uint8_t *)z80_native_addr); |
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1007 dst = jmp_r(dst, SCRATCH1); |
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1008 } |
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1009 *no_jump_off = dst - (no_jump_off+1); |
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1010 break; |
235
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1011 case Z80_CALL: { |
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1012 dst = zcycles(dst, 11);//T States: 4,3,4 |
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1013 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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1014 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
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1015 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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1016 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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1017 if (inst->immed < 0x4000) { |
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1018 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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1019 if (!call_dst) { |
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1020 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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1021 //fake address to force large displacement |
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1022 call_dst = dst + 256; |
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1023 } |
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1024 dst = jmp(dst, call_dst); |
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1025 } else { |
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1026 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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1027 dst = call(dst, (uint8_t *)z80_native_addr); |
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1028 dst = jmp_r(dst, SCRATCH1); |
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1029 } |
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1030 break; |
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1031 } |
238
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1032 case Z80_CALLCC: |
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1033 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
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1034 uint8_t cond = CC_Z; |
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1035 switch (inst->reg) |
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1036 { |
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|
1037 case Z80_CC_NZ: |
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1038 cond = CC_NZ; |
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1039 case Z80_CC_Z: |
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1040 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1041 break; |
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1042 case Z80_CC_NC: |
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1043 cond = CC_NZ; |
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1044 case Z80_CC_C: |
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1045 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1046 break; |
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|
1047 case Z80_CC_PO: |
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|
1048 cond = CC_NZ; |
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1049 case Z80_CC_PE: |
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|
1050 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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|
1051 break; |
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1052 case Z80_CC_P: |
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|
1053 case Z80_CC_M: |
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|
1054 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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|
1055 break; |
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|
1056 } |
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|
1057 uint8_t *no_call_off = dst+1; |
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|
1058 dst = jcc(dst, cond, dst+2); |
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|
1059 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
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|
1060 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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changeset
|
1061 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1062 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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236
diff
changeset
|
1063 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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236
diff
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|
1064 if (inst->immed < 0x4000) { |
827ebce557bf
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236
diff
changeset
|
1065 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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236
diff
changeset
|
1066 if (!call_dst) { |
827ebce557bf
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236
diff
changeset
|
1067 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
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236
diff
changeset
|
1068 //fake address to force large displacement |
827ebce557bf
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236
diff
changeset
|
1069 call_dst = dst + 256; |
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236
diff
changeset
|
1070 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1071 dst = jmp(dst, call_dst); |
827ebce557bf
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236
diff
changeset
|
1072 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
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|
1073 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1074 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
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236
diff
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|
1075 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
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236
diff
changeset
|
1076 } |
827ebce557bf
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236
diff
changeset
|
1077 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
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236
diff
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|
1078 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1079 case Z80_RET: |
235
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213
diff
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|
1080 dst = zcycles(dst, 4);//T States: 4 |
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Get Z80 core working for simple programs
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|
1081 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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|
1082 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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|
1083 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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|
1084 dst = call(dst, (uint8_t *)z80_native_addr); |
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213
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|
1085 dst = jmp_r(dst, SCRATCH1); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1086 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1087 case Z80_RETCC: { |
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Implement RETCC in Z80 core.
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243
diff
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|
1088 dst = zcycles(dst, 5);//T States: 5 |
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Implement RETCC in Z80 core.
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243
diff
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|
1089 uint8_t cond = CC_Z; |
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Implement RETCC in Z80 core.
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243
diff
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|
1090 switch (inst->reg) |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1091 { |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1092 case Z80_CC_NZ: |
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Implement RETCC in Z80 core.
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243
diff
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|
1093 cond = CC_NZ; |
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Implement RETCC in Z80 core.
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|
1094 case Z80_CC_Z: |
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Implement RETCC in Z80 core.
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diff
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|
1095 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1096 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1097 case Z80_CC_NC: |
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Implement RETCC in Z80 core.
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243
diff
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|
1098 cond = CC_NZ; |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1099 case Z80_CC_C: |
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Implement RETCC in Z80 core.
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243
diff
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|
1100 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1101 break; |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1102 case Z80_CC_PO: |
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Implement RETCC in Z80 core.
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243
diff
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|
1103 cond = CC_NZ; |
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Implement RETCC in Z80 core.
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243
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|
1104 case Z80_CC_PE: |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1105 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1106 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1107 case Z80_CC_P: |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1108 case Z80_CC_M: |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1109 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1110 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1111 } |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1112 uint8_t *no_call_off = dst+1; |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1113 dst = jcc(dst, cond, dst+2); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1114 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1115 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1116 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1117 dst = call(dst, (uint8_t *)z80_native_addr); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1118 dst = jmp_r(dst, SCRATCH1); |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1119 *no_call_off = dst - (no_call_off+1); |
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Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1120 break; |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1121 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
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243
diff
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|
1122 /*case Z80_RETI: |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1123 case Z80_RETN:*/ |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1124 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1125 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1126 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1127 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1128 dst = mov_ir(dst, address + 3, SCRATCH2, SZ_W); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1129 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1130 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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239
diff
changeset
|
1131 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1132 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1133 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1134 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1135 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
diff
changeset
|
1136 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1137 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1138 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1139 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1140 /*case Z80_IN: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1141 case Z80_INI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1142 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 case Z80_IND: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1144 case Z80_INDR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 case Z80_OUT: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1146 case Z80_OUTI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1147 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1149 case Z80_OTDR:*/ |
235
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213
diff
changeset
|
1150 default: { |
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213
diff
changeset
|
1151 char disbuf[80]; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1152 z80_disasm(inst, disbuf); |
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parents:
213
diff
changeset
|
1153 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1154 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1155 } |
235
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213
diff
changeset
|
1156 } |
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213
diff
changeset
|
1157 return dst; |
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213
diff
changeset
|
1158 } |
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213
diff
changeset
|
1159 |
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213
diff
changeset
|
1160 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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213
diff
changeset
|
1161 { |
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213
diff
changeset
|
1162 native_map_slot *map; |
d9bf8e61c33c
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213
diff
changeset
|
1163 if (address < 0x4000) { |
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213
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changeset
|
1164 address &= 0x1FFF; |
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changeset
|
1165 map = context->static_code_map; |
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213
diff
changeset
|
1166 } else if (address >= 0x8000) { |
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213
diff
changeset
|
1167 address &= 0x7FFF; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1168 map = context->banked_code_map + (context->bank_reg << 15); |
235
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213
diff
changeset
|
1169 } else { |
d9bf8e61c33c
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213
diff
changeset
|
1170 return NULL; |
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213
diff
changeset
|
1171 } |
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213
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changeset
|
1172 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET) { |
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1173 return NULL; |
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1174 } |
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1175 return map->base + map->offsets[address]; |
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1176 } |
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1177 |
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1178 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
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1179 { |
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1180 if (address >= 0x4000) { |
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1181 return 0; |
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1182 } |
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1183 return opts->ram_inst_sizes[address & 0x1FFF]; |
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1184 } |
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1185 |
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1186 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
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1187 { |
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1188 uint32_t orig_address = address; |
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1189 native_map_slot *map; |
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1190 x86_z80_options * opts = context->options; |
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1191 if (address < 0x4000) { |
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1192 address &= 0x1FFF; |
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1193 map = context->static_code_map; |
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1194 opts->ram_inst_sizes[address] = native_size; |
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1195 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
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1196 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
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1197 } else if (address >= 0x8000) { |
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1198 address &= 0x7FFF; |
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1199 map = context->banked_code_map + (context->bank_reg << 15); |
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1200 if (!map->offsets) { |
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1201 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1202 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1203 } |
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1204 } else { |
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1205 return; |
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1206 } |
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1207 if (!map->base) { |
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1208 map->base = native_address; |
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1209 } |
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1210 map->offsets[address] = native_address - map->base; |
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1211 for(--size; size; --size, orig_address++) { |
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1212 address = orig_address; |
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1213 if (address < 0x4000) { |
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1214 address &= 0x1FFF; |
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1215 map = context->static_code_map; |
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1216 } else if (address >= 0x8000) { |
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1217 address &= 0x7FFF; |
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1218 map = context->banked_code_map + (context->bank_reg << 15); |
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1219 } else { |
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1220 return; |
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1221 } |
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1222 if (!map->offsets) { |
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1223 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1224 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1225 } |
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1226 map->offsets[address] = EXTENSION_WORD; |
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1227 } |
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1228 } |
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1229 |
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1230 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
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1231 |
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1232 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
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1233 { |
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1234 if (!static_code_map->base || address >= 0x4000) { |
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1235 return INVALID_INSTRUCTION_START; |
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1236 } |
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1237 address &= 0x1FFF; |
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1238 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
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1239 return INVALID_INSTRUCTION_START; |
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1240 } |
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1241 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
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1242 --address; |
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1243 address &= 0x1FFF; |
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1244 } |
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1245 return address; |
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1246 } |
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1247 |
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1248 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
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1249 { |
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1250 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
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1251 if (inst_start != INVALID_INSTRUCTION_START) { |
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1252 uint8_t * dst = z80_get_native_address(context, inst_start); |
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1253 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
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1254 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
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1255 } |
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1256 return context; |
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1257 } |
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1258 |
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1259 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
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1260 { |
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1261 x86_z80_options * opts = context->options; |
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1262 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
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1263 uint8_t * orig_start = z80_get_native_address(context, address); |
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1264 uint32_t orig = address; |
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1265 address &= 0x1FFF; |
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1266 uint8_t * dst = opts->cur_code; |
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1267 uint8_t * dst_end = opts->code_end; |
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1268 uint8_t *after, *inst = context->mem_pointers[0] + address; |
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1269 z80inst instbuf; |
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1270 after = z80_decode(inst, &instbuf); |
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1271 if (orig_size != ZMAX_NATIVE_SIZE) { |
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1272 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
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1273 size_t size = 1024*1024; |
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1274 dst = alloc_code(&size); |
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1275 opts->code_end = dst_end = dst + size; |
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1276 opts->cur_code = dst; |
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1277 } |
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1278 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
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1279 if ((native_end - dst) <= orig_size) { |
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1280 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
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1281 while (native_end < orig_start + orig_size) { |
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1282 *(native_end++) = 0x90; //NOP |
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1283 } |
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1284 return orig_start; |
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1285 } else { |
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1286 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
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1287 opts->code_end = dst+ZMAX_NATIVE_SIZE; |
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1288 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op = Z80_NOP && instbuf.immed == 42))) { |
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1289 jmp(native_end, z80_get_native_address(context, address + after-inst)); |
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1290 } |
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1291 return dst; |
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1292 } |
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1293 } else { |
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1294 dst = translate_z80inst(&instbuf, orig_start, context, address); |
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1295 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op = Z80_NOP && instbuf.immed == 42))) { |
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1296 dst = jmp(dst, z80_get_native_address(context, address + after-inst)); |
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1297 } |
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1298 return orig_start; |
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1299 } |
235
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1300 } |
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1301 |
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1302 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
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1303 { |
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1304 uint8_t * addr = z80_get_native_address(context, address); |
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1305 if (!addr) { |
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1306 translate_z80_stream(context, address); |
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1307 addr = z80_get_native_address(context, address); |
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1308 if (!addr) { |
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1309 printf("Failed to translate %X to native code\n", address); |
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1310 } |
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1311 } |
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1312 return addr; |
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1313 } |
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1314 |
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1315 void translate_z80_stream(z80_context * context, uint32_t address) |
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1316 { |
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1317 char disbuf[80]; |
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1318 if (z80_get_native_address(context, address)) { |
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1319 return; |
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1320 } |
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1321 x86_z80_options * opts = context->options; |
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1322 uint8_t * encoded = NULL, *next; |
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1323 if (address < 0x4000) { |
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1324 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1325 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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1326 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1327 } |
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1328 while (encoded != NULL) |
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1329 { |
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1330 z80inst inst; |
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1331 printf("translating Z80 code at address %X\n", address); |
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1332 do { |
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1333 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
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1334 if (opts->code_end-opts->cur_code < 5) { |
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1335 puts("out of code memory, not enough space for jmp to next chunk"); |
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1336 exit(1); |
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1337 } |
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1338 size_t size = 1024*1024; |
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1339 opts->cur_code = alloc_code(&size); |
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1340 opts->code_end = opts->cur_code + size; |
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1341 jmp(opts->cur_code, opts->cur_code); |
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1342 } |
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1343 if (address > 0x4000 & address < 0x8000) { |
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1344 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1345 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1346 break; |
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1347 } |
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1348 uint8_t * existing = z80_get_native_address(context, address); |
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1349 if (existing) { |
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1350 opts->cur_code = jmp(opts->cur_code, existing); |
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1351 break; |
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1352 } |
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1353 next = z80_decode(encoded, &inst); |
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1354 z80_disasm(&inst, disbuf); |
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1355 if (inst.op == Z80_NOP) { |
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1356 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1357 } else { |
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1358 printf("%X\t%s\n", address, disbuf); |
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1359 } |
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1360 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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1361 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
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1362 opts->cur_code = after; |
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1363 address += next-encoded; |
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1364 encoded = next; |
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1365 } while (!(inst.op == Z80_RET || inst.op == Z80_RETI || inst.op == Z80_RETN || inst.op == Z80_JP || (inst.op = Z80_NOP && inst.immed == 42))); |
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1366 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1367 if (opts->deferred) { |
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1368 address = opts->deferred->address; |
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1369 printf("defferred address: %X\n", address); |
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1370 if (address < 0x4000) { |
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1371 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1372 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1373 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1374 } else { |
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1375 printf("attempt to translate non-memory address: %X\n", address); |
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1376 exit(1); |
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1377 } |
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1378 } else { |
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1379 encoded = NULL; |
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1380 } |
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1381 } |
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1382 } |
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1383 |
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1384 void init_x86_z80_opts(x86_z80_options * options) |
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1385 { |
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1386 options->flags = 0; |
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1387 options->regs[Z80_B] = BH; |
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1388 options->regs[Z80_C] = RBX; |
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1389 options->regs[Z80_D] = CH; |
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1390 options->regs[Z80_E] = RCX; |
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1391 options->regs[Z80_H] = AH; |
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1392 options->regs[Z80_L] = RAX; |
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1393 options->regs[Z80_IXH] = DH; |
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1394 options->regs[Z80_IXL] = RDX; |
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1395 options->regs[Z80_IYH] = -1; |
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1396 options->regs[Z80_IYL] = R8; |
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1397 options->regs[Z80_I] = -1; |
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1398 options->regs[Z80_R] = -1; |
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1399 options->regs[Z80_A] = R10; |
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1400 options->regs[Z80_BC] = RBX; |
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1401 options->regs[Z80_DE] = RCX; |
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1402 options->regs[Z80_HL] = RAX; |
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1403 options->regs[Z80_SP] = R9; |
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1404 options->regs[Z80_AF] = -1; |
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1405 options->regs[Z80_IX] = RDX; |
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1406 options->regs[Z80_IY] = R8; |
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1407 size_t size = 1024 * 1024; |
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1408 options->cur_code = alloc_code(&size); |
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1409 options->code_end = options->cur_code + size; |
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1410 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1411 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
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1412 options->deferred = NULL; |
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1413 } |
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1414 |
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1415 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1416 { |
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1417 memset(context, 0, sizeof(*context)); |
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1418 context->static_code_map = malloc(sizeof(context->static_code_map)); |
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1419 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1420 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1421 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1422 context->options = options; |
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1423 } |
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1424 |
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1425 void z80_reset(z80_context * context) |
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1426 { |
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1427 context->native_pc = z80_get_native_address_trans(context, 0); |
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1428 } |
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1429 |
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1430 |