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annotate blastem.c @ 182:924af8b2f7a0

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Fix -(a7) dest when size is byte
author Mike Pavone <pavone@retrodev.com>
date Wed, 09 Jan 2013 21:41:55 -0800
parents 97aa449706c2
children ebcbdd1c4cc8
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1 #include "68kinst.h"
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2 #include "m68k_to_x86.h"
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3 #include "mem.h"
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4 #include "vdp.h"
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5 #include "render.h"
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6 #include "blastem.h"
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7 #include <stdio.h>
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8 #include <stdlib.h>
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9
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10 #define CARTRIDGE_WORDS 0x200000
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11 #define RAM_WORDS 32 * 1024
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12 #define Z80_RAM_BYTES 8 * 1024
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13 #define MCLKS_PER_68K 7
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14 //TODO: Figure out the exact value for this
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15 #define MCLKS_PER_FRAME (MCLKS_LINE*262)
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16 #define CYCLE_NEVER 0xFFFFFFFF
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17
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18 uint16_t cart[CARTRIDGE_WORDS];
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19 uint16_t ram[RAM_WORDS];
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20 uint8_t z80_ram[Z80_RAM_BYTES];
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21
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22 io_port gamepad_1;
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23 io_port gamepad_2;
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24
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25 #ifndef MIN
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26 #define MIN(a,b) ((a) < (b) ? (a) : (b))
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27 #endif
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28
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29 #define SMD_HEADER_SIZE 512
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30 #define SMD_MAGIC1 0x03
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31 #define SMD_MAGIC2 0xAA
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32 #define SMD_MAGIC3 0xBB
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33 #define SMD_BLOCK_SIZE 0x4000
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34
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35 int load_smd_rom(long filesize, FILE * f)
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36 {
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37 uint8_t block[SMD_BLOCK_SIZE];
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38 filesize -= SMD_HEADER_SIZE;
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39 fseek(f, SMD_HEADER_SIZE, SEEK_SET);
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40
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41 uint16_t * dst = cart;
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42 while (filesize > 0) {
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43 fread(block, 1, SMD_BLOCK_SIZE, f);
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44 for (uint8_t *low = block, *high = (block+SMD_BLOCK_SIZE/2), *end = block+SMD_BLOCK_SIZE; high < end; high++, low++) {
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45 *(dst++) = *high << 8 | *low;
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46 }
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47 filesize -= SMD_BLOCK_SIZE;
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48 }
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49 return 1;
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50 }
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51
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52 int load_rom(char * filename)
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53 {
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54 uint8_t header[10];
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55 FILE * f = fopen(filename, "rb");
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56 if (!f) {
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57 return 0;
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58 }
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59 fread(header, 1, sizeof(header), f);
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60 fseek(f, 0, SEEK_END);
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61 long filesize = ftell(f);
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62 if (filesize/2 > CARTRIDGE_WORDS) {
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63 //carts bigger than 4MB not currently supported
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64 filesize = CARTRIDGE_WORDS*2;
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65 }
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66 fseek(f, 0, SEEK_SET);
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67 if (header[1] == SMD_MAGIC1 && header[8] == SMD_MAGIC2 && header[9] == SMD_MAGIC3) {
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68 int i;
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69 for (i = 3; i < 8; i++) {
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70 if (header[i] != 0) {
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71 break;
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72 }
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73 }
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74 if (i == 8) {
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75 if (header[2]) {
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76 fprintf(stderr, "%s is a split SMD ROM which is not currently supported", filename);
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77 exit(1);
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78 }
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79 return load_smd_rom(filesize, f);
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80 }
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81 }
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82 fread(cart, 2, filesize/2, f);
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83 fclose(f);
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84 for(unsigned short * cur = cart; cur - cart < (filesize/2); ++cur)
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85 {
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86 *cur = (*cur >> 8) | (*cur << 8);
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87 }
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88 //TODO: Mirror ROM
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89 return 1;
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90 }
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91
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92 uint16_t read_dma_value(uint32_t address)
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93 {
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94 //addresses here are word addresses (i.e. bit 0 corresponds to A1), so no need to do div by 2
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95 if (address < 0x200000) {
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96 return cart[address];
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97 } else if(address >= 0x700000) {
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98 return ram[address & 0x7FFF];
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99 }
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100 //TODO: Figure out what happens when you try to DMA from weird adresses like IO or banked Z80 area
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101 return 0;
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102 }
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103
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104 #define VINT_CYCLE ((MCLKS_LINE * 226)/MCLKS_PER_68K)
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105
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106 m68k_context * sync_components(m68k_context * context)
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107 {
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108 //TODO: Handle sync targets smaller than a single frame
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109 vdp_context * v_context = context->next_context;
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110 uint32_t mclks = context->current_cycle * MCLKS_PER_68K;
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111 if (mclks >= MCLKS_PER_FRAME) {
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112 //printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, mclks);
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113 vdp_run_context(v_context, MCLKS_PER_FRAME);
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114 wait_render_frame(v_context);
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115 mclks -= MCLKS_PER_FRAME;
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116 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
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117 io_adjust_cycles(&gamepad_1, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K);
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118 io_adjust_cycles(&gamepad_2, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K);
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119 context->current_cycle -= MCLKS_PER_FRAME/MCLKS_PER_68K;
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120 if (mclks) {
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121 vdp_run_context(v_context, mclks);
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122 }
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123 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
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124 if (context->int_cycle > VINT_CYCLE) {
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125 context->int_cycle = VINT_CYCLE;
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126 context->int_num = 6;
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127 if (context->int_cycle < context->sync_cycle) {
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128 context->target_cycle = context->int_cycle;
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129 }
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130 }
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131 } else {
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132 context->int_cycle = 0xFFFFFFFF;
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133 context->target_cycle = context->sync_cycle;
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134 }
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135 } else {
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136 //printf("running VDP for %d cycles\n", mclks - v_context->cycles);
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137 vdp_run_context(v_context, mclks);
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138 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
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139 if (context->int_cycle > VINT_CYCLE) {
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140 context->int_cycle = VINT_CYCLE;
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141 context->int_num = 6;
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142 if (context->int_cycle < context->sync_cycle && context->int_cycle < context->current_cycle) {
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diff changeset
143 context->target_cycle = context->int_cycle;
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diff changeset
144 }
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diff changeset
145 }
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diff changeset
146 if (context->int_cycle <= context->current_cycle) {
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diff changeset
147 context->int_cycle = CYCLE_NEVER;
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diff changeset
148 context->target_cycle = context->sync_cycle;
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diff changeset
149 }
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diff changeset
150 } else {
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diff changeset
151 context->int_cycle = CYCLE_NEVER;
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diff changeset
152 context->target_cycle = context->sync_cycle;
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153 }
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154 }
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parents:
diff changeset
155 return context;
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diff changeset
156 }
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157
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158 m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_t value)
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159 {
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160 //printf("vdp_port write: %X, value: %X, cycle: %d\n", vdp_port, value, context->current_cycle);
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diff changeset
161 sync_components(context);
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diff changeset
162 vdp_context * v_context = context->next_context;
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diff changeset
163 if (vdp_port < 0x10) {
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
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parents: 144
diff changeset
164 int blocked;
88
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165 if (vdp_port < 4) {
149
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parents: 144
diff changeset
166 while (vdp_data_port_write(v_context, value) < 0) {
88
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167 while(v_context->flags & FLAG_DMA_RUN) {
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168 vdp_run_dma_done(v_context, MCLKS_PER_FRAME);
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169 if (v_context->cycles >= MCLKS_PER_FRAME) {
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170 wait_render_frame(v_context);
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171 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
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172 io_adjust_cycles(&gamepad_1, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
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173 io_adjust_cycles(&gamepad_2, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
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174 }
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175 }
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176 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
149
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parents: 144
diff changeset
177 }
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parents: 144
diff changeset
178 } else if(vdp_port < 8) {
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parents: 144
diff changeset
179 blocked = vdp_control_port_write(v_context, value);
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parents: 144
diff changeset
180 if (blocked) {
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parents: 144
diff changeset
181 while (blocked) {
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parents: 144
diff changeset
182 while(v_context->flags & FLAG_DMA_RUN) {
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parents: 144
diff changeset
183 vdp_run_dma_done(v_context, MCLKS_PER_FRAME);
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parents: 144
diff changeset
184 if (v_context->cycles >= MCLKS_PER_FRAME) {
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parents: 144
diff changeset
185 wait_render_frame(v_context);
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parents: 144
diff changeset
186 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
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parents: 144
diff changeset
187 io_adjust_cycles(&gamepad_1, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
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parents: 144
diff changeset
188 io_adjust_cycles(&gamepad_2, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
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parents: 144
diff changeset
189 }
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parents: 144
diff changeset
190 }
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parents: 144
diff changeset
191 if (blocked < 0) {
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parents: 144
diff changeset
192 blocked = vdp_control_port_write(v_context, value);
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parents: 144
diff changeset
193 } else {
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parents: 144
diff changeset
194 blocked = 0;
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parents: 144
diff changeset
195 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
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parents: 144
diff changeset
196 }
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parents: 144
diff changeset
197 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
88
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198 } else {
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199 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
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200 if (context->int_cycle > VINT_CYCLE) {
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201 context->int_cycle = VINT_CYCLE;
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202 context->int_num = 6;
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diff changeset
203 if (context->int_cycle < context->sync_cycle) {
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204 context->target_cycle = context->int_cycle;
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205 }
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parents:
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206 }
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diff changeset
207 } else {
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208 context->int_cycle = 0xFFFFFFFF;
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diff changeset
209 context->target_cycle = context->sync_cycle;
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210 }
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211 }
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212 } else {
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213 printf("Illegal write to HV Counter port %X\n", vdp_port);
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214 exit(1);
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215 }
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216 context->current_cycle = v_context->cycles/MCLKS_PER_68K;
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diff changeset
217 } else if (vdp_port < 0x18) {
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parents:
diff changeset
218 //TODO: Implement PSG
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219 } else {
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parents:
diff changeset
220 //TODO: Implement undocumented test register(s)
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diff changeset
221 }
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diff changeset
222 return context;
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diff changeset
223 }
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diff changeset
224
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225 m68k_context * vdp_port_read(uint32_t vdp_port, m68k_context * context)
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diff changeset
226 {
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diff changeset
227 sync_components(context);
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diff changeset
228 vdp_context * v_context = context->next_context;
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diff changeset
229 if (vdp_port < 0x10) {
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parents:
diff changeset
230 if (vdp_port < 4) {
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parents:
diff changeset
231 context->value = vdp_data_port_read(v_context);
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parents:
diff changeset
232 } else if(vdp_port < 8) {
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parents:
diff changeset
233 context->value = vdp_control_port_read(v_context);
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parents:
diff changeset
234 } else {
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 130
diff changeset
235 context->value = vdp_hv_counter_read(v_context);
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 130
diff changeset
236 //printf("HV Counter: %X at cycle %d\n", context->value, v_context->cycles);
88
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parents:
diff changeset
237 }
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diff changeset
238 context->current_cycle = v_context->cycles/MCLKS_PER_68K;
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parents:
diff changeset
239 } else {
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parents:
diff changeset
240 printf("Illegal read from PSG or test register port %X\n", vdp_port);
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parents:
diff changeset
241 exit(1);
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parents:
diff changeset
242 }
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parents:
diff changeset
243 return context;
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parents:
diff changeset
244 }
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diff changeset
245
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diff changeset
246 #define TH 0x40
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diff changeset
247 #define TH_TIMEOUT 8000
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diff changeset
248 #define Z80_ACK_DELAY 3 //TODO: Calculate this on the fly based on how synced up the Z80 and 68K clocks are
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249
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diff changeset
250 uint8_t reset = 1;
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diff changeset
251 uint8_t busreq = 0;
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diff changeset
252 uint8_t busack = 0;
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diff changeset
253 uint32_t busack_cycle = CYCLE_NEVER;
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diff changeset
254 uint8_t new_busack = 0;
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parents:
diff changeset
255
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parents:
diff changeset
256 void io_adjust_cycles(io_port * pad, uint32_t current_cycle, uint32_t deduction)
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parents:
diff changeset
257 {
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
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parents: 88
diff changeset
258 /*uint8_t control = pad->control | 0x80;
88
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diff changeset
259 uint8_t th = control & pad->output;
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diff changeset
260 if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) {
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parents:
diff changeset
261 printf("adjust_cycles | control: %X, TH: %X, GAMEPAD_TH0: %X, GAMEPAD_TH1: %X, TH Counter: %d, Timeout: %d, Cycle: %d\n", control, th, pad->input[GAMEPAD_TH0], pad->input[GAMEPAD_TH1], pad->th_counter,pad->timeout_cycle, current_cycle);
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
262 }*/
88
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parents:
diff changeset
263 if (current_cycle >= pad->timeout_cycle) {
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parents:
diff changeset
264 pad->th_counter = 0;
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parents:
diff changeset
265 } else {
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parents:
diff changeset
266 pad->timeout_cycle -= deduction;
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parents:
diff changeset
267 }
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parents:
diff changeset
268 if (busack_cycle < CYCLE_NEVER && current_cycle < busack_cycle) {
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parents:
diff changeset
269 busack_cycle -= deduction;
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parents:
diff changeset
270 }
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parents:
diff changeset
271 }
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parents:
diff changeset
272
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diff changeset
273 void io_data_write(io_port * pad, m68k_context * context, uint8_t value)
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parents:
diff changeset
274 {
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parents:
diff changeset
275 if (pad->control & TH) {
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parents:
diff changeset
276 //check if TH has changed
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parents:
diff changeset
277 if ((pad->output & TH) ^ (value & TH)) {
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
278 if (context->current_cycle >= pad->timeout_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
279 pad->th_counter = 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
280 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
281 if (!(value & TH)) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
282 pad->th_counter++;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
283 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
284 pad->timeout_cycle = context->current_cycle + TH_TIMEOUT;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
285 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
286 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
287 pad->output = value;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
288 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
289
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
290 void io_data_read(io_port * pad, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
291 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
292 uint8_t control = pad->control | 0x80;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
293 uint8_t th = control & pad->output;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
294 uint8_t input;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
295 if (context->current_cycle >= pad->timeout_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
296 pad->th_counter = 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
297 }
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
298 /*if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) {
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
299 printf("io_data_read | control: %X, TH: %X, GAMEPAD_TH0: %X, GAMEPAD_TH1: %X, TH Counter: %d, Timeout: %d, Cycle: %d\n", control, th, pad->input[GAMEPAD_TH0], pad->input[GAMEPAD_TH1], pad->th_counter,pad->timeout_cycle, context->current_cycle);
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
300 }*/
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
301 if (th) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 if (pad->th_counter == 2) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
303 input = pad->input[GAMEPAD_EXTRA];
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
305 input = pad->input[GAMEPAD_TH1];
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
306 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
307 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
308 if (pad->th_counter == 2) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309 input = pad->input[GAMEPAD_TH0] | 0xF;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 } else if(pad->th_counter == 3) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311 input = pad->input[GAMEPAD_TH0] & 0x30;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
312 } else {
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
313 input = pad->input[GAMEPAD_TH0] | 0xC;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
315 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
316 context->value = ((~input) & (~control)) | (pad->output & control);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
317 /*if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
318 printf ("value: %X\n", context->value);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
319 }*/
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
320 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
321
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322 m68k_context * io_write(uint32_t location, m68k_context * context, uint8_t value)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
324 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
325 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
326 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
327 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
328 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
329 if (!(busack || reset)) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
330 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
331 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
332 z80_ram[location & 0x1FFF] = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
333 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
334 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
335 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
336 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
337 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
338 switch(location/2)
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
339 {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
340 case 0x1:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
341 io_data_write(&gamepad_1, context, value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
342 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
343 case 0x2:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
344 io_data_write(&gamepad_2, context, value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
345 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
346 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
347 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
348 case 0x4:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
349 gamepad_1.control = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
350 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
351 case 0x5:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
352 gamepad_2.control = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
353 break;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
354 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
355 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
356 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
357 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
358 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
359 busack_cycle = CYCLE_NEVER;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
360 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
361 if (value & 1) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
362 busreq = 1;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
363 if(!reset) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
364 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
365 new_busack = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
366 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
367 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
368 busreq = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
369 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
370 busack = 1;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
371 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
372 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
373 if (value & 1) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
374 if (reset && busreq) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
375 new_busack = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
376 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
377 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
378 reset = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
379 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
380 reset = 1;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
381 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
382 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
383 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
384 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
385 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
386 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
387
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
388 m68k_context * io_write_w(uint32_t location, m68k_context * context, uint16_t value)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
390 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
391 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
392 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
393 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
394 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
395 if (!(busack || reset)) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
396 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
397 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
398 z80_ram[location & 0x1FFE] = value >> 8;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
399 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
400 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
401 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
402 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
403 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
404 switch(location/2)
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
405 {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
406 case 0x1:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
407 io_data_write(&gamepad_1, context, value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
408 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
409 case 0x2:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
410 io_data_write(&gamepad_2, context, value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
411 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
412 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
413 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
414 case 0x4:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
415 gamepad_1.control = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
416 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
417 case 0x5:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
418 gamepad_2.control = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
419 break;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
420 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
421 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
422 //printf("IO Write of %X to %X @ %d\n", value, location, context->current_cycle);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
423 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
424 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
425 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
426 busack_cycle = CYCLE_NEVER;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
427 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
428 if (value & 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
429 busreq = 1;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
430 if(!reset) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
431 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
432 new_busack = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
433 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
434 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
435 busreq = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
436 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
437 busack = 1;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
438 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
439 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
440 if (value & 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
441 if (reset && busreq) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
442 new_busack = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
443 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
444 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
445 reset = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
446 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
447 reset = 1;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
448 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
449 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
450 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
451 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
452 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
453 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
454
130
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
455 #define USA 0x80
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
456 #define JAP 0x00
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
457 #define EUR 0xC0
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
458 #define NO_DISK 0x20
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
459 uint8_t version_reg = NO_DISK | USA;
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
460
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
461 m68k_context * io_read(uint32_t location, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
462 {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
463 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
464 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
465 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
466 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
467 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
468 if (!(busack || reset)) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
469 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
470 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
471 context->value = z80_ram[location & 0x1FFF];
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
472 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
473 context->value = 0xFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
474 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
475 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
476 context->value = 0xFF;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
477 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
478 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
479 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
480 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
481 switch(location/2)
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
482 {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
483 case 0x0:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
484 //version bits should be 0 for now since we're not emulating TMSS
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
485 //Not sure about the other bits
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
486 context->value = version_reg;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
487 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
488 case 0x1:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
489 io_data_read(&gamepad_1, context);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
490 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
491 case 0x2:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
492 io_data_read(&gamepad_2, context);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
493 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
494 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
495 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
496 case 0x4:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
497 context->value = gamepad_1.control;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
498 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
499 case 0x5:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
500 context->value = gamepad_2.control;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
501 break;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
502 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
503 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
504 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
505 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
506 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
507 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
508 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
509 context->value = reset || busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
510 //printf("Byte read of BUSREQ returned %d @ %d (reset: %d, busack: %d)\n", context->value, context->current_cycle, reset, busack);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
511 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
512 context->value = !reset;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
513 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
514 printf("Byte read of unknown IO location: %X\n", location);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
515 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
516 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
517 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
518 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
519 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
520
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
521 m68k_context * io_read_w(uint32_t location, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
522 {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
523 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
524 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
525 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
526 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
527 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
528 if (!(busack || reset)) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
529 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
530 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
531 context->value = z80_ram[location & 0x1FFE];
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
532 context->value |= context->value << 8;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
533 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
534 context->value = 0xFFFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
535 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
536 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
537 context->value = 0xFFFF;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
538 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
539 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
540 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
541 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
542 switch(location/2)
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
543 {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
544 case 0x0:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
545 //version bits should be 0 for now since we're not emulating TMSS
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
546 //Not sure about the other bits
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
547 context->value = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
548 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
549 case 0x1:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
550 io_data_read(&gamepad_1, context);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
551 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
552 case 0x2:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
553 io_data_read(&gamepad_2, context);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
554 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
555 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
556 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
557 case 0x4:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
558 context->value = gamepad_1.control;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
559 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
560 case 0x5:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
561 context->value = gamepad_2.control;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
562 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
563 case 0x6:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
564 //PORT C Control
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
565 context->value = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
566 break;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
567 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
568 context->value = context->value | (context->value << 8);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
569 //printf("Word read to %X returned %d\n", location, context->value);
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
570 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
571 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
572 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
573 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
574 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
575 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
576 context->value = (reset || busack) << 8;
42c031184e8a Implement access to Z80 RAM
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577 //printf("Word read of BUSREQ returned %d\n", context->value);
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578 } else if (location == 0x1200) {
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579 context->value = (!reset) << 8;
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580 } else {
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581 printf("Word read of unknown IO location: %X\n", location);
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582 }
88
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583 }
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584 }
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585 return context;
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586 }
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587
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588 int main(int argc, char ** argv)
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589 {
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590 if (argc < 2) {
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591 fputs("Usage: blastem FILENAME\n", stderr);
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592 return 1;
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parents:
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593 }
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parents:
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594 if(!load_rom(argv[1])) {
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595 fprintf(stderr, "Failed to open %s for reading\n", argv[1]);
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parents:
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596 return 1;
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597 }
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598 int width = 320;
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599 int height = 240;
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600 if (argc > 2) {
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601 width = atoi(argv[2]);
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parents:
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602 if (argc > 3) {
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parents:
diff changeset
603 height = atoi(argv[3]);
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parents:
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604 } else {
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parents:
diff changeset
605 height = (width/320) * 240;
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parents:
diff changeset
606 }
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parents:
diff changeset
607 }
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parents:
diff changeset
608 render_init(width, height);
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parents:
diff changeset
609
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parents:
diff changeset
610 x86_68k_options opts;
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parents:
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611 m68k_context context;
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parents:
diff changeset
612 vdp_context v_context;
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parents:
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613
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parents:
diff changeset
614 init_x86_68k_opts(&opts);
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parents:
diff changeset
615 init_68k_context(&context, opts.native_code_map, &opts);
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parents:
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616 init_vdp_context(&v_context);
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617 context.next_context = &v_context;
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diff changeset
618 //cartridge ROM
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parents:
diff changeset
619 context.mem_pointers[0] = cart;
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620 context.target_cycle = context.sync_cycle = MCLKS_PER_FRAME/MCLKS_PER_68K;
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parents:
diff changeset
621 //work RAM
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parents:
diff changeset
622 context.mem_pointers[1] = ram;
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parents:
diff changeset
623 uint32_t address;
103
a71544cd01ea Don't pre-emptively translate code at interrupt vectors as some PD ROMs have these pointing at junk. Need some kind of heuristic for detecting garbage if I'm going to translate them ahead of time by default.
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
624 /*address = cart[0x68/2] << 16 | cart[0x6A/2];
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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parents: 89
diff changeset
625 translate_m68k_stream(address, &context);
88
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parents:
diff changeset
626 address = cart[0x70/2] << 16 | cart[0x72/2];
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 89
diff changeset
627 translate_m68k_stream(address, &context);
88
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parents:
diff changeset
628 address = cart[0x78/2] << 16 | cart[0x7A/2];
103
a71544cd01ea Don't pre-emptively translate code at interrupt vectors as some PD ROMs have these pointing at junk. Need some kind of heuristic for detecting garbage if I'm going to translate them ahead of time by default.
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
629 translate_m68k_stream(address, &context);*/
88
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parents:
diff changeset
630 address = cart[2] << 16 | cart[3];
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 89
diff changeset
631 translate_m68k_stream(address, &context);
88
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parents:
diff changeset
632 m68k_reset(&context);
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parents:
diff changeset
633 return 0;
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parents:
diff changeset
634 }