Mercurial > repos > blastem

annotate blastem.c @ 158:a2ab895d9708

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Fix predec address mode when used as source
author Mike Pavone <pavone@retrodev.com>
date Sat, 05 Jan 2013 00:53:50 -0800
parents 42c031184e8a
children 97aa449706c2
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1 #include "68kinst.h"
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2 #include "m68k_to_x86.h"
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3 #include "mem.h"
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
4 #include "vdp.h"
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
5 #include "render.h"
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 #include "blastem.h"
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
7 #include <stdio.h>
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8 #include <stdlib.h>
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
10 #define CARTRIDGE_WORDS 0x200000
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 #define RAM_WORDS 32 * 1024
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
12 #define Z80_RAM_BYTES 8 * 1024
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
13 #define MCLKS_PER_68K 7
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14 //TODO: Figure out the exact value for this
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15 #define MCLKS_PER_FRAME (MCLKS_LINE*262)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 #define CYCLE_NEVER 0xFFFFFFFF
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 uint16_t cart[CARTRIDGE_WORDS];
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
19 uint16_t ram[RAM_WORDS];
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
20 uint8_t z80_ram[Z80_RAM_BYTES];
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
21
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
22 io_port gamepad_1;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
23 io_port gamepad_2;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
24
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
25 #ifndef MIN
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 #define MIN(a,b) ((a) < (b) ? (a) : (b))
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 #endif
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
28
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29 int load_rom(char * filename)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31 FILE * f = fopen(filename, "rb");
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 if (!f) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
33 return 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
34 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
35 fseek(f, 0, SEEK_END);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
36 long filesize = ftell(f);
158
a2ab895d9708 Fix predec address mode when used as source
Mike Pavone <pavone@retrodev.com>
parents: 153
diff changeset
37 if (filesize/2 > CARTRIDGE_WORDS) {
a2ab895d9708 Fix predec address mode when used as source
Mike Pavone <pavone@retrodev.com>
parents: 153
diff changeset
38 //carts bigger than 4MB not currently supported
a2ab895d9708 Fix predec address mode when used as source
Mike Pavone <pavone@retrodev.com>
parents: 153
diff changeset
39 filesize = CARTRIDGE_WORDS*2;
a2ab895d9708 Fix predec address mode when used as source
Mike Pavone <pavone@retrodev.com>
parents: 153
diff changeset
40 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
41 fseek(f, 0, SEEK_SET);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
42 fread(cart, 2, MIN(filesize/2, CARTRIDGE_WORDS), f);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
43 fclose(f);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
44 for(unsigned short * cur = cart; cur - cart < (filesize/2); ++cur)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46 *cur = (*cur >> 8) | (*cur << 8);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
47 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
48 //TODO: Mirror ROM
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
49 return 1;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
50 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
51
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
52 uint16_t read_dma_value(uint32_t address)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
53 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
54 //addresses here are word addresses (i.e. bit 0 corresponds to A1), so no need to do div by 2
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
55 if (address < 0x200000) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
56 return cart[address];
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
57 } else if(address >= 0x700000) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
58 return ram[address & 0x7FFF];
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
59 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
60 //TODO: Figure out what happens when you try to DMA from weird adresses like IO or banked Z80 area
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
61 return 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
62 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
63
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
64 #define VINT_CYCLE ((MCLKS_LINE * 226)/MCLKS_PER_68K)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
65
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
66 m68k_context * sync_components(m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
67 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
68 //TODO: Handle sync targets smaller than a single frame
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
69 vdp_context * v_context = context->next_context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
70 uint32_t mclks = context->current_cycle * MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
71 if (mclks >= MCLKS_PER_FRAME) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
72 //printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, mclks);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
73 vdp_run_context(v_context, MCLKS_PER_FRAME);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
74 wait_render_frame(v_context);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
75 mclks -= MCLKS_PER_FRAME;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
76 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
77 io_adjust_cycles(&gamepad_1, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
78 io_adjust_cycles(&gamepad_2, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
79 context->current_cycle -= MCLKS_PER_FRAME/MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
80 if (mclks) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
81 vdp_run_context(v_context, mclks);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
82 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
83 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
84 if (context->int_cycle > VINT_CYCLE) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
85 context->int_cycle = VINT_CYCLE;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
86 context->int_num = 6;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
87 if (context->int_cycle < context->sync_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
88 context->target_cycle = context->int_cycle;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
89 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
90 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
91 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
92 context->int_cycle = 0xFFFFFFFF;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
93 context->target_cycle = context->sync_cycle;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
94 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
95 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
96 //printf("running VDP for %d cycles\n", mclks - v_context->cycles);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
97 vdp_run_context(v_context, mclks);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
98 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
99 if (context->int_cycle > VINT_CYCLE) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
100 context->int_cycle = VINT_CYCLE;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
101 context->int_num = 6;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
102 if (context->int_cycle < context->sync_cycle && context->int_cycle < context->current_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
103 context->target_cycle = context->int_cycle;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
104 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
105 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
106 if (context->int_cycle <= context->current_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
107 context->int_cycle = CYCLE_NEVER;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
108 context->target_cycle = context->sync_cycle;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
109 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
110 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
111 context->int_cycle = CYCLE_NEVER;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
112 context->target_cycle = context->sync_cycle;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
113 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
114 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
115 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
116 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
117
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
118 m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_t value)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
119 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
120 //printf("vdp_port write: %X, value: %X, cycle: %d\n", vdp_port, value, context->current_cycle);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
121 sync_components(context);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
122 vdp_context * v_context = context->next_context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
123 if (vdp_port < 0x10) {
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
124 int blocked;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
125 if (vdp_port < 4) {
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
126 while (vdp_data_port_write(v_context, value) < 0) {
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
127 while(v_context->flags & FLAG_DMA_RUN) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
128 vdp_run_dma_done(v_context, MCLKS_PER_FRAME);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
129 if (v_context->cycles >= MCLKS_PER_FRAME) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
130 wait_render_frame(v_context);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
131 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
132 io_adjust_cycles(&gamepad_1, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
133 io_adjust_cycles(&gamepad_2, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
134 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
135 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
136 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
137 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
138 } else if(vdp_port < 8) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
139 blocked = vdp_control_port_write(v_context, value);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
140 if (blocked) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
141 while (blocked) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
142 while(v_context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
143 vdp_run_dma_done(v_context, MCLKS_PER_FRAME);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
144 if (v_context->cycles >= MCLKS_PER_FRAME) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
145 wait_render_frame(v_context);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
146 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
147 io_adjust_cycles(&gamepad_1, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
148 io_adjust_cycles(&gamepad_2, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
149 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
150 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
151 if (blocked < 0) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
152 blocked = vdp_control_port_write(v_context, value);
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
153 } else {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
154 blocked = 0;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
155 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
156 }
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 144
diff changeset
157 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
158 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
159 if (v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
160 if (context->int_cycle > VINT_CYCLE) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
161 context->int_cycle = VINT_CYCLE;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
162 context->int_num = 6;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
163 if (context->int_cycle < context->sync_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
164 context->target_cycle = context->int_cycle;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
165 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
166 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
167 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
168 context->int_cycle = 0xFFFFFFFF;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
169 context->target_cycle = context->sync_cycle;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
170 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
171 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
172 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
173 printf("Illegal write to HV Counter port %X\n", vdp_port);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
174 exit(1);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
175 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
176 context->current_cycle = v_context->cycles/MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 } else if (vdp_port < 0x18) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
178 //TODO: Implement PSG
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
180 //TODO: Implement undocumented test register(s)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
181 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
182 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
183 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
184
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
185 m68k_context * vdp_port_read(uint32_t vdp_port, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
186 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
187 sync_components(context);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
188 vdp_context * v_context = context->next_context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
189 if (vdp_port < 0x10) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
190 if (vdp_port < 4) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
191 context->value = vdp_data_port_read(v_context);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 } else if(vdp_port < 8) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
193 context->value = vdp_control_port_read(v_context);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 } else {
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 130
diff changeset
195 context->value = vdp_hv_counter_read(v_context);
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 130
diff changeset
196 //printf("HV Counter: %X at cycle %d\n", context->value, v_context->cycles);
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
197 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
198 context->current_cycle = v_context->cycles/MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
199 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
200 printf("Illegal read from PSG or test register port %X\n", vdp_port);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
201 exit(1);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
203 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
205
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
206 #define TH 0x40
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 #define TH_TIMEOUT 8000
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
208 #define Z80_ACK_DELAY 3 //TODO: Calculate this on the fly based on how synced up the Z80 and 68K clocks are
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210 uint8_t reset = 1;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 uint8_t busreq = 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 uint8_t busack = 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213 uint32_t busack_cycle = CYCLE_NEVER;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 uint8_t new_busack = 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
215
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216 void io_adjust_cycles(io_port * pad, uint32_t current_cycle, uint32_t deduction)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 {
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
218 /*uint8_t control = pad->control | 0x80;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219 uint8_t th = control & pad->output;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
220 if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 printf("adjust_cycles | control: %X, TH: %X, GAMEPAD_TH0: %X, GAMEPAD_TH1: %X, TH Counter: %d, Timeout: %d, Cycle: %d\n", control, th, pad->input[GAMEPAD_TH0], pad->input[GAMEPAD_TH1], pad->th_counter,pad->timeout_cycle, current_cycle);
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
222 }*/
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 if (current_cycle >= pad->timeout_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224 pad->th_counter = 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226 pad->timeout_cycle -= deduction;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
227 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 if (busack_cycle < CYCLE_NEVER && current_cycle < busack_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
229 busack_cycle -= deduction;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
230 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
231 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
232
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 void io_data_write(io_port * pad, m68k_context * context, uint8_t value)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
234 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 if (pad->control & TH) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 //check if TH has changed
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237 if ((pad->output & TH) ^ (value & TH)) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 if (context->current_cycle >= pad->timeout_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 pad->th_counter = 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
240 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 if (!(value & TH)) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242 pad->th_counter++;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
243 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 pad->timeout_cycle = context->current_cycle + TH_TIMEOUT;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
245 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
246 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
247 pad->output = value;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
248 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
249
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250 void io_data_read(io_port * pad, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
251 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
252 uint8_t control = pad->control | 0x80;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
253 uint8_t th = control & pad->output;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
254 uint8_t input;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
255 if (context->current_cycle >= pad->timeout_cycle) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
256 pad->th_counter = 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
257 }
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
258 /*if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) {
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
259 printf("io_data_read | control: %X, TH: %X, GAMEPAD_TH0: %X, GAMEPAD_TH1: %X, TH Counter: %d, Timeout: %d, Cycle: %d\n", control, th, pad->input[GAMEPAD_TH0], pad->input[GAMEPAD_TH1], pad->th_counter,pad->timeout_cycle, context->current_cycle);
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
260 }*/
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
261 if (th) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
262 if (pad->th_counter == 2) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
263 input = pad->input[GAMEPAD_EXTRA];
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
264 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 input = pad->input[GAMEPAD_TH1];
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
266 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
268 if (pad->th_counter == 2) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
269 input = pad->input[GAMEPAD_TH0] | 0xF;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
270 } else if(pad->th_counter == 3) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
271 input = pad->input[GAMEPAD_TH0] & 0x30;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
272 } else {
89
9757b4c6c33f Minor joypad fix and commeount out some debug printfs
Mike Pavone <pavone@retrodev.com>
parents: 88
diff changeset
273 input = pad->input[GAMEPAD_TH0] | 0xC;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
274 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
275 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
276 context->value = ((~input) & (~control)) | (pad->output & control);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
277 /*if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
278 printf ("value: %X\n", context->value);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
279 }*/
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
280 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
281
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
282 m68k_context * io_write(uint32_t location, m68k_context * context, uint8_t value)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
283 {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
284 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
285 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
286 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
287 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
288 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
289 if (!(busack || reset)) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
290 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
291 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
292 z80_ram[location & 0x1FFF] = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
293 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
294 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
295 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
296 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
297 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
298 switch(location/2)
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
299 {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
300 case 0x1:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
301 io_data_write(&gamepad_1, context, value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
302 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
303 case 0x2:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
304 io_data_write(&gamepad_2, context, value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
305 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
306 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
307 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
308 case 0x4:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
309 gamepad_1.control = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
310 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
311 case 0x5:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
312 gamepad_2.control = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
313 break;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
315 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
316 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
317 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
318 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
319 busack_cycle = CYCLE_NEVER;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
320 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
321 if (value & 1) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
322 busreq = 1;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
323 if(!reset) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
324 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
325 new_busack = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
326 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
327 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
328 busreq = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
329 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
330 busack = 1;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
331 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
332 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
333 if (value & 1) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
334 if (reset && busreq) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
335 new_busack = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
336 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
337 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
338 reset = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
339 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
340 reset = 1;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
341 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
342 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
344 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
346 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
347
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
348 m68k_context * io_write_w(uint32_t location, m68k_context * context, uint16_t value)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
349 {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
350 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
351 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
352 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
353 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
354 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
355 if (!(busack || reset)) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
356 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
357 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
358 z80_ram[location & 0x1FFE] = value >> 8;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
359 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
360 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
361 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
362 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
363 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
364 switch(location/2)
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
365 {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
366 case 0x1:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
367 io_data_write(&gamepad_1, context, value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
368 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
369 case 0x2:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
370 io_data_write(&gamepad_2, context, value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
371 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
372 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
373 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
374 case 0x4:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
375 gamepad_1.control = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
376 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
377 case 0x5:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
378 gamepad_2.control = value;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
379 break;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
381 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
382 //printf("IO Write of %X to %X @ %d\n", value, location, context->current_cycle);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
383 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
384 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
385 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
386 busack_cycle = CYCLE_NEVER;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
387 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
388 if (value & 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
389 busreq = 1;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
390 if(!reset) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
391 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
392 new_busack = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
393 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
394 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
395 busreq = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
396 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
397 busack = 1;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
399 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
400 if (value & 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
401 if (reset && busreq) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
402 new_busack = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
403 busack_cycle = context->current_cycle + Z80_ACK_DELAY;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
404 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
405 reset = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
406 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
407 reset = 1;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
408 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
410 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
411 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
412 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
414
130
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
415 #define USA 0x80
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
416 #define JAP 0x00
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
417 #define EUR 0xC0
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
418 #define NO_DISK 0x20
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
419 uint8_t version_reg = NO_DISK | USA;
0bdbffa9fe90 Make version register return correct value for USA
Mike Pavone <pavone@retrodev.com>
parents: 115
diff changeset
420
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
421 m68k_context * io_read(uint32_t location, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
422 {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
423 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
424 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
425 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
426 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
427 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
428 if (!(busack || reset)) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
429 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
430 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
431 context->value = z80_ram[location & 0x1FFF];
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
432 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
433 context->value = 0xFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
434 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
435 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
436 context->value = 0xFF;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
437 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
438 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
439 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
440 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
441 switch(location/2)
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
442 {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
443 case 0x0:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
444 //version bits should be 0 for now since we're not emulating TMSS
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
445 //Not sure about the other bits
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
446 context->value = version_reg;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
447 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
448 case 0x1:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
449 io_data_read(&gamepad_1, context);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
450 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
451 case 0x2:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
452 io_data_read(&gamepad_2, context);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
453 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
454 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
455 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
456 case 0x4:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
457 context->value = gamepad_1.control;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
458 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
459 case 0x5:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
460 context->value = gamepad_2.control;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
461 break;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
462 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
463 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
464 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
465 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
466 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
467 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
468 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
469 context->value = reset || busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
470 //printf("Byte read of BUSREQ returned %d @ %d (reset: %d, busack: %d)\n", context->value, context->current_cycle, reset, busack);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
471 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
472 context->value = !reset;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
473 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
474 printf("Byte read of unknown IO location: %X\n", location);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
475 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
476 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
477 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
478 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
479 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
480
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
481 m68k_context * io_read_w(uint32_t location, m68k_context * context)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
482 {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
483 if (location < 0x10000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
484 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
485 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
486 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
487 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
488 if (!(busack || reset)) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
489 location &= 0x7FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
490 if (location < 0x4000) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
491 context->value = z80_ram[location & 0x1FFE];
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
492 context->value |= context->value << 8;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
493 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
494 context->value = 0xFFFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
495 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
496 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
497 context->value = 0xFFFF;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
498 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
499 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
500 location &= 0x1FFF;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
501 if (location < 0x100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
502 switch(location/2)
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
503 {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
504 case 0x0:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
505 //version bits should be 0 for now since we're not emulating TMSS
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
506 //Not sure about the other bits
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
507 context->value = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
508 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
509 case 0x1:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
510 io_data_read(&gamepad_1, context);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
511 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
512 case 0x2:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
513 io_data_read(&gamepad_2, context);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
514 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
515 case 0x3://PORT C Data
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
516 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
517 case 0x4:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
518 context->value = gamepad_1.control;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
519 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
520 case 0x5:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
521 context->value = gamepad_2.control;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
522 break;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
523 case 0x6:
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
524 //PORT C Control
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
525 context->value = 0;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
526 break;
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
527 }
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
528 context->value = context->value | (context->value << 8);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
529 //printf("Word read to %X returned %d\n", location, context->value);
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
530 } else {
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
531 if (location == 0x1100) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
532 if (busack_cycle > context->current_cycle) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
533 busack = new_busack;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
534 busack_cycle = CYCLE_NEVER;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
535 }
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
536 context->value = (reset || busack) << 8;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
537 //printf("Word read of BUSREQ returned %d\n", context->value);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
538 } else if (location == 0x1200) {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
539 context->value = (!reset) << 8;
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
540 } else {
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
541 printf("Word read of unknown IO location: %X\n", location);
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
542 }
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
543 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
544 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
545 return context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
547
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
548 int main(int argc, char ** argv)
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
549 {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
550 if (argc < 2) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
551 fputs("Usage: blastem FILENAME\n", stderr);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
552 return 1;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
553 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
554 if(!load_rom(argv[1])) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
555 fprintf(stderr, "Failed to open %s for reading\n", argv[1]);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
556 return 1;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
557 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
558 int width = 320;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
559 int height = 240;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
560 if (argc > 2) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
561 width = atoi(argv[2]);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
562 if (argc > 3) {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
563 height = atoi(argv[3]);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
564 } else {
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
565 height = (width/320) * 240;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
566 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
567 }
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
568 render_init(width, height);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
569
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
570 x86_68k_options opts;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
571 m68k_context context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
572 vdp_context v_context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
573
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
574 init_x86_68k_opts(&opts);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
575 init_68k_context(&context, opts.native_code_map, &opts);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
576 init_vdp_context(&v_context);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
577 context.next_context = &v_context;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
578 //cartridge ROM
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
579 context.mem_pointers[0] = cart;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
580 context.target_cycle = context.sync_cycle = MCLKS_PER_FRAME/MCLKS_PER_68K;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
581 //work RAM
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
582 context.mem_pointers[1] = ram;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
583 uint32_t address;
103
a71544cd01ea Don't pre-emptively translate code at interrupt vectors as some PD ROMs have these pointing at junk. Need some kind of heuristic for detecting garbage if I'm going to translate them ahead of time by default.
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
584 /*address = cart[0x68/2] << 16 | cart[0x6A/2];
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 89
diff changeset
585 translate_m68k_stream(address, &context);
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
586 address = cart[0x70/2] << 16 | cart[0x72/2];
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 89
diff changeset
587 translate_m68k_stream(address, &context);
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
588 address = cart[0x78/2] << 16 | cart[0x7A/2];
103
a71544cd01ea Don't pre-emptively translate code at interrupt vectors as some PD ROMs have these pointing at junk. Need some kind of heuristic for detecting garbage if I'm going to translate them ahead of time by default.
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
589 translate_m68k_stream(address, &context);*/
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
590 address = cart[2] << 16 | cart[3];
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 89
diff changeset
591 translate_m68k_stream(address, &context);
88
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
592 m68k_reset(&context);
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
593 return 0;
c339559f1d4f Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
594 }