Mercurial > repos > blastem
annotate cpu_dsl.py @ 1620:a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
author | Michael Pavone <pavone@retrodev.com> |
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date | Thu, 04 Oct 2018 19:12:56 -0700 |
parents | 0e8438a4c76f |
children | ca158bc091f9 |
rev | line source |
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1 #!/usr/bin/env python3 |
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2 |
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3 |
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4 class Block: |
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5 def addOp(self, op): |
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6 pass |
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7 |
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8 def processLine(self, parts): |
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9 if parts[0] == 'switch': |
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10 o = Switch(self, parts[1]) |
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11 self.addOp(o) |
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12 return o |
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13 elif parts[0] == 'if': |
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14 o = If(self, parts[1]) |
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15 self.addOp(o) |
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16 return o |
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17 elif parts[0] == 'end': |
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18 raise Exception('end is only allowed inside a switch or if block') |
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19 else: |
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20 self.addOp(NormalOp(parts)) |
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21 return self |
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22 |
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23 def resolveLocal(self, name): |
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24 return None |
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25 |
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26 class ChildBlock(Block): |
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27 def processLine(self, parts): |
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28 if parts[0] == 'end': |
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29 return self.parent |
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30 return super().processLine(parts) |
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31 |
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32 #Represents an instruction of the emulated CPU |
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33 class Instruction(Block): |
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34 def __init__(self, value, fields, name): |
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35 self.value = value |
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36 self.fields = fields |
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37 self.name = name |
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38 self.implementation = [] |
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39 self.locals = {} |
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40 self.regValues = {} |
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41 self.varyingBits = 0 |
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42 self.invalidFieldValues = {} |
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43 self.newLocals = [] |
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44 for field in fields: |
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45 self.varyingBits += fields[field][1] |
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46 |
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47 def addOp(self, op): |
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48 if op.op == 'local': |
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49 name = op.params[0] |
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50 size = op.params[1] |
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51 self.locals[name] = size |
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52 elif op.op == 'invalid': |
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53 name = op.params[0] |
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54 value = int(op.params[1]) |
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55 self.invalidFieldValues.setdefault(name, set()).add(value) |
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56 else: |
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57 self.implementation.append(op) |
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58 |
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59 def resolveLocal(self, name): |
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60 if name in self.locals: |
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61 return name |
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62 return None |
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63 |
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64 def addLocal(self, name, size): |
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65 self.locals[name] = size |
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66 self.newLocals.append(name) |
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67 |
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68 def localSize(self, name): |
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69 return self.locals.get(name) |
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70 |
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71 def __lt__(self, other): |
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72 if isinstance(other, Instruction): |
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73 if self.varyingBits != other.varyingBits: |
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74 return self.varyingBits < other.varyingBits |
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75 return self.value < other.value |
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76 else: |
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77 return NotImplemented |
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78 |
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79 def allValues(self): |
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80 values = [] |
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81 for i in range(0, 1 << self.varyingBits): |
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82 iword = self.value |
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83 doIt = True |
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84 for field in self.fields: |
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85 shift,bits = self.fields[field] |
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86 val = i & ((1 << bits) - 1) |
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87 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]: |
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88 doIt = False |
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89 break |
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90 i >>= bits |
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91 iword |= val << shift |
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92 if doIt: |
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93 values.append(iword) |
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94 return values |
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95 |
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96 def getFieldVals(self, value): |
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97 fieldVals = {} |
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98 fieldBits = {} |
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99 for field in self.fields: |
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100 shift,bits = self.fields[field] |
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101 val = (value >> shift) & ((1 << bits) - 1) |
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102 fieldVals[field] = val |
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103 fieldBits[field] = bits |
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104 return (fieldVals, fieldBits) |
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105 |
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106 def generateName(self, value): |
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107 fieldVals,fieldBits = self.getFieldVals(value) |
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108 names = list(fieldVals.keys()) |
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109 names.sort() |
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110 funName = self.name |
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111 for name in names: |
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112 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name]) |
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113 return funName |
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114 |
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115 def generateBody(self, value, prog, otype): |
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116 output = [] |
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117 prog.meta = {} |
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118 prog.pushScope(self) |
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119 self.regValues = {} |
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120 for var in self.locals: |
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121 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)) |
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122 self.newLocals = [] |
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123 fieldVals,_ = self.getFieldVals(value) |
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124 for op in self.implementation: |
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125 op.generate(prog, self, fieldVals, output, otype) |
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126 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context)\n{' |
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127 if prog.needFlagCoalesce: |
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128 begin += prog.flags.coalesceFlags(prog, otype) |
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129 if prog.needFlagDisperse: |
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130 output.append(prog.flags.disperseFlags(prog, otype)) |
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131 for var in self.newLocals: |
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132 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var) |
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133 prog.popScope() |
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134 return begin + ''.join(output) + '\n}' |
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135 |
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136 def __str__(self): |
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137 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)] |
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138 for name in self.locals: |
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139 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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140 for op in self.implementation: |
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141 pieces.append(str(op)) |
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142 return ''.join(pieces) |
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143 |
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144 #Represents the definition of a helper function |
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145 class SubRoutine(Block): |
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146 def __init__(self, name): |
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147 self.name = name |
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148 self.implementation = [] |
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149 self.args = [] |
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150 self.arg_map = {} |
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151 self.locals = {} |
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152 self.regValues = {} |
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153 |
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154 def addOp(self, op): |
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155 if op.op == 'arg': |
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156 name = op.params[0] |
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157 size = op.params[1] |
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158 self.arg_map[name] = len(self.args) |
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159 self.args.append((name, size)) |
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160 elif op.op == 'local': |
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161 name = op.params[0] |
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162 size = op.params[1] |
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163 self.locals[name] = size |
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164 else: |
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165 self.implementation.append(op) |
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166 |
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167 def resolveLocal(self, name): |
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168 if name in self.locals: |
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169 return self.name + '_' + name |
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170 return None |
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171 |
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172 def addLocal(self, name, size): |
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173 self.locals[name] = size |
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174 |
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175 def localSize(self, name): |
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176 return self.locals.get(name) |
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177 |
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178 def inline(self, prog, params, output, otype, parent): |
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179 if len(params) != len(self.args): |
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180 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params))) |
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181 argValues = {} |
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182 if parent: |
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183 self.regValues = parent.regValues |
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184 prog.pushScope(self) |
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185 i = 0 |
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186 for name,size in self.args: |
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187 argValues[name] = params[i] |
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188 i += 1 |
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189 for name in self.locals: |
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190 size = self.locals[name] |
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191 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name)) |
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192 for op in self.implementation: |
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193 op.generate(prog, self, argValues, output, otype) |
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194 prog.popScope() |
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195 |
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196 def __str__(self): |
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197 pieces = [self.name] |
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198 for name,size in self.args: |
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199 pieces.append('\n\targ {0} {1}'.format(name, size)) |
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200 for name in self.locals: |
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201 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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202 for op in self.implementation: |
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203 pieces.append(str(op)) |
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204 return ''.join(pieces) |
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205 |
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206 class Op: |
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207 def __init__(self, evalFun = None): |
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208 self.evalFun = evalFun |
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209 self.impls = {} |
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210 self.outOp = () |
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211 def cBinaryOperator(self, op): |
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212 def _impl(prog, params): |
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213 if op == '-': |
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214 a = params[1] |
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215 b = params[0] |
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216 else: |
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217 a = params[0] |
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218 b = params[1] |
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219 return '\n\t{dst} = {a} {op} {b};'.format( |
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220 dst = params[2], a = a, b = b, op = op |
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221 ) |
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222 self.impls['c'] = _impl |
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223 self.outOp = (2,) |
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224 return self |
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225 def cUnaryOperator(self, op): |
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226 def _impl(prog, params): |
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227 return '\n\t{dst} = {op}{a};'.format( |
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228 dst = params[1], a = params[0], op = op |
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229 ) |
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230 self.impls['c'] = _impl |
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231 self.outOp = (1,) |
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232 return self |
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233 def addImplementation(self, lang, outOp, impl): |
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234 self.impls[lang] = impl |
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235 if not outOp is None: |
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236 if type(outOp) is tuple: |
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237 self.outOp = outOp |
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238 else: |
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239 self.outOp = (outOp,) |
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240 return self |
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241 def evaluate(self, params): |
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242 return self.evalFun(*params) |
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243 def canEval(self): |
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244 return not self.evalFun is None |
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245 def numArgs(self): |
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246 return self.evalFun.__code__.co_argcount |
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247 def generate(self, otype, prog, params, rawParams): |
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248 if self.impls[otype].__code__.co_argcount == 2: |
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249 return self.impls[otype](prog, params) |
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250 else: |
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251 return self.impls[otype](prog, params, rawParams) |
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252 |
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253 |
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254 def _xchgCImpl(prog, params, rawParams): |
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255 size = prog.paramSize(rawParams[0]) |
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256 decl,name = prog.getTemp(size) |
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257 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name) |
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258 |
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259 def _dispatchCImpl(prog, params): |
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260 if len(params) == 1: |
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261 table = 'main' |
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262 else: |
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263 table = params[1] |
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264 return '\n\timpl_{tbl}[{op}](context);'.format(tbl = table, op = params[0]) |
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265 |
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266 def _updateFlagsCImpl(prog, params, rawParams): |
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267 i = 0 |
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268 last = '' |
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269 autoUpdate = set() |
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270 explicit = {} |
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271 for c in params[0]: |
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272 if c.isdigit(): |
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273 if last.isalpha(): |
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274 num = int(c) |
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275 if num > 1: |
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276 raise Exception(c + ' is not a valid digit for update_flags') |
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277 explicit[last] = num |
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278 last = c |
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279 else: |
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280 raise Exception('Digit must follow flag letter in update_flags') |
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281 else: |
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282 if last.isalpha(): |
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283 autoUpdate.add(last) |
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284 last = c |
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285 if last.isalpha(): |
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286 autoUpdate.add(last) |
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287 output = [] |
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288 #TODO: handle autoUpdate flags |
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289 for flag in autoUpdate: |
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290 calc = prog.flags.flagCalc[flag] |
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291 calc,_,resultBit = calc.partition('-') |
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292 lastDst = prog.resolveParam(prog.lastDst, None, {}) |
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293 storage = prog.flags.getStorage(flag) |
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294 if calc == 'bit' or calc == 'sign': |
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295 if calc == 'sign': |
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296 resultBit = prog.paramSize(prog.lastDst) - 1 |
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297 else: |
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298 resultBit = int(resultBit) |
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299 if type(storage) is tuple: |
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300 reg,storageBit = storage |
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301 reg = prog.resolveParam(reg, None, {}) |
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302 if storageBit == resultBit: |
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303 #TODO: optimize this case |
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304 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} & {mask}U);'.format( |
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305 reg = reg, mask = 1 << resultBit, res = lastDst |
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306 )) |
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307 else: |
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308 if resultBit > storageBit: |
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309 op = '>>' |
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310 shift = resultBit - storageBit |
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311 else: |
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312 op = '<<' |
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313 shift = storageBit - resultBit |
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314 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} {op} {shift}U & {mask}U);'.format( |
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315 reg = reg, mask = 1 << storageBit, res = lastDst, op = op, shift = shift |
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316 )) |
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317 else: |
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318 reg = prog.resolveParam(storage, None, {}) |
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319 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=lastDst, mask = 1 << resultBit)) |
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320 elif calc == 'zero': |
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321 if type(storage) is tuple: |
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322 reg,storageBit = storage |
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323 reg = prog.resolveParam(reg, None, {}) |
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324 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format( |
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325 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit |
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326 )) |
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327 elif prog.paramSize(prog.lastDst) > prog.paramSize(storage): |
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328 reg = prog.resolveParam(storage, None, {}) |
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329 output.append('\n\t{reg} = {res} != 0;'.format( |
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330 reg = reg, res = lastDst |
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331 )) |
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332 else: |
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333 reg = prog.resolveParam(storage, None, {}) |
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334 output.append('\n\t{reg} = {res};'.format(reg = reg, res = lastDst)) |
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335 elif calc == 'half-carry': |
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336 pass |
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337 elif calc == 'carry': |
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338 pass |
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339 elif calc == 'overflow': |
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340 pass |
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341 elif calc == 'parity': |
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342 pass |
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343 #TODO: combine explicit flags targeting the same storage location |
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344 for flag in explicit: |
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345 location = prog.flags.getStorage(flag) |
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346 if type(location) is tuple: |
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347 reg,bit = location |
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348 reg = prog.resolveReg(reg, None, {}) |
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349 value = str(1 << bit) |
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350 if explicit[flag]: |
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351 operator = '|=' |
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352 else: |
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353 operator = '&=' |
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354 value = '~' + value |
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355 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value)) |
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356 else: |
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357 reg = prog.resolveReg(location, None, {}) |
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358 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag])) |
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359 return ''.join(output) |
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360 |
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361 def _cmpCImpl(prog, params): |
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362 size = prog.paramSize(params[1]) |
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363 tmpvar = 'cmp_tmp{sz}__'.format(sz=size) |
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364 typename = '' |
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365 scope = prog.getRootScope() |
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366 if not scope.resolveLocal(tmpvar): |
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367 scope.addLocal(tmpvar, size) |
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368 prog.lastDst = tmpvar |
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369 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1]) |
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370 |
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371 def _asrCImpl(prog, params, rawParams): |
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372 shiftSize = prog.paramSize(rawParams[0]) |
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373 mask = 1 << (shiftSize - 1) |
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374 return '\n\t{dst} = ({a} >> {b}) | ({a} & {mask});'.format(a = params[0], b = params[1], dst = params[2], mask = mask) |
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375 |
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376 _opMap = { |
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377 'mov': Op(lambda val: val).cUnaryOperator(''), |
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378 'not': Op(lambda val: ~val).cUnaryOperator('~'), |
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379 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), |
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380 'neg': Op(lambda val: -val).cUnaryOperator('-'), |
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381 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), |
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382 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), |
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383 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), |
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384 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), |
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385 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), |
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386 'and': Op(lambda a, b: a & b).cBinaryOperator('&'), |
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387 'or': Op(lambda a, b: a | b).cBinaryOperator('|'), |
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388 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'), |
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389 'abs': Op(lambda val: abs(val)).addImplementation( |
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390 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0]) |
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391 ), |
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392 'cmp': Op().addImplementation('c', None, _cmpCImpl), |
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393 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( |
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394 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) |
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395 )), |
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396 'cycles': Op().addImplementation('c', None, |
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397 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format( |
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398 params[0] |
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399 ) |
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400 ), |
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401 'addsize': Op( |
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402 lambda a, b: b + (2 * a if a else 1) |
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403 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + {sz} ? {sz} * 2 : 1;'.format( |
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404 dst = params[2], sz = params[0], val = params[1] |
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405 )), |
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406 'decsize': Op( |
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407 lambda a, b: b - (2 * a if a else 1) |
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408 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - {sz} ? {sz} * 2 : 1;'.format( |
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409 dst = params[2], sz = params[0], val = params[1] |
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410 )), |
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411 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl), |
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412 'dispatch': Op().addImplementation('c', None, _dispatchCImpl), |
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413 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl) |
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414 } |
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415 |
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416 #represents a simple DSL instruction |
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417 class NormalOp: |
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418 def __init__(self, parts): |
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419 self.op = parts[0] |
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420 self.params = parts[1:] |
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421 |
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422 def generate(self, prog, parent, fieldVals, output, otype): |
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423 procParams = [] |
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424 allParamsConst = True |
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425 opDef = _opMap.get(self.op) |
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426 for param in self.params: |
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427 allowConst = (self.op in prog.subroutines or len(procParams) != len(self.params) - 1) and param in parent.regValues |
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428 isDst = (not opDef is None) and len(procParams) in opDef.outOp |
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429 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst) |
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430 |
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431 if (not type(param) is int) and len(procParams) != len(self.params) - 1: |
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432 allParamsConst = False |
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433 procParams.append(param) |
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434 |
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435 if self.op == 'meta': |
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436 param,_,index = self.params[1].partition('.') |
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437 if index: |
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438 index = (parent.resolveLocal(index) or index) |
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439 if index in fieldVals: |
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440 index = str(fieldVals[index]) |
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441 param = param + '.' + index |
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442 else: |
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443 param = parent.resolveLocal(param) or param |
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444 if param in fieldVals: |
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445 param = fieldVals[index] |
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446 prog.meta[self.params[0]] = param |
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447 elif self.op == 'dis': |
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448 #TODO: Disassembler |
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449 pass |
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450 elif not opDef is None: |
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451 if opDef.canEval() and allParamsConst: |
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452 #do constant folding |
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453 if opDef.numArgs() >= len(procParams): |
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454 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')') |
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455 dst = self.params[opDef.numArgs()] |
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456 result = opDef.evaluate(procParams[:opDef.numArgs()]) |
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457 while dst in prog.meta: |
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458 dst = prog.meta[dst] |
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459 maybeLocal = parent.resolveLocal(dst) |
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460 if maybeLocal: |
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461 dst = maybeLocal |
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462 parent.regValues[dst] = result |
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463 if prog.isReg(dst): |
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464 output.append(_opMap['mov'].generate(otype, prog, procParams, self.params)) |
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465 else: |
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466 output.append(opDef.generate(otype, prog, procParams, self.params)) |
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467 elif self.op in prog.subroutines: |
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468 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent) |
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469 else: |
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470 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');') |
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471 prog.lastOp = self |
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472 |
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473 def __str__(self): |
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474 return '\n\t' + self.op + ' ' + ' '.join(self.params) |
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475 |
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476 #represents a DSL switch construct |
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477 class Switch(ChildBlock): |
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478 def __init__(self, parent, param): |
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479 self.op = 'switch' |
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480 self.parent = parent |
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481 self.param = param |
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482 self.cases = {} |
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483 self.regValues = None |
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484 self.current_locals = {} |
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485 self.case_locals = {} |
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486 self.current_case = None |
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487 self.default = None |
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488 self.default_locals = None |
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489 |
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490 def addOp(self, op): |
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491 if op.op == 'case': |
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492 val = int(op.params[0], 16) if op.params[0].startswith('0x') else int(op.params[0]) |
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493 self.cases[val] = self.current_case = [] |
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494 self.case_locals[val] = self.current_locals = {} |
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495 elif op.op == 'default': |
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496 self.default = self.current_case = [] |
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497 self.default_locals = self.current_locals = {} |
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498 elif self.current_case == None: |
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499 raise ion('Orphan instruction in switch') |
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500 elif op.op == 'local': |
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501 name = op.params[0] |
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502 size = op.params[1] |
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503 self.current_locals[name] = size |
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504 else: |
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505 self.current_case.append(op) |
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506 |
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507 def resolveLocal(self, name): |
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508 if name in self.current_locals: |
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509 return name |
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510 return self.parent.resolveLocal(name) |
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511 |
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512 def addLocal(self, name, size): |
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513 self.current_locals[name] = size |
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514 |
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515 def localSize(self, name): |
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516 if name in self.current_locals: |
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517 return self.current_locals[name] |
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518 return self.parent.localSize(name) |
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519 |
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520 def generate(self, prog, parent, fieldVals, output, otype): |
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521 prog.pushScope(self) |
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522 param = prog.resolveParam(self.param, parent, fieldVals) |
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523 if type(param) is int: |
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524 self.regValues = self.parent.regValues |
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525 if param in self.cases: |
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526 self.current_locals = self.case_locals[param] |
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527 output.append('\n\t{') |
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528 for local in self.case_locals[param]: |
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529 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local)) |
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530 for op in self.cases[param]: |
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531 op.generate(prog, self, fieldVals, output, otype) |
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532 output.append('\n\t}') |
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533 elif self.default: |
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534 self.current_locals = self.default_locals |
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535 output.append('\n\t{') |
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536 for local in self.default_locals: |
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537 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local)) |
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538 for op in self.default: |
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539 op.generate(prog, self, fieldVals, output, otype) |
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540 output.append('\n\t}') |
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541 else: |
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542 output.append('\n\tswitch(' + param + ')') |
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543 output.append('\n\t{') |
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544 for case in self.cases: |
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545 self.current_locals = self.case_locals[case] |
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546 self.regValues = dict(self.parent.regValues) |
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547 output.append('\n\tcase {0}U: '.format(case) + '{') |
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548 for local in self.case_locals[case]: |
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549 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local)) |
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550 for op in self.cases[case]: |
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551 op.generate(prog, self, fieldVals, output, otype) |
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552 output.append('\n\tbreak;') |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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553 output.append('\n\t}') |
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554 if self.default: |
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555 self.current_locals = self.default_locals |
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556 self.regValues = dict(self.parent.regValues) |
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557 output.append('\n\tdefault: {') |
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558 for local in self.default_locals: |
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559 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local)) |
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560 for op in self.default: |
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561 op.generate(prog, self, fieldVals, output, otype) |
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562 output.append('\n\t}') |
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563 prog.popScope() |
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564 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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565 def __str__(self): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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566 keys = self.cases.keys() |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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567 keys.sort() |
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568 lines = ['\n\tswitch'] |
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569 for case in keys: |
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570 lines.append('\n\tcase {0}'.format(case)) |
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571 lines.append(''.join([str(op) for op in self.cases[case]])) |
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572 lines.append('\n\tend') |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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573 return ''.join(lines) |
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574 |
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575 |
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576 def _geuCImpl(prog, parent, fieldVals, output): |
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577 if prog.lastOp.op == 'cmp': |
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578 output.pop() |
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579 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
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580 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{' |
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581 else: |
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582 raise ion(">=U not implemented in the general case yet") |
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583 |
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584 _ifCmpImpl = { |
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585 'c': { |
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586 '>=U': _geuCImpl |
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587 } |
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588 } |
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589 #represents a DSL conditional construct |
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590 class If(ChildBlock): |
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591 def __init__(self, parent, cond): |
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592 self.op = 'if' |
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593 self.parent = parent |
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594 self.cond = cond |
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595 self.body = [] |
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596 self.elseBody = [] |
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597 self.curBody = self.body |
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598 self.locals = {} |
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599 self.elseLocals = {} |
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600 self.curLocals = self.locals |
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601 self.regValues = None |
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602 |
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603 def addOp(self, op): |
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604 if op.op in ('case', 'arg'): |
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605 raise Exception(self.op + ' is not allows inside an if block') |
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606 if op.op == 'local': |
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607 name = op.params[0] |
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608 size = op.params[1] |
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609 self.locals[name] = size |
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610 elif op.op == 'else': |
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611 self.curLocals = self.elseLocals |
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612 self.curBody = self.elseBody |
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613 else: |
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614 self.curBody.append(op) |
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615 |
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616 def localSize(self, name): |
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617 return self.curLocals.get(name) |
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618 |
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619 def resolveLocal(self, name): |
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620 if name in self.locals: |
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621 return name |
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622 return self.parent.resolveLocal(name) |
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623 |
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624 def _genTrueBody(self, prog, fieldVals, output, otype): |
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625 self.curLocals = self.locals |
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626 for local in self.locals: |
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627 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local)) |
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628 for op in self.body: |
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629 op.generate(prog, self, fieldVals, output, otype) |
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630 |
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631 def _genFalseBody(self, prog, fieldVals, output, otype): |
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632 self.curLocals = self.elseLocals |
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633 for local in self.elseLocals: |
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634 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local)) |
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635 for op in self.elseBody: |
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636 op.generate(prog, self, fieldVals, output, otype) |
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637 |
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638 def _genConstParam(self, param, prog, fieldVals, output, otype): |
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639 if param: |
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640 self._genTrueBody(prog, fieldVals, output, otype) |
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641 else: |
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642 self._genFalseBody(prog, fieldVals, output, otype) |
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643 |
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644 def generate(self, prog, parent, fieldVals, output, otype): |
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645 self.regValues = parent.regValues |
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646 try: |
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647 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype) |
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648 except Exception: |
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649 if self.cond in _ifCmpImpl[otype]: |
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650 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output)) |
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651 self._genTrueBody(prog, fieldVals, output, otype) |
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652 if self.elseBody: |
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changeset
|
653 output.append('\n\t} else {') |
1618
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|
654 self._genFalseBody(prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
655 output.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
656 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
657 cond = prog.resolveParam(self.cond, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
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|
658 if type(cond) is int: |
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|
659 self._genConstParam(cond, prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
660 else: |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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1613
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|
661 output.append('\n\tif ({cond}) '.format(cond=cond) + '{') |
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|
662 self._genTrueBody(prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
663 if self.elseBody: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
664 output.append('\n\t} else {') |
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|
665 self._genFalseBody(prog, fieldVals, output, otype) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
666 output.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
667 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
668 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
669 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
670 lines = ['\n\tif'] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
671 for op in self.body: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
672 lines.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
673 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
674 return ''.join(lines) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
675 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
676 class Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
677 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
678 self.regs = {} |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
679 self.regArrays = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
680 self.regToArray = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
681 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
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|
682 def addReg(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
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|
683 self.regs[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
684 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
685 def addRegArray(self, name, size, regs): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
686 self.regArrays[name] = (size, regs) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
687 idx = 0 |
1615
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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
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|
688 if not type(regs) is int: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
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|
689 for reg in regs: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
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|
690 self.regs[reg] = size |
28f80d1b343e
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|
691 self.regToArray[reg] = (name, idx) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
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|
692 idx += 1 |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
693 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
694 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
695 return name in self.regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
696 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
697 def isRegArray(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
698 return name in self.regArrays |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
699 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 def isRegArrayMember(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 return name in self.regToArray |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
702 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
703 def arrayMemberParent(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 return self.regToArray[name][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
706 def arrayMemberIndex(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 return self.regToArray[name][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
708 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 def arrayMemberName(self, array, index): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
710 if type(index) is int and not type(self.regArrays[array][1]) is int: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
711 return self.regArrays[array][1][index] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
712 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
713 return None |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
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|
714 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
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|
715 def isNamedArray(self, array): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
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1614
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|
716 return array in self.regArrays and type(self.regArrays[array][1]) is int |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
717 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 def processLine(self, parts): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
719 if len(parts) == 3: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
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|
720 self.addRegArray(parts[0], int(parts[1]), int(parts[2])) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
721 elif len(parts) > 2: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
722 self.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
723 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
724 self.addReg(parts[0], int(parts[1])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
725 return self |
1618
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
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diff
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|
726 |
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parents:
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diff
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|
727 def writeHeader(self, otype, hFile): |
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
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|
728 fieldList = [] |
5dbc453cd345
Getting SVP core closer to compiling
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diff
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|
729 for reg in self.regs: |
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diff
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|
730 if not self.isRegArrayMember(reg): |
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Michael Pavone <pavone@retrodev.com>
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|
731 fieldList.append((self.regs[reg], 1, reg)) |
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parents:
1616
diff
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|
732 for arr in self.regArrays: |
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parents:
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|
733 size,regs = self.regArrays[arr] |
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parents:
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|
734 if not type(regs) is int: |
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parents:
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diff
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|
735 regs = len(regs) |
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parents:
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|
736 fieldList.append((size, regs, arr)) |
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parents:
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|
737 fieldList.sort() |
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parents:
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diff
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|
738 fieldList.reverse() |
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parents:
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diff
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|
739 for size, count, name in fieldList: |
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parents:
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|
740 if count > 1: |
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parents:
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diff
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|
741 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count)) |
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parents:
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diff
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|
742 else: |
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parents:
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diff
changeset
|
743 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
744 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 class Flags: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 self.flagBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 self.flagCalc = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 self.flagStorage = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 self.flagReg = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 self.maxBit = -1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
752 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 if parts[0] == 'register': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
755 self.flagReg = parts[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
756 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
757 flag,bit,calc,storage = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 bit,_,top = bit.partition('-') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 bit = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 if top: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 top = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 if top > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 self.maxBit = top |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 self.flagBits[flag] = (bit,top) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 if bit > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 self.maxBit = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 self.flagBits[flag] = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 self.flagCalc[flag] = calc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 self.flagStorage[flag] = storage |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
771 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
772 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
773 def getStorage(self, flag): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
774 if not flag in self.flagStorage: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
775 raise Exception('Undefined flag ' + flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
776 loc,_,bit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
777 if bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
778 return (loc, int(bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
779 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
780 return loc |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
781 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
782 def disperseFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
783 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
784 src = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
785 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
786 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
788 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
789 bot,top = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 mask = ((1 << (top + 1 - bot)) - 1) << bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 output.append('\n\t{dst} = {src} & mask;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 bitToFlag[self.flagBits[flag]] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
799 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 field,_,dstbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 dst = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 if dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 dstbit = int(dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 multi.setdefault(dst, []).append((dstbit, bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 for dst in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 didClear = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 direct = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
810 for dstbit, bit in multi[dst]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 if dstbit == bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 direct.append(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
813 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 if not didClear: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 output.append('\n\t{dst} = 0;'.format(dst=dst)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 didClear = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 if dstbit > bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 shift = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
819 diff = dstbit - bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 shift = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 diff = bit - dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 output.append('\n\t{dst} |= {src} {shift} {diff} & {mask};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 if len(direct) == len(multi[dst]): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 mask = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 for bit in direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 mask = mask | (1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 def coalesceFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 dst = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 output = ['\n\t{dst} = 0;'.format(dst=dst)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 bot,_ = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 src = prog.resolveReg(self.flagStorage[flag], None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 if bot: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 output.append('\n\t{dst} |= {src} << {shift};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
847 dst=dst, src = src, shift = bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 output.append('\n\t{dst} |= {src};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 dst=dst, src = src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
853 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
854 bitToFlag[bit] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
855 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 field,_,srcbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 src = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 if srcbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 srcbit = int(srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 multi.setdefault(src, []).append((srcbit,bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 output.append('\n\tif ({src}) {{\n\t\t{dst} |= 1 << {bit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 dst=dst, src=src, bit=bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 for src in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 direct = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 for srcbit, dstbit in multi[src]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 if srcbit == dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 direct = direct | (1 << srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} |= 1 << {dstbit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 output.append('\n\t{dst} |= {src} & {mask}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 dst=dst, src=src, mask=direct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 class Program: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 def __init__(self, regs, instructions, subs, info, flags): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 self.regs = regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 self.instructions = instructions |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 self.subroutines = subs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 self.booleans = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 self.prefix = info.get('prefix', [''])[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 self.opsize = int(info.get('opcode_size', ['8'])[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 self.extra_tables = info.get('extra_tables', []) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 self.context_type = self.prefix + 'context' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 self.body = info.get('body', [None])[0] |
1620
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Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents:
1619
diff
changeset
|
896 self.includes = info.get('include', []) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 self.flags = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 self.lastDst = None |
1618
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Getting SVP core closer to compiling
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parents:
1616
diff
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|
899 self.scopes = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 self.currentScope = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 pieces = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 for reg in self.regs: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 pieces.append(str(self.regs[reg])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 for name in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 pieces.append('\n'+str(self.subroutines[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 for instruction in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 pieces.append('\n'+str(instruction)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
913 def writeHeader(self, otype, header): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
914 hFile = open(header, 'w') |
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
915 macro = header.upper().replace('.', '_') |
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
916 hFile.write('#ifndef {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
917 hFile.write('\n#define {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
918 hFile.write('\n#include "backend.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
919 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
920 hFile.write('\n\tcpu_options gen;') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
921 hFile.write('\n}} {0}options;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
922 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
923 hFile.write('\n\t{0}options *opts;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
924 hFile.write('\n\tuint32_t cycles;') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
925 self.regs.writeHeader(otype, hFile) |
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
926 hFile.write('\n}} {0}context;'.format(self.prefix)) |
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
927 hFile.write('\n') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
928 hFile.write('\n#endif //{0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
929 hFile.write('\n') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
930 hFile.close() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 def build(self, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 body = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 pieces = [] |
1620
a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents:
1619
diff
changeset
|
934 for include in self.includes: |
a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents:
1619
diff
changeset
|
935 body.append('#include "{0}"\n'.format(include)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 for table in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 opmap = [None] * (1 << self.opsize) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 bodymap = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 instructions = self.instructions[table] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 instructions.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 for inst in instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 for val in inst.allValues(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 if opmap[val] is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 self.needFlagCoalesce = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 self.needFlagDisperse = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 opmap[val] = inst.generateName(val) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 bodymap[val] = inst.generateBody(val, self, otype) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 |
1618
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parents:
1616
diff
changeset
|
952 pieces.append('\ntypedef void (*impl_fun)({pre}context *context);'.format(pre=self.prefix)) |
5dbc453cd345
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Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
953 pieces.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 for inst in range(0, len(opmap)): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 op = opmap[inst] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 if op is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 pieces.append('\n\tunimplemented,') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 pieces.append('\n\t' + op + ',') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 body.append(bodymap[inst]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 pieces.append('\n};') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 if self.body in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 pieces.append('\n{') |
1618
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Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
965 pieces.append('\n\twhile (context->cycles < target_cycle)') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 pieces.append('\n\t{') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 self.subroutines[self.body].inline(self, [], pieces, otype, None) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 pieces.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 pieces.append('\n}') |
1618
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Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
972 body.append('\nstatic void unimplemented({pre}context *context)'.format(pre = self.prefix)) |
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Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
973 body.append('\n{') |
5dbc453cd345
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parents:
1616
diff
changeset
|
974 body.append('\n\tfatal_error("Unimplemented instruction");') |
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Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
975 body.append('\n}\n') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 return ''.join(body) + ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 def checkBool(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 if not name in self.booleans: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 raise Exception(name + ' is not a defined boolean flag') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 return self.booleans[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 def getTemp(self, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 if size in self.temp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 return ('', self.temp[size]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 self.temp[size] = 'tmp{sz}'.format(sz=size); |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 return ('\n\tuint{sz}_t tmp{sz};'.format(sz=size), self.temp[size]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 while keepGoing: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 keepGoing = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 try: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 if type(param) is int: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 elif param.startswith('0x'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 param = int(param, 16) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 param = int(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 except ValueError: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 if param in parent.regValues and allowConstant: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 return parent.regValues[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 maybeLocal = parent.resolveLocal(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 if maybeLocal: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 return maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 if param in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 param = fieldVals[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 elif param in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 param = self.meta[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 elif self.isReg(param): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 param = self.resolveReg(param, parent, fieldVals, isdst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 return param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 if not type(name) is str: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 return False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 return self.regs.isRegArray(begin) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1025 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 return self.regs.isReg(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 def resolveReg(self, name, parent, fieldVals, isDst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 begin,sep,end = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 if not self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 end = self.resolveParam(end, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 if not type(end) is int and self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 arrayName = self.regs.arrayMemberParent(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 end = self.regs.arrayMemberIndex(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 if arrayName != begin: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 end = 'context->{0}[{1}]'.format(arrayName, end) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1040 if self.regs.isNamedArray(begin): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1041 regName = self.regs.arrayMemberName(begin, end) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1042 else: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1043 regName = '{0}.{1}'.format(begin, end) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 ret = 'context->{0}[{1}]'.format(begin, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 regName = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 if self.regs.isRegArrayMember(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 arr,idx = self.regs.regToArray[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1049 ret = 'context->{0}[{1}]'.format(arr, idx) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 ret = 'context->' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 if regName == self.flags.flagReg: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 self.needFlagDisperse = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 self.needFlagCoalesce = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 self.lastDst = regName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 return ret |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 def paramSize(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 size = self.currentScope.localSize(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 if size: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 return size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 if sep and self.regs.isRegArray(begin): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 return self.regs.regArrays[begin][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 if self.regs.isReg(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 return self.regs.regs[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 return 32 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1073 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1074 def pushScope(self, scope): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1075 self.scopes.append(scope) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1076 self.currentScope = scope |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1077 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1078 def popScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1079 ret = self.scopes.pop() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1080 self.currentScope = self.scopes[-1] if self.scopes else None |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1081 return ret |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1082 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1083 def getRootScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1084 return self.scopes[0] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1085 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1086 def parse(f): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 instructions = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1088 subroutines = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1089 registers = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1090 flags = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1091 errors = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 info = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1093 line_num = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 cur_object = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1095 for line in f: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1096 line_num += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1097 line,_,comment = line.partition('#') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1098 if not line.strip(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1099 continue |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1100 if line[0].isspace(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1101 if not cur_object is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1102 parts = [el.strip() for el in line.split(' ')] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1103 if type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1104 cur_object[parts[0]] = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1105 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1106 cur_object = cur_object.processLine(parts) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1107 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1108 # if type(cur_object) is Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1109 # if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1110 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1111 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1112 # cur_object.addReg(parts[0], int(parts[1])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1113 # elif type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1114 # cur_object[parts[0]] = parts[1:] |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1115 # elif parts[0] == 'switch': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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1116 # o = Switch(cur_object, parts[1]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1117 # cur_object.addOp(o) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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1118 # cur_object = o |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
1119 # elif parts[0] == 'if': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1120 # o = If(cur_object, parts[1]) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1121 # cur_object.addOp(o) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1122 # cur_object = o |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1123 # elif parts[0] == 'end': |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1124 # cur_object = cur_object.parent |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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1125 # else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
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|
1126 # cur_object.addOp(NormalOp(parts)) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1127 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1128 errors.append("Orphan instruction on line {0}".format(line_num)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1129 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1130 parts = line.split(' ') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1131 if len(parts) > 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1132 if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1133 table,bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1134 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1135 bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1136 table = 'main' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1137 value = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1138 fields = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1139 curbit = len(bitpattern) - 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1140 for char in bitpattern: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1141 value <<= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1142 if char in ('0', '1'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 value |= int(char) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1144 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1145 if char in fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1146 fields[char] = (curbit, fields[char][1] + 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1147 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1148 fields[char] = (curbit, 1) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1149 curbit -= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1150 cur_object = Instruction(value, fields, name.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1151 instructions.setdefault(table, []).append(cur_object) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1152 elif line.strip() == 'regs': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1153 if registers is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1154 registers = Registers() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1155 cur_object = registers |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1156 elif line.strip() == 'info': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1157 cur_object = info |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1158 elif line.strip() == 'flags': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1159 if flags is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1160 flags = Flags() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1161 cur_object = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1162 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1163 cur_object = SubRoutine(line.strip()) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1164 subroutines[cur_object.name] = cur_object |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1165 if errors: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1166 print(errors) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1167 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1168 p = Program(registers, instructions, subroutines, info, flags) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1169 p.booleans['dynarec'] = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1170 p.booleans['interp'] = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1171 |
1618
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
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|
1172 if 'header' in info: |
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
1173 print('#include "{0}"'.format(info['header'][0])) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
1174 p.writeHeader('c', info['header'][0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
1175 print('#include "util.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
1176 print('#include <stdlib.h>') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1177 print(p.build('c')) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1178 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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|
1179 def main(argv): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1180 f = open(argv[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1181 parse(f) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1182 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1183 if __name__ == '__main__': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1184 from sys import argv |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1185 main(argv) |