repos/blastem: 68kinst.c annotate

annotate 68kinst.c @ 15:c0f339564819

Make x86 generator generic with respect to operand size for immediate parameters.

author	Mike Pavone <pavone@retrodev.com>
date	Tue, 27 Nov 2012 22:43:32 -0800
parents	168b1a873895
children	3e7bfde7606e

rev	line source
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "68kinst.h"
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2 #include <string.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	3 #include <stdio.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	4
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	5 uint32_t sign_extend16(uint32_t val)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	6 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	7 return (val & 0x8000) ? val \| 0xFFFF0000 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	8 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	9
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	10 uint32_t sign_extend8(uint32_t val)
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	12 return (val & 0x80) ? val \| 0xFFFFFF00 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	13 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	14
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	15 uint16_t m68k_decode_op_ex(uint16_t cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	16 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	17 uint16_t ext;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 dst->addr_mode = mode;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 switch(mode)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 case MODE_REG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 case MODE_AREG:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	23 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	24 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	25 case MODE_AREG_PREDEC:
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 dst->params.regs.pri = reg;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	28 case MODE_AREG_DISPLACE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	29 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	30 dst->params.regs.pri = reg;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	31 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	32 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	33 case MODE_AREG_INDEX_MEM:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	34 //TODO: implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	35 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	36 case MODE_PC_INDIRECT_ABS_IMMED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	37 switch(reg)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	38 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	39 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	40 dst->addr_mode = MODE_ABSOLUTE_SHORT;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	41 ext = *(++cur);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	42 dst->params.immed = sign_extend16(ext);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	43 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	44 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	45 dst->addr_mode = MODE_ABSOLUTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	46 ext = *(++cur);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	47 dst->params.immed = ext << 16 \| *(++cur);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	48 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	49 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	50 dst->addr_mode = MODE_PC_DISPLACE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	51 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	52 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	53 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	54 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	55 dst->addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	56 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	57 switch (size)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	58 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	59 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	60 dst->params.immed = ext & 0xFF;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	61 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	62 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	63 dst->params.immed = ext;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	64 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	65 case OPSIZE_LONG:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	66 dst->params.immed = ext << 16 \| *(++cur);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	67 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	68 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	69 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	70 //TODO: implement the rest of these
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	71 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	72 break;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	74 return cur;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	75 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	76
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	77 uint16_t m68k_decode_op(uint16_t cur, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	78 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	79 uint8_t mode = (*cur >> 3) & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	80 uint8_t reg = *cur & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	81 return m68k_decode_op_ex(cur, mode, reg, size, dst);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	82 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	83
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	84 void m68k_decode_cond(uint16_t op, m68kinst * decoded)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	85 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	86 decoded->extra.cond = (op >> 0x8) & 0xF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	87 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	88
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	89 uint8_t m68K_reg_quick_field(uint16_t op)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	90 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	91 return (op >> 9) & 0x7;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	93
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 uint16_t * m68K_decode(uint16_t * istream, m68kinst * decoded)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 uint8_t optype = *istream >> 12;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 uint8_t size;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	98 uint8_t reg;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	99 uint8_t opmode;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	100 uint32_t immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	101 decoded->op = M68K_INVALID;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	102 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	103 decoded->variant = VAR_NORMAL;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 switch(optype)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 case BIT_MOVEP_IMMED:
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	107 if (*istream & 0x100) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	108 //BTST, BCHG, BCLR, BSET
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	109 switch ((*istream >> 6) & 0x3)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	110 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	111 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	112 decoded->op = M68K_BTST;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	113 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	114 case 1:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	115 decoded->op = M68K_BCHG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	116 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	117 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	118 decoded->op = M68K_BCLR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	119 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	120 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	121 decoded->op = M68K_BSET;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	122 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	123 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	124 decoded->src.addr_mode = MODE_REG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	125 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	126 decoded->extra.size = OPSIZE_LONG;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	127 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->dst));
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	128 } else if ((*istream & 0xF00) == 0x800) {
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	129 //BTST, BCHG, BCLR, BSET
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	130 switch ((*istream >> 6) & 0x3)
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	131 {
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	132 case 0:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	133 decoded->op = M68K_BTST;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	134 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	135 case 1:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	136 decoded->op = M68K_BCHG;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	137 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	138 case 2:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	139 decoded->op = M68K_BCLR;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	140 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	141 case 3:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	142 decoded->op = M68K_BSET;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	143 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	144 }
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	145 opmode = (*istream >> 3) & 0x7;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	146 reg = *istream & 0x7;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	147 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	148 decoded->src.params.immed = *(++istream) & 0xFF;
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	149 decoded->extra.size = OPSIZE_BYTE;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	150 istream = m68k_decode_op_ex(istream, opmode, reg, OPSIZE_BYTE, &(decoded->dst));
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	151 } else if ((*istream & 0xC0) == 0xC0) {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	152 #ifdef M68020
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	153 //CMP2, CHK2, CAS, CAS2, RTM, CALLM
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	154 #endif
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	155 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	156 switch ((*istream >> 9) & 0x7)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	157 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	158 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	159 if ((*istream & 0xFF) == 0x3C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	160 decoded->op = M68K_ORI_CCR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	161 decoded->extra.size = OPSIZE_BYTE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	162 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	163 decoded->src.params.immed = *(++istream) & 0xFF;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	164 } else if((*istream & 0xFF) == 0x7C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	165 decoded->op = M68K_ORI_SR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	166 decoded->extra.size = OPSIZE_WORD;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	167 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	168 decoded->src.params.immed = *(++istream);
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	169 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	170 decoded->op = M68K_OR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	171 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	172 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	173 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	174 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	175 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	176 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	177 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	178 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	179 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	180 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	181 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	182 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	183 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	184 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	185 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	186 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	187 break;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	188 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	189 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	190 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	191 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	192 case 1:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	193 //ANDI, ANDI to CCR, ANDI to SR
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	194 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	195 decoded->op = M68K_ANDI_CCR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	196 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	197 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	198 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	199 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	200 decoded->op = M68K_ANDI_SR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	201 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	202 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	203 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	204 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	205 decoded->op = M68K_AND;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	206 decoded->variant = VAR_IMMEDIATE;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	207 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	208 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	209 reg = *istream & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	210 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	211 switch (size)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	212 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	213 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	214 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	215 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	216 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	217 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	218 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	219 case OPSIZE_LONG:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	220 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	221 decoded->src.params.immed = immed << 16 \| *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	222 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	223 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	224 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	225 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	226 break;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	227 case 2:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	228 decoded->op = M68K_SUB;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	229 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	230 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	231 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	232 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	233 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	234 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	235 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	236 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	237 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	238 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	239 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	240 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	241 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	242 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	243 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	244 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	245 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	246 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	247 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	248 break;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	249 case 3:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	250 decoded->op = M68K_ADD;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	251 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	252 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	253 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	254 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	255 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	256 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	257 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	258 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	259 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	260 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	261 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	262 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	263 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	264 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	265 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	266 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	267 break;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	268 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	269 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	270 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	271 case 4:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	272 //BTST, BCHG, BCLR, BSET
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	273 switch ((*istream >> 6) & 0x3)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	274 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	275 case 0:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	276 decoded->op = M68K_BTST;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	277 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	278 case 1:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	279 decoded->op = M68K_BCHG;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	280 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	281 case 2:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	282 decoded->op = M68K_BCLR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	283 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	284 case 3:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	285 decoded->op = M68K_BSET;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	286 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	287 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	288 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	289 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	290 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	291 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	292 case 5:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	293 //EORI, EORI to CCR, EORI to SR
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	294 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	295 decoded->op = M68K_EORI_CCR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	296 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	297 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	298 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	299 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	300 decoded->op = M68K_EORI_SR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	301 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	302 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	303 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	304 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	305 decoded->op = M68K_EOR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	306 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	307 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	308 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	309 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	310 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	311 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	312 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	313 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	314 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	315 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	316 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	317 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	318 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	319 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	320 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	321 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	322 break;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	323 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	324 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	325 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	326 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	327 case 6:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	328 decoded->op = M68K_CMP;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	329 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	330 decoded->extra.size = (*istream >> 6) & 0x3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	331 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	332 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	333 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	334 switch (decoded->extra.size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	335 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	336 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	337 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	338 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	339 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	340 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	341 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	342 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	343 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	344 decoded->src.params.immed = (immed << 16) \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	345 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	346 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	347 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	348 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	349 case 7:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	350 //MOVEP
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	351 decoded->op = M68K_MOVEP;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	352 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	353 if (*istream & 0x80) {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	354 //memory dest
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	355 decoded->src.addr_mode = MODE_REG;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	356 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	357 decoded->dst.addr_mode = MODE_AREG_DISPLACE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	358 decoded->dst.params.regs.pri = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	359 } else {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	360 //memory source
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	361 decoded->dst.addr_mode = MODE_REG;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	362 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	363 decoded->src.addr_mode = MODE_AREG_DISPLACE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	364 decoded->src.params.regs.pri = *istream & 0x7;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	365 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	366 immed = *(++istream);
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	367
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	368 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	369 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	370 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 case MOVE_BYTE:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	373 case MOVE_LONG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 case MOVE_WORD:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	375 decoded->op = M68K_MOVE;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	377 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	378 istream = m68k_decode_op_ex(istream, (istream >> 6) & 0x7, m68K_reg_quick_field(istream), decoded->extra.size, &(decoded->dst));
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	379 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	380 case MISC:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	381
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	382 if ((*istream & 0x1C0) == 0x1C0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	383 decoded->op = M68K_LEA;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	384 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	385 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	386 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	387 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	388 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	389 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	390 decoded->op = M68K_CHK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	391 if ((*istream & 0x180) == 0x180) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	392 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	393 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	394 //only on M68020+
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	395 #ifdef M68020
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	396 decoded->extra.size = OPSIZE_LONG;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	397 #else
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	398 decoded->op = M68K_INVALID;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	399 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	400 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	401 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	402 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	403 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	404 decoded->dst.addr_mode = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	405 } else {
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	406 opmode = (*istream >> 3) & 0x7;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	407 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG && opmode != MODE_AREG_POSTINC) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	408 decoded->op = M68K_MOVEM;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	409 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	410 reg = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	411 immed = *(++istream);
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	412 if(*istream & 0x400) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	413 decoded->dst.addr_mode = MODE_REG;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	414 decoded->dst.params.immed = immed;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	415 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src));
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	416 } else {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	417 decoded->src.addr_mode = MODE_REG;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	418 decoded->src.params.immed = immed;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	419 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	420 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	421 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	422 optype = (*istream >> 9) & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	423 size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	424 switch(optype)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	425 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	426 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	427 //Move from SR or NEGX
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	428 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	429 decoded->op = M68K_MOVE_FROM_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	430 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	431 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	432 decoded->op = M68K_NEGX;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	433 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	434 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	435 istream= m68k_decode_op(istream, size, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	436 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	437 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	438 //MOVE from CCR or CLR
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	439 if (size == OPSIZE_INVALID) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	440 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	441 decoded->op = M68K_MOVE_FROM_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	442 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	443 #else
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	444 return istream+1;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	445 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	446 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	447 decoded->op = M68K_CLR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	448 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	449 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	450 istream= m68k_decode_op(istream, size, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	451 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	452 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	453 //MOVE to CCR or NEG
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	454 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	455 decoded->op = M68K_MOVE_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	456 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	457 istream= m68k_decode_op(istream, size, &(decoded->src));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	458 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	459 decoded->op = M68K_NEG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	460 istream= m68k_decode_op(istream, size, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	461 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	462 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	463 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	464 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	465 //MOVE to SR or NOT
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	466 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	467 decoded->op = M68K_MOVE_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	468 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	469 istream= m68k_decode_op(istream, size, &(decoded->src));
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	470 } else {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	471 decoded->op = M68K_NOT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	472 istream= m68k_decode_op(istream, size, &(decoded->dst));
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	473 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	474 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	475 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	476 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	477 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	478 switch((*istream >> 3) & 0x3F)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	479 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	480 case 1:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	481 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	482 decoded->op = M68K_LINK;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	483 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	484 reg = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	485 immed = *(++istream) << 16;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	486 immed \|= *(++istream);
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	487 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	488 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	489 case 8:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	490 decoded->op = M68K_SWAP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	491 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	492 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	493 decoded->extra.size = OPSIZE_WORD;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	494 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	495 case 9:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	496 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	497 decoded->op = M68K_BKPT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	498 decoded->src.addr_mode = MODE_IMMEDIATE;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	499 decoded->extra.size = OPSIZE_UNSIZED;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	500 decoded->src.params.immed = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	501 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	502 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	503 case 0x10:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	504 decoded->op = M68K_EXT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	505 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	506 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	507 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	508 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	509 case 0x18:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	510 decoded->op = M68K_EXT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	511 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	512 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	513 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	514 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	515 case 0x38:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	516 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	517 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	518 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	519 default:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	520 if (!(*istream & 0x1C0)) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	521 decoded->op = M68K_NBCD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	522 decoded->extra.size = OPSIZE_BYTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	523 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	524 } else if((*istream & 0x1C0) == 0x40) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	525 decoded->op = M68K_PEA;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	526 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	527 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	528 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	529 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	530 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	531 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	532 //BGND, ILLEGAL, TAS, TST
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	533 optype = *istream & 0xFF;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	534 if (optype == 0xFA) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	535 //BGND - CPU32 only
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	536 } else if (optype == 0xFC) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	537 decoded->op = M68K_ILLEGAL;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	538 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	539 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	540 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	541 decoded->op = M68K_TAS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	542 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	543 decoded->op = M68K_TST;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	544 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	545 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	546 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	547 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	548 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	549 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	550 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	551 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	552 //TODO: Implement these for 68020+ support
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	553 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	554 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	555 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	556 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	557 if (*istream & 0x80) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	558 //JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	559 if (*istream & 0x40) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	560 decoded->op = M68K_JMP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	561 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	562 decoded->op = M68K_JSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	563 }
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	564 decoded->extra.size = OPSIZE_UNSIZED;
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	565 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src));
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	566 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	567 //it would appear bit 6 needs to be set for it to be a valid instruction here
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	568 switch((*istream >> 3) & 0x7)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	569 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	570 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	571 case 1:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	572 //TRAP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	573 decoded->op = M68K_TRAP;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	574 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	575 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	576 decoded->src.params.immed = *istream & 0xF;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	577 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	578 case 2:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	579 //LINK.w
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	580 decoded->op = M68K_LINK;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	581 decoded->extra.size = OPSIZE_WORD;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	582 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	583 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	584 decoded->dst.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	585 decoded->dst.params.immed = *(++istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	586 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	587 case 3:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	588 //UNLK
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	589 decoded->op = M68K_UNLK;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	590 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	591 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	592 decoded->dst.params.regs.pri = *istream & 0x7;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	593 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	594 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	595 case 5:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	596 //MOVE USP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	597 decoded->op = M68K_MOVE_USP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	598 if (*istream & 0x8) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	599 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	600 decoded->dst.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	601 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	602 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	603 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	604 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	605 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	606 case 6:
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	607 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	608 switch(*istream & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	609 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	610 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	611 decoded->op = M68K_RESET;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	612 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	613 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	614 decoded->op = M68K_NOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	615 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	616 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	617 decoded->op = M68K_STOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	618 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	619 decoded->src.params.immed =*(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	620 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	621 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	622 decoded->op = M68K_RTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	623 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	624 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	625 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	626 decoded->op = M68K_RTD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	627 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	628 decoded->src.params.immed =*(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	629 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	630 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	631 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	632 decoded->op = M68K_RTS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	633 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	634 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	635 decoded->op = M68K_TRAPV;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	636 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	637 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	638 decoded->op = M68K_RTR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	639 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	640 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	641 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	642 case 7:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	643 //MOVEC
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	644 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	645 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	646 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	647 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	648 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	649 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	650 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	651 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	652 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	653 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	654 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	655 case QUICK_ARITH_LOOP:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	656 size = (*istream >> 6) & 3;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	657 if (size == 0x3) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	658 //DBcc, TRAPcc or Scc
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	659 m68k_decode_cond(*istream, decoded);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	660 switch ((*istream >> 3) & 0x7)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	661 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	662 case 1: //DBcc
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	663 decoded->op = M68K_DBCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	664 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	665 decoded->src.params.immed = *(++istream);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	666 decoded->dst.addr_mode = MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	667 decoded->dst.params.regs.pri = *istream & 0x7;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	668 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	669 case 7: //TRAPcc
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	670 #ifdef M68020
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	671 decoded->op = M68K_TRAPCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	672 decoded->src.addr_mode = MODE_IMMEDIATE;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	673 //TODO: Figure out what to do with OPMODE and optional extention words
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	674 #endif
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	675 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	676 default: //Scc
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	677 decoded->op = M68K_SCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	678 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	679 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	680 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	681 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	682 //ADDQ, SUBQ
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	683 decoded->variant = VAR_QUICK;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	684 decoded->extra.size = size;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	685 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	686 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	687 immed = m68K_reg_quick_field(*istream);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	688 if (!immed) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	689 immed = 8;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	690 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	691 decoded->src.params.immed = immed;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	692 if (*istream & 0x100) {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	693 decoded->op = M68K_SUB;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	694 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	695 decoded->op = M68K_ADD;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	696 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	697 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	698 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	699 case BRANCH:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	700 m68k_decode_cond(*istream, decoded);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	701 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	702 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	703 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	704 if (immed == 0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	705 decoded->variant = VAR_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	706 immed = *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	707 immed = sign_extend16(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	708 } else if (immed == 0xFF) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	709 decoded->variant = VAR_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	710 immed = *(++istream) << 16;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	711 immed \|= *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	712 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	713 decoded->variant = VAR_BYTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	714 immed = sign_extend8(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	715 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	716 decoded->src.params.immed = immed;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	717 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	718 case MOVEQ:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	719 decoded->op = M68K_MOVE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	720 decoded->variant = VAR_QUICK;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	721 decoded->extra.size = OPSIZE_LONG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	722 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	723 decoded->src.params.immed = sign_extend8(*istream & 0xFF);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	724 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	725 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	726 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	727 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	728 case OR_DIV_SBCD:
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	729 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea>
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	730 opmode = (*istream >> 6) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	731 size = opmode & 0x3;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	732 if (size == OPSIZE_INVALID \|\| (opmode & 0x4 && !(*istream & 0x30))) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	733 switch(opmode)
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	734 {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	735 case 3:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	736 decoded->op = M68K_DIVU;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	737 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	738 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	739 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	740 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	741 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	742 case 4:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	743 decoded->op = M68K_SBCD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	744 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	745 decoded->src.params.regs.pri = *istream & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	746 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	747 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	748 case 5:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	749 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	750 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	751 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	752 case 6:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	753 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	754 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	755 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	756 case 7:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	757 decoded->op = M68K_DIVS;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	758 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	759 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	760 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	761 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	762 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	763 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	764 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	765 decoded->op = M68K_OR;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	766 decoded->extra.size = size;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	767 if (opmode & 0x4) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	768 decoded->src.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	769 decoded->src.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	770 istream = m68k_decode_op(istream, size, &(decoded->dst));
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	771 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	772 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	773 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	774 istream = m68k_decode_op(istream, size, &(decoded->src));
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	775 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	776 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	777 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	778 case SUB_SUBX:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	779 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	780 decoded->op = M68K_SUB;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	781 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	782 //<ea> destination, SUBA.l or SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	783 if (*istream & 0x6) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	784 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	785 //SUBA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	786 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	787 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	788 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	789 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	790 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	791 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	792 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	793 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	794 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	795 //SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	796 decoded->op = M68K_SUBX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	797 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	798 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	799 decoded->dst.addr_mode = decoded->src.addr_mode;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	800 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	801 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	802 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	803 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	804 //SUBA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	805 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	806 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	807 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	808 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	809 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	810 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	811 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	812 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	813 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	814 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	815 case RESERVED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	816 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	817 case CMP_XOR:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	818 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	819 decoded->op = M68K_CMP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	820 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	821 //CMPM or EOR
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	822 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	823 if (decoded->src.addr_mode == MODE_AREG) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	824 //CMPM
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	825 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	826 decoded->src.params.regs.pri = decoded->dst.params.regs.pri;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	827 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	828 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	829 //EOR
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	830 decoded->op = M68K_EOR;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	831 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	832 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	833 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	834 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	835 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	836 //CMP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	837 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	838 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	839 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	840 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	841 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	842 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	843 case AND_MUL_ABCD_EXG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	844 //page 575 for summary
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	845 //EXG opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	846 //01000 -data regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	847 //01001 -addr regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	848 //10001 -one of each
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	849 //AND opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	850 //operand order bit + 2 size bits (00 - 10)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	851 //no address register direct addressing
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	852 //data register direct not allowed when <ea> is the source (operand order bit of 1)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	853 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	854 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	855 decoded->op = M68K_MULS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	856 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	857 decoded->dst.addr_mode = MODE_REG;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	858 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	859 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	860 } else if(!(*istream & 0xF0)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	861 decoded->op = M68K_ABCD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	862 decoded->extra.size = OPSIZE_BYTE;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	863 decoded->src.params.regs.pri = *istream & 0x7;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	864 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	865 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	866 } else if(!(*istream & 0x30)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	867 decoded->op = M68K_EXG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	868 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	869 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	870 decoded->dst.params.regs.pri = *istream & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	871 if (*istream & 0x8) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	872 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	873 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	874 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	875 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	876 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	877 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	878 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	879 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	880 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	881 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	882 decoded->op = M68K_AND;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	883 decoded->extra.size = (*istream >> 6);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	884 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	885 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	886 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	887 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	888 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	889 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	890 decoded->op = M68K_MULU;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	891 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	892 decoded->dst.addr_mode = MODE_REG;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	893 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	894 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	895 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	896 decoded->op = M68K_AND;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	897 decoded->extra.size = (*istream >> 6);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	898 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	899 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	900 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	901 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	902 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	903 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	904 case ADD_ADDX:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	905 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	906 decoded->op = M68K_ADD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	907 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	908 //<ea> destination, ADDA.l or ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	909 if (*istream & 0x6) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	910 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	911 //ADDA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	912 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	913 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	914 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	915 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	916 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	917 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	918 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	919 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	920 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	921 //ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	922 decoded->op = M68K_ADDX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	923 //FIXME: Size is not technically correct
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	924 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	925 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	926 decoded->dst.addr_mode = decoded->src.addr_mode;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	927 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	928 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	929 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	930 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	931 //ADDA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	932 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	933 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	934 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	935 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	936 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	937 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	938 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	939 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	940 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	941 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	942 case SHIFT_ROTATE:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	943 if ((*istream & 0x8C0) == 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	944 switch((*istream >> 8) & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	945 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	946 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	947 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	948 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	949 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	950 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	951 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	952 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	953 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	954 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	955 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	956 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	957 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	958 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	959 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	960 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	961 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	962 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	963 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	964 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	965 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	966 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	967 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	968 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	969 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	970 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	971 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	972 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst));
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	973 } else if((*istream & 0xC0) != 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	974 switch(((istream >> 2) & 0x6) \| ((istream >> 8) & 1))
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	975 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	976 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	977 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	978 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	979 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	980 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	981 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	982 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	983 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	984 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	985 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	986 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	987 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	988 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	989 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	990 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	991 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	992 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	993 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	994 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	995 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	996 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	997 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	998 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	999 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1000 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1001 decoded->extra.size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1002 immed = (*istream >> 9) & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1003 if (*istream & 0x100) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1004 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1005 decoded->src.params.immed = immed;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1006 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1007 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1008 decoded->src.params.regs.pri = immed;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1009 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1010 decoded->dst.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1011 decoded->dst.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1012
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1013 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1014 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1015 //TODO: Implement bitfield instructions for M68020+ support
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1016 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1017 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1018 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1019 case COPROC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1020 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1021 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1022 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1023 return istream+1;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1024 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1025
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1026 char * mnemonics[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1027 "abcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1028 "add",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1029 "addx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1030 "and",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1031 "andi",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1032 "andi",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1033 "asl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1034 "asr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1035 "bcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1036 "bchg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1037 "bclr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1038 "bset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1039 "bsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1040 "btst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1041 "chk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1042 "clr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1043 "cmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1044 "dbcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1045 "divs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1046 "divu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1047 "eor",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1048 "eori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1049 "eori",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1050 "exg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1051 "ext",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1052 "illegal",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1053 "jmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1054 "jsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1055 "lea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1056 "link",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1057 "lsl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1058 "lsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1059 "move",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1060 "move",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1061 "move",//from_sr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1062 "move",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1063 "move_usp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1064 "movem",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1065 "movep",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1066 "muls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1067 "mulu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1068 "nbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1069 "neg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1070 "negx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1071 "nop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1072 "not",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1073 "or",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1074 "ori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1075 "ori",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1076 "pea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1077 "reset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1078 "rol",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1079 "ror",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1080 "roxl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1081 "roxr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1082 "rte",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1083 "rtr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1084 "rts",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1085 "sbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1086 "scc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1087 "stop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1088 "sub",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1089 "subx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1090 "swap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1091 "tas",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1092 "trap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1093 "trapv",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1094 "tst",
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	1095 "unlk",
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1096 "invalid"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1097 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1098
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1099 char * cond_mnem[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1100 "ra",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1101 "f",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1102 "hi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1103 "ls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1104 "cc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1105 "cs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1106 "ne",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1107 "eq",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1108 "vc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1109 "vs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1110 "pl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1111 "mi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1112 "ge",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1113 "lt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1114 "gt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1115 "le"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1116 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1117
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1118 int m68k_disasm_op(m68k_op_info decoded, char dst, int need_comma)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1119 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1120 char * c = need_comma ? "," : "";
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1121 switch(decoded->addr_mode)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1122 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1123 case MODE_REG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1124 return sprintf(dst, "%s d%d", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1125 case MODE_AREG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1126 return sprintf(dst, "%s a%d", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1127 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1128 return sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1129 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1130 return sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1131 case MODE_AREG_PREDEC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1132 return sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1133 case MODE_AREG_DISPLACE:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1134 return sprintf(dst, "%s (a%d, %d)", c, decoded->params.regs.pri, decoded->params.regs.displacement);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1135 case MODE_IMMEDIATE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1136 return sprintf(dst, "%s #%d", c, decoded->params.immed);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1137 case MODE_ABSOLUTE_SHORT:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1138 return sprintf(dst, "%s $%X.w", c, decoded->params.immed);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1139 case MODE_ABSOLUTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1140 return sprintf(dst, "%s $%X", c, decoded->params.immed);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1141 case MODE_PC_DISPLACE:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1142 return sprintf(dst, "%s (pc, %d)", c, decoded->params.regs.displacement);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1143 default:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1144 return 0;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1145 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1146 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1147
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1148 int m68k_disasm_movem_op(m68k_op_info decoded, m68k_op_info other, char *dst, int need_comma)
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1149 {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1150 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1151 char rtype, last_rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1152 int oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1153 if (decoded->addr_mode == MODE_REG) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1154 if (other->addr_mode == MODE_AREG_PREDEC) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1155 bit = 15;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1156 dir = -1;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1157 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1158 reg = 0;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1159 bit = 1;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1160 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1161 strcat(dst, " ");
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1162 for (oplen = 1, reg=0; bit < 16 && bit > -1; bit += dir, reg++) {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1163 if (decoded->params.immed & (1 << bit)) {
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1164 if (reg > 7) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1165 rtype = "a";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1166 regnum = reg - 8;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1167 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1168 rtype = "d";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1169 regnum = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1170 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1171 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1172 last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1173 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1174 } else if(last >= 0) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1175 if (first != last) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1176 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1177 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1178 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1179 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1180 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1181 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1182 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1183 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1184 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1185 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1186 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1187 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1188 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1189 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1190 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1191 if (last >= 0 && last != first) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1192 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1193 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1194 return oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1195 } else {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1196 return m68k_disasm_op(decoded, dst, need_comma);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1197 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1198 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1199
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1200 int m68k_disasm(m68kinst * decoded, char * dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1201 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1202 int ret,op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1203 uint8_t size;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1204 char * special_op = "CCR";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1205 switch (decoded->op)
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1206 {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1207 case M68K_BCC:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1208 case M68K_DBCC:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1209 case M68K_SCC:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1210 ret = strlen(mnemonics[decoded->op]) - 2;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1211 memcpy(dst, mnemonics[decoded->op], ret);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1212 dst[ret] = 0;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1213 strcat(dst, cond_mnem[decoded->extra.cond]);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1214 ret = strlen(dst);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1215 break;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1216 case M68K_BSR:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1217 ret = sprintf(dst, "bsr%s", decoded->variant == VAR_BYTE ? ".s" : "");
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1218 break;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1219 case M68K_MOVE_FROM_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1220 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1221 ret += sprintf(dst + ret, " SR");
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1222 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1223 return ret;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1224 case M68K_ANDI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1225 case M68K_EORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1226 case M68K_MOVE_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1227 case M68K_ORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1228 special_op = "SR";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1229 case M68K_ANDI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1230 case M68K_EORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1231 case M68K_MOVE_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1232 case M68K_ORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1233 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1234 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1235 ret += sprintf(dst + ret, ", %s", special_op);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1236 return ret;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1237 default:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1238 size = decoded->extra.size;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1239 ret = sprintf(dst, "%s%s%s",
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1240 mnemonics[decoded->op],
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	1241 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""),
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1242 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : "")));
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1243 }
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1244 if (decoded->op == M68K_MOVEM) {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1245 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1246 ret += op1len;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1247 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1248 } else {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1249 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1250 ret += op1len;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1251 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1252 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1253 return ret;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1254 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1255

Mercurial > repos > blastem

annotate 68kinst.c @ 15:c0f339564819