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YM2612 WIP snapshot before register refactor
author Mike Pavone <pavone@retrodev.com>
date Mon, 27 May 2013 09:54:58 -0700
parents a8ee7934a1f8
children b7c3facee762
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1 #include <string.h>
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2 #include <math.h>
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3 #include <stdio.h>
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4 #include "ym2612.h"
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5
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6 #define BUSY_CYCLES 17
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7 #define TIMERA_UPDATE_PERIOD 144
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8
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9 #define REG_TIMERA_HIGH 0x03 // 0x24
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10 #define REG_TIMERA_LOW 0x04 // 0x25
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11 #define REG_TIMERB 0x05 // 0x26
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12 #define REG_TIME_CTRL 0x06 // 0x27
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13 #define REG_DAC 0x0A // 0x2A
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14 #define REG_DAC_ENABLE 0x0B // 0x2B
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15
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16 //offset to add to "shared" regs when looking for them in Part I
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17 #define REG_SHARED 0x10
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19
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20 #define REG_ALG_FEEDBACK (0xB0-0x30)
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21 #define REG_ATTACK_KS (0x50-0x30)
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22 #define REG_DECAY_AM (0x60-0x30)
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23 #define REG_SUSTAIN_RATE (0x70-0x30)
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24
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26 #define BIT_TIMERA_ENABLE 0x1
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27 #define BIT_TIMERB_ENABLE 0x2
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28 #define BIT_TIMERA_OVEREN 0x4
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29 #define BIT_TIMERB_OVEREN 0x8
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30 #define BIT_TIMERA_RESET 0x10
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31 #define BIT_TIMERB_RESET 0x20
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32
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33 #define BIT_STATUS_TIMERA 0x1
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34 #define BIT_STATUS_TIMERB 0x2
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35
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36 enum {
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37 PHASE_ATTACK,
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38 PHASE_DECAY,
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39 PHASE_SUSTAIN,
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40 PHASE_RELEASE
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41 };
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42
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43 uint8_t did_tbl_init = 0;
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44 //According to Nemesis, real hardware only uses a 256 entry quarter sine table; however,
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45 //memory is cheap so using a half sine table will probably save some cycles
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46 //a full sine table would be nice, but negative numbers don't get along with log2
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47 #define SINE_TABLE_SIZE 512
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48 uint16_t sine_table[SINE_TABLE_SIZE];
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49 //Similar deal here with the power table for log -> linear conversion
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50 //According to Nemesis, real hardware only uses a 256 entry table for the fractional part
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51 //and uses the whole part as a shift amount.
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52 #define POW_TABLE_SIZE (1 << 13)
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53 uint16_t pow_table[POW_TABLE_SIZE];
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54
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55
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56 uint16_t round_fixed_point(double value, int dec_bits)
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57 {
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58 return value * (1 << dec_bits) + 0.5;
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59 }
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60
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61 void ym_init(ym2612_context * context)
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62 {
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63 memset(context, 0, sizeof(*context));
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64 if (!did_tbl_init) {
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65 //populate sine table
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66 for (int32_t i = 0; i < 512; i++) {
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67 double sine = sin( ((double)(i*2+1) / SINE_TABLE_SIZE) * M_PI_2 );
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68
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69 //table stores 4.8 fixed pointed representation of the base 2 log
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70 sine_table[i] = round_fixed_point(-log2(sine), 8);
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71 }
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72 //populate power table
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73 for (int32_t i = 0; i < POW_TABLE_SIZE; i++) {
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74 double linear = pow(2, -((double)((i & 0xFF)+1) / 256.0));
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75 int32_t tmp = round_fixed_point(linear, 11);
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76 int32_t shift = (i >> 8) - 2;
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77 if (shift < 0) {
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78 tmp <<= 0-shift;
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79 } else {
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80 tmp >>= shift;
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81 }
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82 pow_table[i] = tmp;
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83 }
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84 }
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85 }
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86
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87 void ym_run(ym2612_context * context, uint32_t to_cycle)
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88 {
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89 for (; context->current_cycle < to_cycle; context->current_cycle += 6) {
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90 uint32_t update_cyc = context->current_cycle % 144;
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91 //Update timers at beginning of 144 cycle period
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92 if (!update_cyc && context->part1_regs[REG_TIME_CTRL] & BIT_TIMERA_ENABLE) {
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93 if (context->timer_a) {
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94 context->timer_a--;
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95 } else {
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96 if (context->part1_regs[REG_TIME_CTRL] & BIT_TIMERA_OVEREN) {
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97 context->status |= BIT_STATUS_TIMERA;
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98 }
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99 context->timer_a = (context->part1_regs[REG_TIMERA_HIGH] << 2) | (context->part1_regs[REG_TIMERA_LOW] & 0x3);
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100 }
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101 if (context->part1_regs[REG_TIME_CTRL] & BIT_TIMERB_ENABLE) {
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102 uint32_t b_cyc = (context->current_cycle / 144) % 16;
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103 if (!b_cyc) {
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104 if (context->timer_b) {
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105 context->timer_b--;
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106 } else {
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107 if (context->part1_regs[REG_TIME_CTRL] & BIT_TIMERB_OVEREN) {
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108 context->status |= BIT_STATUS_TIMERB;
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109 }
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110 context->timer_b = context->part1_regs[REG_TIMERB];
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111 }
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112 }
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113 }
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114 }
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115 //Update Envelope Generator
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116 if (update_cyc == 0 || update_cyc == 72) {
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117 uint32_t env_cyc = context->current_cycle / 72;
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118 uint32_t op = env_cyc % 24;
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119 env_cyc /= 24;
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120 uint8_t rate;
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121 switch(context->env_phase[op])
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122 {
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123 case PHASE_ATTACK:
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124 rate = (op < 3 ? context->part1_regs[REG_SHARED + REG_ATTACK_KS + op] : context->part2_regs[REG_ATTACK_KS + op - 3]) & 0x1F;
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125 break;
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126 case PHASE_DECAY:
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127 rate = (op < 3 ? context->part1_regs[REG_SHARED + REG_DECAY_AM + op] : context->part2_regs[REG_DECAY_AM + op - 3]) & 0x1F;
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128 break;
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129 case PHASE_SUSTAIN:
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130 rate = (op < 3 ? context->part1_regs[REG_SHARED + REG_SUSTAIN_RATE + op] : context->part2_regs[REG_SUSTAIN_RATE + op - 3]) & 0x1F;
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131 break;
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132 case PHASE_RELEASE:
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133 rate = (op < 3 ? context->part1_regs[REG_SHARED + REG_DECAY_AM + op] : context->part2_regs[REG_DECAY_AM + op - 3]) << 1 & 0x1E | 1;
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134 break;
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135 }
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136 if (rate) {
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137 //apply key scaling
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138 uint8_t shift = (op < 3 ?
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139 context->part1_regs[REG_SHARED + REG_ATTACK_KS + op] :
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140 context->part2_regs[REG_ATTACK_KS + op - 3]
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141 ) >> 6;
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142 uint8_t ks = context->keycode[op] >> (3 - shift);
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143 rate = rate*2 + ks;
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144 if (rate > 63) {
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145 rate = 63;
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146 }
288
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147 }
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148 }
359
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149 //Update Phase Generator
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150 uint32_t channel = update_cyc / 24;
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151 if (channel != 6 || !(context->part1_regs[REG_DAC_ENABLE] & 0x80)) {
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152 uint32_t op = (update_cyc) / 6;
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153 uint8_t alg;
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154 if (op < 3) {
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155 alg = context->part1_regs[REG_SHARED + REG_ALG_FEEDBACK + op] & 0x7;
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156 } else {
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157 alg = context->part2_regs[REG_ALG_FEEDBACK + op-3] & 0x7;
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158 }
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159 context->phase_counter[op] += context->phase_inc[op];
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160 uint16_t phase = context->phase_counter[op] >> 10 & 0x3FF;
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161 //TODO: Modulate phase if necessary
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162 uint16_t output = pow_table[sine_table[phase & 0x1FF] + context->envelope[op]];
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163 if (phase & 0x200) {
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164 output = -output;
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165 }
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166 context->op_out[op] = output;
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167 //Update the channel output if we've updated all operators
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168 if (op % 4 == 3) {
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169 if (alg < 4) {
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170 context->channel_out[channel] = context->op_out[channel * 4 + 3];
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171 } else if(alg == 4) {
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172 context->channel_out[channel] = context->op_out[channel * 4 + 3] + context->op_out[channel * 4 + 1];
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173 } else {
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174 output = 0;
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175 for (uint32_t op = ((alg == 7) ? 0 : 1) + channel*4; op < (channel+1)*4; op++) {
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176 output += context->op_out[op];
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177 }
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178 context->channel_out[channel] = output;
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179 }
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180 }
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181 }
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182
288
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183 }
359
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184 if (context->current_cycle >= context->write_cycle + BUSY_CYCLES) {
288
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185 context->status &= 0x7F;
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186 }
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187 }
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188
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189 void ym_address_write_part1(ym2612_context * context, uint8_t address)
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190 {
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191 if (address >= 0x21 && address < 0xB7) {
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192 context->selected_reg = context->part1_regs + address - 0x21;
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193 } else {
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194 context->selected_reg = NULL;
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195 }
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196 }
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197
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198 void ym_address_write_part2(ym2612_context * context, uint8_t address)
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199 {
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200 if (address >= 0x30 && address < 0xB7) {
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201 context->selected_reg = context->part1_regs + address - 0x30;
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202 } else {
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203 context->selected_reg = NULL;
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204 }
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205 }
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206
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207 void ym_data_write(ym2612_context * context, uint8_t value)
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208 {
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209 if (context->selected_reg && !(context->status & 0x80)) {
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210 *context->selected_reg = value;
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211 context->write_cycle = context->current_cycle;
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212 context->selected_reg = NULL;//TODO: Verify this
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213 }
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214 }
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215
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216 uint8_t ym_read_status(ym2612_context * context)
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217 {
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218 return context->status;
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219 }
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220