Mercurial > repos > blastem
annotate vdp.c @ 317:e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Fri, 10 May 2013 22:57:56 -0700 |
| parents | eea3b118940d |
| children | 789f2f5f2277 |
| rev | line source |
|---|---|
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1 #include "vdp.h" |
| 75 | 2 #include "blastem.h" |
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3 #include <stdlib.h> |
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4 #include <string.h> |
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5 |
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6 #define NTSC_ACTIVE 225 |
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7 #define PAL_ACTIVE 241 |
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8 #define BUF_BIT_PRIORITY 0x40 |
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9 #define MAP_BIT_PRIORITY 0x8000 |
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10 #define MAP_BIT_H_FLIP 0x800 |
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11 #define MAP_BIT_V_FLIP 0x1000 |
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12 |
| 75 | 13 #define BIT_PAL 0x8 |
| 14 #define BIT_DMA_ENABLE 0x4 | |
| 15 #define BIT_H40 0x1 | |
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16 |
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17 #define BIT_HILIGHT 0x8 |
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18 |
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19 #define SCROLL_BUFFER_SIZE 32 |
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20 #define SCROLL_BUFFER_DRAW 16 |
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21 |
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22 #define FIFO_SIZE 4 |
| 40 | 23 |
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24 void init_vdp_context(vdp_context * context) |
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25 { |
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26 memset(context, 0, sizeof(*context)); |
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27 context->vdpmem = malloc(VRAM_SIZE); |
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28 memset(context->vdpmem, 0, VRAM_SIZE); |
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29 context->framebuf = malloc(FRAMEBUF_SIZE); |
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30 memset(context->framebuf, 0, FRAMEBUF_SIZE); |
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31 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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32 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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33 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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34 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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35 context->sprite_draws = MAX_DRAWS; |
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36 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE); |
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37 context->fifo_end = context->fifo_cur + FIFO_SIZE; |
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38 } |
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39 |
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40 void render_sprite_cells(vdp_context * context) |
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41 { |
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42 if (context->cur_slot >= context->sprite_draws) { |
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43 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
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44 |
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45 uint16_t dir; |
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46 int16_t x; |
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47 if (d->h_flip) { |
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48 x = d->x_pos + 7; |
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49 dir = -1; |
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50 } else { |
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51 x = d->x_pos; |
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52 dir = 1; |
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53 } |
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54 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
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55 context->cur_slot--; |
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56 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
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57 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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58 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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59 } |
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60 x += dir; |
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61 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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62 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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63 } |
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64 x += dir; |
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65 } |
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66 } |
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67 } |
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68 |
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69 void scan_sprite_table(uint32_t line, vdp_context * context) |
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70 { |
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71 if (context->sprite_index && context->slot_counter) { |
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72 line += 1; |
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73 line &= 0xFF; |
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74 context->sprite_index &= 0x7F; |
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75 if (context->latched_mode & BIT_H40) { |
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76 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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77 context->sprite_index = 0; |
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78 return; |
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79 } |
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80 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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81 context->sprite_index = 0; |
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82 return; |
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83 } |
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84 //TODO: Read from SAT cache rather than from VRAM |
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85 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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86 uint16_t address = context->sprite_index * 8 + sat_address; |
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87 line += 128; |
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88 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]); |
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89 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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90 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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91 if (y <= line && line < (y + height)) { |
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92 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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93 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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94 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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95 context->sprite_info_list[context->slot_counter].y = y-128; |
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96 } |
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97 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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98 if (context->sprite_index && context->slot_counter) |
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99 { |
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100 address = context->sprite_index * 8 + sat_address; |
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101 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]); |
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102 height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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103 if (y <= line && line < (y + height)) { |
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104 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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105 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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106 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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107 context->sprite_info_list[context->slot_counter].y = y-128; |
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108 } |
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109 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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110 } |
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111 } |
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112 } |
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113 |
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114 void read_sprite_x(uint32_t line, vdp_context * context) |
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115 { |
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116 if (context->cur_slot >= context->slot_counter) { |
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117 if (context->sprite_draws) { |
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118 line += 1; |
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119 line &= 0xFF; |
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120 //in tiles |
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121 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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122 //in pixels |
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123 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
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124 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
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125 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
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126 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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127 uint8_t row; |
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128 if (tileinfo & MAP_BIT_V_FLIP) { |
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129 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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130 } else { |
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131 row = line-context->sprite_info_list[context->cur_slot].y; |
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132 } |
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133 uint16_t address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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134 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8) | context->vdpmem[att_addr + 3]; |
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135 if (x) { |
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136 context->flags |= FLAG_CAN_MASK; |
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137 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
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138 context->flags |= FLAG_MASKED; |
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139 } |
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140 |
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141 context->flags &= ~FLAG_DOT_OFLOW; |
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142 int16_t i; |
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143 if (context->flags & FLAG_MASKED) { |
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144 for (i=0; i < width && context->sprite_draws; i++) { |
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145 --context->sprite_draws; |
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146 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
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147 } |
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148 } else { |
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149 x -= 128; |
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150 int16_t base_x = x; |
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151 int16_t dir; |
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152 if (tileinfo & MAP_BIT_H_FLIP) { |
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153 x += (width-1) * 8; |
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154 dir = -8; |
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155 } else { |
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156 dir = 8; |
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157 } |
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158 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
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159 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
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160 --context->sprite_draws; |
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161 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
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162 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
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163 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
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164 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
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165 } |
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166 } |
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167 if (i < width) { |
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168 context->flags |= FLAG_DOT_OFLOW; |
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169 } |
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170 context->cur_slot--; |
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171 } else { |
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172 context->flags |= FLAG_DOT_OFLOW; |
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173 } |
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174 } |
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175 } |
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176 |
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177 #define VRAM_READ 0 |
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178 #define VRAM_WRITE 1 |
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179 #define CRAM_READ 8 |
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180 #define CRAM_WRITE 3 |
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181 #define VSRAM_READ 4 |
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182 #define VSRAM_WRITE 5 |
| 75 | 183 #define DMA_START 0x20 |
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184 |
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185 void external_slot(vdp_context * context) |
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186 { |
| 75 | 187 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
| 188 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
| 189 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
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190 if(context->flags & FLAG_DMA_RUN) { |
| 75 | 191 uint16_t dma_len; |
| 192 switch(context->regs[REG_DMASRC_H] & 0xC0) | |
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193 { |
| 75 | 194 //68K -> VDP |
| 195 case 0: | |
| 196 case 0x40: | |
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197 switch(context->dma_cd & 0xF) |
| 75 | 198 { |
| 199 case VRAM_WRITE: | |
| 200 if (context->flags & FLAG_DMA_PROG) { | |
| 201 context->vdpmem[context->address ^ 1] = context->dma_val; | |
| 202 context->flags &= ~FLAG_DMA_PROG; | |
| 203 } else { | |
| 204 context->dma_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 205 context->vdpmem[context->address] = context->dma_val >> 8; | |
| 206 context->flags |= FLAG_DMA_PROG; | |
| 207 } | |
| 208 break; | |
| 209 case CRAM_WRITE: | |
| 210 context->cram[(context->address/2) & (CRAM_SIZE-1)] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
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211 //printf("CRAM DMA | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->cycles); |
| 75 | 212 break; |
| 213 case VSRAM_WRITE: | |
| 214 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 215 context->vsram[(context->address/2) & 63] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 216 } | |
| 217 break; | |
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218 } |
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219 break; |
| 75 | 220 //Fill |
| 221 case 0x80: | |
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222 switch(context->dma_cd & 0xF) |
| 75 | 223 { |
| 224 case VRAM_WRITE: | |
| 225 //Charles MacDonald's VDP doc says that the low byte gets written first | |
| 142 | 226 context->vdpmem[context->address] = context->dma_val; |
| 227 context->dma_val = (context->dma_val << 8) | ((context->dma_val >> 8) & 0xFF); | |
| 75 | 228 break; |
| 229 case CRAM_WRITE: | |
| 230 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val; | |
| 231 break; | |
| 232 case VSRAM_WRITE: | |
| 233 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 234 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 235 } | |
| 236 break; | |
| 237 } | |
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238 break; |
| 75 | 239 //Copy |
| 240 case 0xC0: | |
| 241 if (context->flags & FLAG_DMA_PROG) { | |
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242 switch(context->dma_cd & 0xF) |
| 75 | 243 { |
| 244 case VRAM_WRITE: | |
| 245 context->vdpmem[context->address] = context->dma_val; | |
| 246 break; | |
| 247 case CRAM_WRITE: | |
| 248 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val; | |
| 249 break; | |
| 250 case VSRAM_WRITE: | |
| 251 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 252 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 253 } | |
| 254 break; | |
| 255 } | |
| 256 context->flags &= ~FLAG_DMA_PROG; | |
| 257 } else { | |
| 258 //I assume, that DMA copy copies from the same RAM as the destination | |
| 259 //but it's possible I'm mistaken | |
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260 switch(context->dma_cd & 0xF) |
| 75 | 261 { |
| 262 case VRAM_WRITE: | |
| 263 context->dma_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; | |
| 264 break; | |
| 265 case CRAM_WRITE: | |
| 266 context->dma_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; | |
| 267 break; | |
| 268 case VSRAM_WRITE: | |
| 269 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { | |
| 270 context->dma_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; | |
| 271 } else { | |
| 272 context->dma_val = 0; | |
| 273 } | |
| 274 break; | |
| 275 } | |
| 276 context->flags |= FLAG_DMA_PROG; | |
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277 } |
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278 break; |
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279 } |
| 75 | 280 if (!(context->flags & FLAG_DMA_PROG)) { |
| 281 context->address += context->regs[REG_AUTOINC]; | |
| 282 context->regs[REG_DMASRC_L] += 1; | |
| 135 | 283 if (!context->regs[REG_DMASRC_L]) { |
| 284 context->regs[REG_DMASRC_M] += 1; | |
| 285 } | |
| 75 | 286 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
| 287 context->regs[REG_DMALEN_H] = dma_len >> 8; | |
| 288 context->regs[REG_DMALEN_L] = dma_len; | |
| 289 if (!dma_len) { | |
| 290 context->flags &= ~FLAG_DMA_RUN; | |
| 291 } | |
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292 } |
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293 } else { |
| 75 | 294 fifo_entry * start = (context->fifo_end - FIFO_SIZE); |
| 295 if (context->fifo_cur != start && start->cycle <= context->cycles) { | |
| 296 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) { | |
| 297 context->flags |= FLAG_DMA_RUN; | |
| 298 context->dma_val = start->value; | |
| 138 | 299 context->address = start->address; //undo auto-increment |
|
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300 context->dma_cd = context->cd; |
| 75 | 301 } else { |
| 138 | 302 switch (start->cd & 0xF) |
| 75 | 303 { |
| 304 case VRAM_WRITE: | |
| 305 if (start->partial) { | |
| 306 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); | |
| 138 | 307 context->vdpmem[start->address ^ 1] = start->value; |
| 75 | 308 } else { |
| 309 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address); | |
| 138 | 310 context->vdpmem[start->address] = start->value >> 8; |
| 75 | 311 start->partial = 1; |
| 312 //skip auto-increment and removal of entry from fifo | |
| 313 return; | |
| 314 } | |
| 315 break; | |
| 316 case CRAM_WRITE: | |
|
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317 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
| 138 | 318 context->cram[(start->address/2) & (CRAM_SIZE-1)] = start->value; |
| 75 | 319 break; |
| 320 case VSRAM_WRITE: | |
| 138 | 321 if (((start->address/2) & 63) < VSRAM_SIZE) { |
| 75 | 322 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
| 138 | 323 context->vsram[(start->address/2) & 63] = start->value; |
| 75 | 324 } |
| 325 break; | |
| 326 } | |
| 138 | 327 //context->address += context->regs[REG_AUTOINC]; |
| 75 | 328 } |
| 329 fifo_entry * cur = start+1; | |
| 330 if (cur < context->fifo_cur) { | |
| 331 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur)); | |
| 332 } | |
| 333 context->fifo_cur -= 1; | |
| 334 } else { | |
| 335 context->flags |= FLAG_UNUSED_SLOT; | |
| 336 } | |
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337 } |
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338 } |
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339 |
| 40 | 340 #define WINDOW_RIGHT 0x80 |
| 341 #define WINDOW_DOWN 0x80 | |
| 342 | |
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343 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
|
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344 { |
| 40 | 345 if (!vsram_off) { |
| 346 uint16_t left_col, right_col; | |
| 347 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
|
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348 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
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349 right_col = 42; |
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350 } else { |
| 40 | 351 left_col = 0; |
| 352 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
| 353 if (right_col) { | |
| 354 right_col += 2; | |
| 355 } | |
| 356 } | |
|
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357 uint16_t top_line, bottom_line; |
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358 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
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359 top_line = (context->regs[REG_WINDOW_V] & 0x1F) * 8; |
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360 bottom_line = 241; |
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361 } else { |
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362 top_line = 0; |
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363 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) * 8; |
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364 } |
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365 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
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366 uint16_t address = context->regs[REG_WINDOW] << 10; |
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367 uint16_t line_offset, offset, mask; |
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368 if (context->latched_mode & BIT_H40) { |
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369 address &= 0xF000; |
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370 line_offset = (((line) / 8) * 64 * 2) & 0xFFF; |
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371 mask = 0x7F; |
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372 |
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373 } else { |
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374 address &= 0xF800; |
|
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375 line_offset = (((line) / 8) * 32 * 2) & 0xFFF; |
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376 mask = 0x3F; |
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377 } |
|
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378 offset = address + line_offset + (((column - 2) * 2) & mask); |
|
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379 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
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380 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
|
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381 offset = address + line_offset + (((column - 1) * 2) & mask); |
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382 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
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383 context->v_offset = (line) & 0x7; |
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384 context->flags |= FLAG_WINDOW; |
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385 return; |
| 40 | 386 } |
| 387 context->flags &= ~FLAG_WINDOW; | |
| 388 } | |
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389 uint16_t vscroll; |
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390 switch(context->regs[REG_SCROLL] & 0x30) |
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391 { |
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392 case 0: |
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393 vscroll = 0xFF; |
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394 break; |
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395 case 0x10: |
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396 vscroll = 0x1FF; |
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397 break; |
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398 case 0x20: |
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399 //TODO: Verify this behavior |
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400 vscroll = 0; |
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401 break; |
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402 case 0x30: |
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403 vscroll = 0x3FF; |
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404 break; |
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405 } |
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406 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & 0x4 ? column : 0) + vsram_off] + line); |
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407 context->v_offset = vscroll & 0x7; |
|
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408 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
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409 vscroll /= 8; |
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410 uint16_t hscroll_mask; |
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411 uint16_t v_mul; |
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412 switch(context->regs[REG_SCROLL] & 0x3) |
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413 { |
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414 case 0: |
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415 hscroll_mask = 0x1F; |
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416 v_mul = 64; |
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417 break; |
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418 case 0x1: |
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419 hscroll_mask = 0x3F; |
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420 v_mul = 128; |
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421 break; |
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422 case 0x2: |
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423 //TODO: Verify this behavior |
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424 hscroll_mask = 0; |
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425 v_mul = 0; |
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426 break; |
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427 case 0x3: |
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428 hscroll_mask = 0x7F; |
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429 v_mul = 256; |
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430 break; |
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431 } |
| 28 | 432 uint16_t hscroll, offset; |
| 433 for (int i = 0; i < 2; i++) { | |
|
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434 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
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435 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
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436 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
| 28 | 437 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
| 438 if (i) { | |
| 439 context->col_2 = col_val; | |
| 440 } else { | |
| 441 context->col_1 = col_val; | |
| 442 } | |
| 443 } | |
|
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444 } |
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445 |
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446 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
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447 { |
|
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448 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
|
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449 } |
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450 |
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451 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
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452 { |
|
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453 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
|
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454 } |
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455 |
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456 void render_map(uint16_t col, uint8_t * tmp_buf, vdp_context * context) |
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457 { |
|
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6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
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458 uint16_t address = ((col & 0x7FF) << 5); |
|
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459 if (col & MAP_BIT_V_FLIP) { |
|
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460 address += 28 - 4 * context->v_offset; |
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461 } else { |
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462 address += 4 * context->v_offset; |
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463 } |
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464 uint16_t pal_priority = (col >> 9) & 0x70; |
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465 int32_t dir; |
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466 if (col & MAP_BIT_H_FLIP) { |
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467 tmp_buf += 7; |
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468 dir = -1; |
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469 } else { |
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470 dir = 1; |
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471 } |
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472 for (uint32_t i=0; i < 4; i++, address++) |
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473 { |
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474 *tmp_buf = pal_priority | (context->vdpmem[address] >> 4); |
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475 tmp_buf += dir; |
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476 *tmp_buf = pal_priority | (context->vdpmem[address] & 0xF); |
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477 tmp_buf += dir; |
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478 } |
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479 } |
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480 |
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481 void render_map_1(vdp_context * context) |
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482 { |
|
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483 render_map(context->col_1, context->tmp_buf_a+SCROLL_BUFFER_DRAW, context); |
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484 } |
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485 |
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486 void render_map_2(vdp_context * context) |
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487 { |
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488 render_map(context->col_2, context->tmp_buf_a+SCROLL_BUFFER_DRAW+8, context); |
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489 } |
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490 |
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491 void render_map_3(vdp_context * context) |
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492 { |
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493 render_map(context->col_1, context->tmp_buf_b+SCROLL_BUFFER_DRAW, context); |
|
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494 } |
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495 |
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496 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
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497 { |
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498 if (line >= 240) { |
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499 return; |
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500 } |
|
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|
501 render_map(context->col_2, context->tmp_buf_b+SCROLL_BUFFER_DRAW+8, context); |
|
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502 uint16_t *dst, *end; |
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503 uint8_t *sprite_buf, *plane_a, *plane_b; |
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504 if (col) |
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|
505 { |
|
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|
506 col-=2; |
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507 dst = context->framebuf + line * 320 + col * 8; |
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|
508 sprite_buf = context->linebuf + col * 8; |
|
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|
509 uint16_t a_src; |
| 40 | 510 if (context->flags & FLAG_WINDOW) { |
| 511 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW; | |
|
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|
512 a_src = FBUF_SRC_W; |
| 40 | 513 } else { |
| 514 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW - (context->hscroll_a & 0xF); | |
|
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|
515 a_src = FBUF_SRC_A; |
| 40 | 516 } |
|
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38
diff
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|
517 plane_b = context->tmp_buf_b + SCROLL_BUFFER_DRAW - (context->hscroll_b & 0xF); |
| 30 | 518 end = dst + 16; |
|
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|
519 uint16_t src; |
| 30 | 520 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
|
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|
521 |
|
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522 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
|
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523 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) { |
|
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|
524 uint8_t pixel; |
|
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|
525 |
|
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|
526 src = 0; |
|
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|
527 uint8_t sprite_color = *sprite_buf & 0x3F; |
|
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|
528 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
|
232
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230
diff
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|
529 if (sprite_color == 0x3F) { |
|
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|
530 src = FBUF_SHADOW; |
|
230
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|
531 } else { |
|
232
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|
532 src = FBUF_HILIGHT; |
|
230
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191
diff
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|
533 } |
|
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191
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|
534 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
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191
diff
changeset
|
535 pixel = *plane_a; |
|
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diff
changeset
|
536 src |= a_src; |
|
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191
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|
537 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
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191
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|
538 pixel = *plane_b; |
|
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191
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changeset
|
539 src |= FBUF_SRC_B; |
|
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191
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|
540 } else if (*plane_a & 0xF) { |
|
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|
541 pixel = *plane_a; |
|
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diff
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|
542 src |= a_src; |
|
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|
543 } else if (*plane_b & 0xF){ |
|
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changeset
|
544 pixel = *plane_b; |
|
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191
diff
changeset
|
545 src |= FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
546 } else { |
|
d3266cee02c9
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191
diff
changeset
|
547 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
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191
diff
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|
548 src |= FBUF_SRC_BG; |
|
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191
diff
changeset
|
549 } |
|
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191
diff
changeset
|
550 } else { |
|
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191
diff
changeset
|
551 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
552 pixel = *sprite_buf; |
|
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191
diff
changeset
|
553 src = FBUF_SRC_S; |
|
d3266cee02c9
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191
diff
changeset
|
554 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
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191
diff
changeset
|
555 pixel = *plane_a; |
|
d3266cee02c9
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191
diff
changeset
|
556 src = a_src; |
|
d3266cee02c9
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191
diff
changeset
|
557 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
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191
diff
changeset
|
558 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
559 src = FBUF_SRC_B; |
|
233
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232
diff
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|
560 } else { |
|
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232
diff
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|
561 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
|
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232
diff
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|
562 src = FBUF_SHADOW; |
|
230
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191
diff
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|
563 } |
|
233
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232
diff
changeset
|
564 if (*sprite_buf & 0xF) { |
|
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232
diff
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|
565 pixel = *sprite_buf; |
|
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232
diff
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|
566 if (*sprite_buf & 0xF == 0xE) { |
|
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232
diff
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|
567 src = FBUF_SRC_S; |
|
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232
diff
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|
568 } else { |
|
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232
diff
changeset
|
569 src |= FBUF_SRC_S; |
|
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232
diff
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|
570 } |
|
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571 } else if (*plane_a & 0xF) { |
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diff
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572 pixel = *plane_a; |
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232
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|
573 src |= a_src; |
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|
574 } else if (*plane_b & 0xF){ |
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575 pixel = *plane_b; |
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576 src |= FBUF_SRC_B; |
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|
577 } else { |
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|
578 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
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|
579 src |= FBUF_SRC_BG; |
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|
580 } |
|
230
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|
581 } |
|
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|
582 } |
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|
583 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
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|
584 } |
|
230
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|
585 } else { |
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191
diff
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|
586 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) { |
|
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|
587 uint8_t pixel; |
|
d3266cee02c9
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|
588 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
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191
diff
changeset
|
589 pixel = *sprite_buf; |
|
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191
diff
changeset
|
590 src = FBUF_SRC_S; |
|
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|
591 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
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|
592 pixel = *plane_a; |
|
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diff
changeset
|
593 src = a_src; |
|
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191
diff
changeset
|
594 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
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changeset
|
595 pixel = *plane_b; |
|
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|
596 src = FBUF_SRC_B; |
|
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changeset
|
597 } else if (*sprite_buf & 0xF) { |
|
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|
598 pixel = *sprite_buf; |
|
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191
diff
changeset
|
599 src = FBUF_SRC_S; |
|
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diff
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|
600 } else if (*plane_a & 0xF) { |
|
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|
601 pixel = *plane_a; |
|
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Implemented shadow hilight mode.
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|
602 src = a_src; |
|
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|
603 } else if (*plane_b & 0xF){ |
|
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diff
changeset
|
604 pixel = *plane_b; |
|
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diff
changeset
|
605 src = FBUF_SRC_B; |
|
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diff
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|
606 } else { |
|
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191
diff
changeset
|
607 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
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|
608 src = FBUF_SRC_BG; |
|
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diff
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|
609 } |
|
291
eea3b118940d
Make sure all rendering operations mask CRAM with 0xEEE before using it
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610 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
230
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|
611 } |
|
20
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changeset
|
612 } |
|
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changeset
|
613 } else { |
|
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diff
changeset
|
614 //dst = context->framebuf + line * 320; |
|
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diff
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|
615 //sprite_buf = context->linebuf + col * 8; |
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diff
changeset
|
616 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
|
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|
617 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
|
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|
618 //end = dst + 8; |
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changeset
|
619 } |
|
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diff
changeset
|
620 |
| 40 | 621 uint16_t remaining; |
| 622 if (!(context->flags & FLAG_WINDOW)) { | |
| 623 remaining = context->hscroll_a & 0xF; | |
| 624 memcpy(context->tmp_buf_a + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_a + SCROLL_BUFFER_SIZE - remaining, remaining); | |
| 625 } | |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
626 remaining = context->hscroll_b & 0xF; |
|
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
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38
diff
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|
627 memcpy(context->tmp_buf_b + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_b + SCROLL_BUFFER_SIZE - remaining, remaining); |
|
20
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|
628 } |
|
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changeset
|
629 |
|
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diff
changeset
|
630 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
|
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diff
changeset
|
631 case startcyc:\ |
|
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diff
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|
632 read_map_scroll_a(column, line, context);\ |
|
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diff
changeset
|
633 break;\ |
|
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diff
changeset
|
634 case (startcyc+1):\ |
|
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diff
changeset
|
635 external_slot(context);\ |
|
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diff
changeset
|
636 break;\ |
|
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diff
changeset
|
637 case (startcyc+2):\ |
|
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diff
changeset
|
638 render_map_1(context);\ |
|
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diff
changeset
|
639 break;\ |
|
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diff
changeset
|
640 case (startcyc+3):\ |
|
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diff
changeset
|
641 render_map_2(context);\ |
|
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diff
changeset
|
642 break;\ |
|
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parents:
diff
changeset
|
643 case (startcyc+4):\ |
|
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parents:
diff
changeset
|
644 read_map_scroll_b(column, line, context);\ |
|
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Mostly broken VDP core and savestate viewer
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diff
changeset
|
645 break;\ |
|
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parents:
diff
changeset
|
646 case (startcyc+5):\ |
|
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parents:
diff
changeset
|
647 read_sprite_x(line, context);\ |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
648 break;\ |
|
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parents:
diff
changeset
|
649 case (startcyc+6):\ |
|
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parents:
diff
changeset
|
650 render_map_3(context);\ |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
651 break;\ |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
652 case (startcyc+7):\ |
|
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parents:
diff
changeset
|
653 render_map_output(line, column, context);\ |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
654 break; |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
655 |
|
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parents:
diff
changeset
|
656 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
|
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parents:
diff
changeset
|
657 case startcyc:\ |
|
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parents:
diff
changeset
|
658 read_map_scroll_a(column, line, context);\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
659 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
660 case (startcyc+1):\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
661 break;\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
662 case (startcyc+2):\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
663 render_map_1(context);\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
664 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
665 case (startcyc+3):\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
666 render_map_2(context);\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
667 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
668 case (startcyc+4):\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
669 read_map_scroll_b(column, line, context);\ |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
670 break;\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
671 case (startcyc+5):\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
672 read_sprite_x(line, context);\ |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
673 break;\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
674 case (startcyc+6):\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
675 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
676 break;\ |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
677 case (startcyc+7):\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
678 render_map_output(line, column, context);\ |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
679 break; |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
680 |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
681 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
682 { |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
683 uint16_t address; |
|
f664eeb55cb4
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parents:
diff
changeset
|
684 uint32_t mask; |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
685 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
686 { |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
687 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
688 case 0: |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
689 context->cur_slot = MAX_DRAWS-1; |
|
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
690 memset(context->linebuf, 0, LINEBUF_SIZE); |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
691 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
692 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
693 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
694 case 2: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
695 case 3: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
696 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
697 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
698 //sprite attribute table scan starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
699 case 4: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
700 render_sprite_cells( context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 context->sprite_index = 0x80; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
702 context->slot_counter = MAX_SPRITES_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
703 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
706 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
708 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
710 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
711 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
712 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
713 case 13: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 case 14: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
715 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
716 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
717 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 case 19: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
720 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
721 //!HSYNC asserted |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
722 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
723 case 22: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
724 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
725 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
726 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
727 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
728 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
729 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
730 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
731 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
732 case 26: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
733 case 27: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 case 28: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 case 31: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 case 32: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 case 33: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 case 34: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
741 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 case 35: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 mask = 0; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 if (context->regs[REG_MODE_3] & 0x2) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 mask |= 0xF8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 if (context->regs[REG_MODE_3] & 0x1) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 mask |= 0x7; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
752 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 line &= mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 address += line * 4; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
755 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
756 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
757 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 case 36: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 //!HSYNC high |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 case 37: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 case 38: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 case 39: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
764 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 case 40: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 read_map_scroll_a(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 case 41: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
771 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
772 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
773 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
774 case 42: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
775 render_map_1(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
776 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
777 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
778 case 43: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
779 render_map_2(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
780 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
781 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
782 case 44: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
783 read_map_scroll_b(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
784 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
785 case 45: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
786 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
788 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
789 case 46: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 render_map_3(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 case 47: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 render_map_output(line, 0, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 //reverse context slot counter so it counts the number of sprite slots |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 //filled rather than the number of available slots |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
798 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
|
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
799 context->cur_slot = MAX_SPRITES_LINE-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 context->sprite_draws = MAX_DRAWS; |
|
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
801 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 COLUMN_RENDER_BLOCK(2, 48) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 COLUMN_RENDER_BLOCK(4, 56) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 COLUMN_RENDER_BLOCK(6, 64) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 COLUMN_RENDER_BLOCK(10, 80) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 COLUMN_RENDER_BLOCK(12, 88) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 COLUMN_RENDER_BLOCK(14, 96) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
810 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 COLUMN_RENDER_BLOCK(18, 112) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 COLUMN_RENDER_BLOCK(20, 120) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
813 COLUMN_RENDER_BLOCK(22, 128) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 COLUMN_RENDER_BLOCK(26, 144) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 COLUMN_RENDER_BLOCK(28, 152) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 COLUMN_RENDER_BLOCK(30, 160) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
819 COLUMN_RENDER_BLOCK(34, 176) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 COLUMN_RENDER_BLOCK(36, 184) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 COLUMN_RENDER_BLOCK(38, 192) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 case 208: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 case 209: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 default: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 //leftovers from HSYNC clock change nonsense |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 { |
| 37 | 835 uint16_t address; |
| 836 uint32_t mask; | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 case 0: |
| 37 | 841 context->cur_slot = MAX_DRAWS_H32-1; |
| 842 memset(context->linebuf, 0, LINEBUF_SIZE); | |
| 843 render_sprite_cells(context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 case 2: |
| 37 | 847 case 3: |
| 848 render_sprite_cells(context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 break; |
| 37 | 850 //sprite attribute table scan starts |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 case 4: |
| 37 | 852 render_sprite_cells( context); |
| 853 context->sprite_index = 0x80; | |
| 854 context->slot_counter = MAX_SPRITES_LINE_H32; | |
| 855 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 case 13: |
| 37 | 866 render_sprite_cells(context); |
| 867 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 case 14: |
| 37 | 869 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 case 19: |
| 37 | 876 //HSYNC start |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 case 22: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 case 26: |
| 37 | 884 render_sprite_cells(context); |
| 885 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 case 27: |
| 37 | 888 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 case 28: |
| 37 | 891 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
| 892 mask = 0; | |
| 893 if (context->regs[REG_MODE_3] & 0x2) { | |
| 894 mask |= 0xF8; | |
| 895 } | |
| 896 if (context->regs[REG_MODE_3] & 0x1) { | |
| 897 mask |= 0x7; | |
| 898 } | |
| 899 line &= mask; | |
| 900 address += line * 4; | |
| 901 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
| 902 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
| 903 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case 31: |
| 37 | 908 case 32: |
| 909 render_sprite_cells(context); | |
| 910 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 break; |
| 37 | 912 //!HSYNC high |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 case 33: |
| 37 | 914 read_map_scroll_a(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 case 34: |
| 37 | 917 render_sprite_cells(context); |
| 918 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 case 35: |
| 37 | 921 render_map_1(context); |
| 922 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 case 36: |
| 37 | 925 render_map_2(context); |
| 926 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 case 37: |
| 37 | 929 read_map_scroll_b(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 case 38: |
| 37 | 932 render_sprite_cells(context); |
| 933 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 case 39: |
| 37 | 936 render_map_3(context); |
| 937 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 case 40: |
| 37 | 940 render_map_output(line, 0, context); |
| 941 scan_sprite_table(line, context);//Just a guess | |
| 942 //reverse context slot counter so it counts the number of sprite slots | |
| 943 //filled rather than the number of available slots | |
| 944 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
| 945 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
| 946 context->sprite_draws = MAX_DRAWS_H32; | |
| 947 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 break; |
| 37 | 949 COLUMN_RENDER_BLOCK(2, 41) |
| 950 COLUMN_RENDER_BLOCK(4, 49) | |
| 951 COLUMN_RENDER_BLOCK(6, 57) | |
| 952 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
| 953 COLUMN_RENDER_BLOCK(10, 73) | |
| 954 COLUMN_RENDER_BLOCK(12, 81) | |
| 955 COLUMN_RENDER_BLOCK(14, 89) | |
| 956 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
| 957 COLUMN_RENDER_BLOCK(18, 105) | |
| 958 COLUMN_RENDER_BLOCK(20, 113) | |
| 959 COLUMN_RENDER_BLOCK(22, 121) | |
| 960 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
| 961 COLUMN_RENDER_BLOCK(26, 137) | |
| 962 COLUMN_RENDER_BLOCK(28, 145) | |
| 963 COLUMN_RENDER_BLOCK(30, 153) | |
| 964 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 case 169: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 case 170: |
| 37 | 967 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 void latch_mode(vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
976 int is_refresh(vdp_context * context) |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
977 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
978 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
979 if (context->latched_mode & BIT_H40) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
980 linecyc = linecyc/16; |
|
189
806c3b7a6f2a
Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents:
180
diff
changeset
|
981 //TODO: Figure out the exact behavior that reduces DMA slots for direct color DMA demos |
|
806c3b7a6f2a
Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents:
180
diff
changeset
|
982 return (linecyc == 37 || linecyc == 69 || linecyc == 102 || linecyc == 133 || linecyc == 165 || linecyc == 197 || linecyc >= 210 || (linecyc < 6 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
983 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
984 linecyc = linecyc/20; |
|
189
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985 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
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986 //These numbers are guesses based on H40 numbers |
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987 return (linecyc == 24 || linecyc == 56 || linecyc == 88 || linecyc == 120 || linecyc == 152 || (linecyc < 5 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
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988 //The numbers below are the refresh slots during active display |
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989 //return (linecyc == 66 || linecyc == 98 || linecyc == 130 || linecyc == 162); |
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990 } |
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991 } |
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992 |
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993 void check_render_bg(vdp_context * context, int32_t line) |
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994 { |
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995 if (line > 0) { |
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996 line -= 1; |
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997 uint16_t * start = NULL, *end = NULL; |
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998 uint32_t linecyc = (context->cycles % MCLKS_LINE); |
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999 if (context->latched_mode & BIT_H40) { |
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1000 linecyc /= 16; |
|
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1001 if (linecyc >= 50 && linecyc < 210) { |
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1002 uint32_t x = (linecyc-50)*2; |
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1003 start = context->framebuf + line * 320 + x; |
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1004 end = start + 2; |
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1005 } |
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1006 } else { |
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1007 linecyc /= 20; |
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1008 if (linecyc >= 43 && linecyc < 171) { |
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1009 uint32_t x = (linecyc-43)*2; |
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1010 start = context->framebuf + line * 320 + x; |
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1011 end = start + 2; |
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1012 } |
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1013 } |
|
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1014 uint16_t color = (context->cram[context->regs[REG_BG_COLOR] & 0x3F] & 0xEEE); |
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1015 while (start != end) { |
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1016 *start = color; |
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1017 ++start; |
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1018 } |
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1019 } |
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1020 } |
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1021 |
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1022 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
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1023 { |
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1024 while(context->cycles < target_cycles) |
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1025 { |
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1026 uint32_t line = context->cycles / MCLKS_LINE; |
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1027 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
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1028 if (!line) { |
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1029 latch_mode(context); |
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1030 } |
|
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1031 uint32_t linecyc = context->cycles % MCLKS_LINE; |
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1032 if (linecyc == 0) { |
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1033 if (line <= 1 || line >= active_lines) { |
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1034 context->hint_counter = context->regs[REG_HINT]; |
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1035 } else if (context->hint_counter) { |
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1036 context->hint_counter--; |
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1037 } else { |
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1038 context->flags2 |= FLAG2_HINT_PENDING; |
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1039 context->hint_counter = context->regs[REG_HINT]; |
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1040 } |
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1041 } else if(line == active_lines) { |
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1042 uint32_t intcyc = context->latched_mode & BIT_H40 ? (148 + 40) * 4 : (132 + 28) * 5;; |
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1043 if (linecyc == intcyc) { |
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1044 context->flags2 |= FLAG2_VINT_PENDING; |
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|
1045 } |
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1046 } |
|
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1047 if (line < active_lines && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
|
20
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|
1048 //first sort-of active line is treated as 255 internally |
|
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1049 //it's used for gathering sprite info for line |
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1050 line = (line - 1) & 0xFF; |
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1051 |
|
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|
1052 //Convert to slot number |
|
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|
1053 if (context->latched_mode & BIT_H40){ |
|
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|
1054 //TODO: Deal with nasty clock switching during HBLANK |
|
317
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1055 uint32_t clock_inc = MCLKS_LINE-linecyc < 16 ? MCLKS_LINE-linecyc : 16; |
|
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|
1056 linecyc = linecyc/16; |
|
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1057 vdp_h40(line, linecyc, context); |
|
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1058 context->cycles += clock_inc; |
|
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|
1059 } else { |
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|
1060 linecyc = linecyc/20; |
|
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|
1061 vdp_h32(line, linecyc, context); |
|
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|
1062 context->cycles += 20; |
|
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|
1063 } |
|
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|
1064 } else { |
|
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1065 if (!is_refresh(context)) { |
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|
1066 external_slot(context); |
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|
1067 } |
|
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|
1068 if (line < active_lines) { |
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|
1069 check_render_bg(context, line); |
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1070 } |
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1071 if (context->latched_mode & BIT_H40){ |
|
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1072 uint32_t clock_inc = MCLKS_LINE-linecyc < 16 ? MCLKS_LINE-linecyc : 16; |
|
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|
1073 //TODO: Deal with nasty clock switching during HBLANK |
|
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1074 context->cycles += clock_inc; |
|
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|
1075 } else { |
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|
1076 context->cycles += 20; |
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|
1077 } |
|
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|
1078 } |
|
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|
1079 } |
|
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|
1080 } |
|
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|
1081 |
|
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|
1082 uint32_t vdp_run_to_vblank(vdp_context * context) |
|
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|
1083 { |
|
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|
1084 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
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|
1085 vdp_run_context(context, target_cycles); |
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|
1086 return context->cycles; |
|
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|
1087 } |
|
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|
1088 |
| 75 | 1089 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
| 1090 { | |
| 1091 for(;;) { | |
| 1092 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
| 1093 if (!dmalen) { | |
| 1094 dmalen = 0x10000; | |
| 1095 } | |
| 1096 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
| 1097 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
| 1098 //DMA copies take twice as long to complete since they require a read and a write | |
| 1099 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
| 1100 min_dma_complete *= 2; | |
| 1101 } | |
| 1102 min_dma_complete += context->cycles; | |
| 1103 if (target_cycles < min_dma_complete) { | |
| 1104 vdp_run_context(context, target_cycles); | |
| 1105 return; | |
| 1106 } else { | |
| 1107 vdp_run_context(context, min_dma_complete); | |
| 1108 if (!(context->flags & FLAG_DMA_RUN)) { | |
| 1109 return; | |
| 1110 } | |
| 1111 } | |
| 1112 } | |
| 1113 } | |
| 1114 | |
| 1115 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
|
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1116 { |
|
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1117 //printf("control port write: %X\n", value); |
|
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1118 if (context->flags & FLAG_DMA_RUN) { |
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1119 return -1; |
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1120 } |
|
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1121 if (context->flags & FLAG_PENDING) { |
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1122 context->address = (context->address & 0x3FFF) | (value << 14); |
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1123 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
| 75 | 1124 context->flags &= ~FLAG_PENDING; |
|
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1125 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
| 75 | 1126 if (context->cd & 0x20) { |
| 1127 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { | |
| 1128 //DMA copy or 68K -> VDP, transfer starts immediately | |
| 1129 context->flags |= FLAG_DMA_RUN; | |
|
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1130 context->dma_cd = context->cd; |
| 75 | 1131 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
| 1132 return 1; | |
| 1133 } | |
| 1134 } | |
|
63
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Add FPS counter to console output
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|
1135 } |
|
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1136 } else { |
|
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1137 if ((value & 0xC000) == 0x8000) { |
|
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1138 //Register write |
|
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1139 uint8_t reg = (value >> 8) & 0x1F; |
|
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1140 if (reg < VDP_REGS) { |
|
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1141 //printf("register %d set to %X\n", reg, value & 0xFF); |
|
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1142 context->regs[reg] = value; |
|
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|
1143 if (reg == REG_MODE_2) { |
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1144 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); |
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1145 } |
|
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1146 } |
|
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1147 } else { |
|
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1148 context->flags |= FLAG_PENDING; |
|
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1149 context->address = (context->address &0xC000) | (value & 0x3FFF); |
|
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1150 context->cd = (context->cd &0x3C) | (value >> 14); |
|
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1151 } |
|
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1152 } |
| 75 | 1153 return 0; |
|
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1154 } |
|
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1155 |
|
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1156 int vdp_data_port_write(vdp_context * context, uint16_t value) |
|
54
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1157 { |
|
58
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1158 //printf("data port write: %X\n", value); |
|
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1159 if (context->flags & FLAG_DMA_RUN) { |
|
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1160 return -1; |
|
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1161 } |
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1162 if (!(context->cd & 1)) { |
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1163 //ignore writes when cd is configured for read |
|
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1164 return 0; |
|
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1165 } |
|
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|
1166 context->flags &= ~FLAG_PENDING; |
|
109
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1167 /*if (context->fifo_cur == context->fifo_end) { |
|
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1168 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
|
109
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1169 }*/ |
|
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1170 while (context->fifo_cur == context->fifo_end) { |
|
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1171 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
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1172 } |
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|
1173 context->fifo_cur->cycle = context->cycles; |
| 138 | 1174 context->fifo_cur->address = context->address; |
|
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1175 context->fifo_cur->value = value; |
| 138 | 1176 context->fifo_cur->cd = context->cd; |
|
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1177 context->fifo_cur->partial = 0; |
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1178 context->fifo_cur++; |
| 138 | 1179 context->address += context->regs[REG_AUTOINC]; |
|
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1180 return 0; |
|
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1181 } |
|
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1182 |
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1183 uint16_t vdp_control_port_read(vdp_context * context) |
|
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1184 { |
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1185 context->flags &= ~FLAG_PENDING; |
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1186 uint16_t value = 0x3400; |
|
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1187 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) { |
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1188 value |= 0x200; |
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1189 } |
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1190 if (context->fifo_cur == context->fifo_end) { |
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1191 value |= 0x100; |
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1192 } |
|
317
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|
1193 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
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1194 value |- 0x80; |
|
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1195 } |
|
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1196 if (context->flags & FLAG_DMA_RUN) { |
|
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|
1197 value |= 0x2; |
| 75 | 1198 } |
| 137 | 1199 uint32_t line= context->cycles / MCLKS_LINE; |
| 1200 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { | |
| 1201 value |= 0x8; | |
| 1202 } | |
|
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1203 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
|
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1204 value |= 0x1; |
|
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1205 } |
|
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1206 //TODO: Lots of other bits in status port |
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1207 return value; |
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1208 } |
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1209 |
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1210 uint16_t vdp_data_port_read(vdp_context * context) |
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1211 { |
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1212 context->flags &= ~FLAG_PENDING; |
| 138 | 1213 if (context->cd & 1) { |
|
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1214 return 0; |
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1215 } |
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1216 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
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1217 context->flags &= ~FLAG_UNUSED_SLOT; |
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1218 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
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1219 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
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1220 } |
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1221 uint16_t value = 0; |
| 138 | 1222 switch (context->cd & 0xF) |
|
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1223 { |
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1224 case VRAM_READ: |
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1225 value = context->vdpmem[context->address] << 8; |
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1226 context->flags &= ~FLAG_UNUSED_SLOT; |
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1227 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
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1228 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
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1229 } |
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1230 value |= context->vdpmem[context->address ^ 1]; |
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1231 break; |
|
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|
1232 case CRAM_READ: |
|
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|
1233 value = context->cram[(context->address/2) & (CRAM_SIZE-1)]; |
|
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|
1234 break; |
|
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|
1235 case VSRAM_READ: |
|
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|
1236 if (((context->address / 2) & 63) < VSRAM_SIZE) { |
|
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diff
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|
1237 value = context->vsram[context->address & 63]; |
|
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diff
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|
1238 } |
|
3b79cbcf6846
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diff
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|
1239 break; |
|
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diff
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|
1240 } |
|
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|
1241 context->address += context->regs[REG_AUTOINC]; |
|
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diff
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|
1242 return value; |
|
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diff
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|
1243 } |
|
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|
1244 |
| 137 | 1245 uint16_t vdp_hv_counter_read(vdp_context * context) |
| 1246 { | |
| 1247 uint32_t line= context->cycles / MCLKS_LINE; | |
| 1248 if (!line) { | |
| 1249 line = 0xFF; | |
| 1250 } else { | |
| 1251 line--; | |
| 1252 if (line > 0xEA) { | |
| 1253 line = (line + 0xFA) & 0xFF; | |
| 1254 } | |
| 1255 } | |
| 1256 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
| 1257 if (context->latched_mode & BIT_H40) { | |
| 1258 linecyc /= 8; | |
| 1259 if (linecyc >= 86) { | |
| 1260 linecyc -= 86; | |
| 1261 } else { | |
| 1262 linecyc += 334; | |
| 1263 } | |
| 1264 if (linecyc > 0x16C) { | |
| 1265 linecyc += 92; | |
| 1266 } | |
| 1267 } else { | |
| 1268 linecyc /= 10; | |
| 1269 if (linecyc >= 74) { | |
| 1270 linecyc -= 74; | |
| 1271 } else { | |
| 1272 linecyc += 268; | |
| 1273 } | |
| 1274 if (linecyc > 0x127) { | |
| 1275 linecyc += 170; | |
| 1276 } | |
| 1277 } | |
| 1278 linecyc &= 0xFF; | |
| 1279 return (line << 8) | linecyc; | |
| 1280 } | |
| 1281 | |
|
65
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|
1282 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
|
aef6302770c2
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|
1283 { |
|
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|
1284 context->cycles -= deduction; |
|
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|
1285 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) { |
|
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|
1286 if (start->cycle >= deduction) { |
|
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|
1287 start->cycle -= deduction; |
|
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|
1288 } else { |
|
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diff
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|
1289 start->cycle = 0; |
|
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|
1290 } |
|
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|
1291 } |
|
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|
1292 } |
|
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|
1293 |
|
317
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|
1294 uint32_t vdp_next_hint(vdp_context * context) |
|
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1295 { |
|
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|
1296 if (!(context->regs[REG_MODE_1] & 0x10)) { |
|
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|
1297 return 0xFFFFFFFF; |
|
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1298 } |
|
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|
1299 if (context->flags2 & FLAG2_HINT_PENDING) { |
|
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|
1300 return context->cycles; |
|
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|
1301 } |
|
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|
1302 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
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|
1303 uint32_t line = context->cycles / MCLKS_LINE; |
|
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|
1304 if (line >= active_lines) { |
|
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|
1305 return 0xFFFFFFFF; |
|
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|
1306 } |
|
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diff
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|
1307 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
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|
1308 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
|
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|
1309 if (!line) { |
|
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|
1310 hcycle += MCLKS_LINE; |
|
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diff
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|
1311 } |
|
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291
diff
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|
1312 return hcycle; |
|
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|
1313 } |
|
e5e8b48ad157
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|
1314 |
|
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|
1315 uint32_t vdp_next_vint(vdp_context * context) |
|
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diff
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|
1316 { |
|
e5e8b48ad157
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Mike Pavone <pavone@retrodev.com>
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|
1317 if (!(context->regs[REG_MODE_2] & 0x20)) { |
|
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Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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diff
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|
1318 return 0xFFFFFFFF; |
|
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diff
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|
1319 } |
|
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Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
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291
diff
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|
1320 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
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|
1321 return context->cycles; |
|
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|
1322 } |
|
e5e8b48ad157
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Mike Pavone <pavone@retrodev.com>
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diff
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|
1323 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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291
diff
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|
1324 uint32_t vcycle = MCLKS_LINE * active_lines; |
|
e5e8b48ad157
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291
diff
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|
1325 if (context->latched_mode & BIT_H40) { |
|
e5e8b48ad157
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diff
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|
1326 vcycle += (148 + 40) * 4; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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291
diff
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|
1327 } else { |
|
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Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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291
diff
changeset
|
1328 vcycle += (132 + 28) * 5; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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diff
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|
1329 } |
|
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Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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291
diff
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|
1330 if (vcycle < context->cycles) { |
|
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Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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|
1331 return 0xFFFFFFFF; |
|
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Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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|
1332 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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291
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|
1333 return vcycle; |
|
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Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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|
1334 } |
|
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|
1335 |
|
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Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
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291
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|
1336 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
|
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|
1337 { |
|
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|
1338 if (int_num == 6) { |
|
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|
1339 context->flags2 &= ~FLAG2_VINT_PENDING; |
|
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|
1340 } else if(int_num ==4) { |
|
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|
1341 context->flags2 &= ~FLAG2_HINT_PENDING; |
|
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|
1342 } |
|
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|
1343 } |
|
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|
1344 |
|
20
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diff
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|
1345 #define GST_VDP_REGS 0xFA |
|
f664eeb55cb4
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diff
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|
1346 #define GST_VDP_MEM 0x12478 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1347 |
|
f664eeb55cb4
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|
1348 void vdp_load_savestate(vdp_context * context, FILE * state_file) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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|
1349 { |
|
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Mostly broken VDP core and savestate viewer
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|
1350 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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|
1351 fseek(state_file, GST_VDP_REGS, SEEK_SET); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
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|
1352 fread(context->regs, 1, VDP_REGS, state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
changeset
|
1353 latch_mode(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1354 fread(tmp_buf, 1, sizeof(tmp_buf), state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
changeset
|
1355 for (int i = 0; i < CRAM_SIZE; i++) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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diff
changeset
|
1356 context->cram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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|
1357 } |
|
f664eeb55cb4
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diff
changeset
|
1358 fread(tmp_buf, 2, VSRAM_SIZE, state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1359 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
23
3e924bb56560
Fix endianness of VSRAM when read from Genecyst save state
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22
diff
changeset
|
1360 context->vsram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
20
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diff
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|
1361 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1362 fseek(state_file, GST_VDP_MEM, SEEK_SET); |
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f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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1363 fread(context->vdpmem, 1, VRAM_SIZE, state_file); |
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f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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1364 } |
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54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
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1365 |
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56
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
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1366 void vdp_save_state(vdp_context * context, FILE * outfile) |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
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parents:
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diff
changeset
|
1367 { |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
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parents:
54
diff
changeset
|
1368 uint8_t tmp_buf[CRAM_SIZE*2]; |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
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parents:
54
diff
changeset
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1369 fseek(outfile, GST_VDP_REGS, SEEK_SET); |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
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parents:
54
diff
changeset
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1370 fwrite(context->regs, 1, VDP_REGS, outfile); |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
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parents:
54
diff
changeset
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1371 for (int i = 0; i < CRAM_SIZE; i++) { |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
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1372 tmp_buf[i*2] = context->cram[i]; |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1373 tmp_buf[i*2+1] = context->cram[i] >> 8; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1374 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1375 fwrite(tmp_buf, 1, sizeof(tmp_buf), outfile); |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1376 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1377 tmp_buf[i*2] = context->vsram[i]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1378 tmp_buf[i*2+1] = context->vsram[i] >> 8; |
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a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1379 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1380 fwrite(tmp_buf, 2, VSRAM_SIZE, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1381 fseek(outfile, GST_VDP_MEM, SEEK_SET); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1382 fwrite(context->vdpmem, 1, VRAM_SIZE, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1383 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
1384 |