Mercurial > repos > blastem
annotate m68k_util.c @ 2590:e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Sun, 09 Feb 2025 02:57:37 -0800 |
parents | e04c7e753bf6 |
children | 1c493b8c513b |
rev | line source |
---|---|
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1 #include <string.h> |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3 void m68k_read_8(m68k_context *context) |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4 { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
5 context->cycles += 4 * context->opts->gen.clock_divider; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
6 context->scratch1 = read_byte(context->scratch1, context->mem_pointers, &context->opts->gen, context); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
7 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
8 |
2590
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
9 #ifdef DEBUG_DISASM |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
10 #include "68kinst.h" |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
11 static uint16_t debug_disasm_fetch(uint32_t address, void *vcontext) |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
12 { |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
13 m68k_context *context = vcontext; |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
14 return read_word(address, context->mem_pointers, &context->opts->gen, context); |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
15 } |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
16 #endif |
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
17 void m68k_read_16(m68k_context *context) |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
18 { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
19 context->cycles += 4 * context->opts->gen.clock_divider; |
2590
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
20 #ifdef DEBUG_DISASM |
2587
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
21 uint32_t tmp = context->scratch1; |
2590
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
22 #endif |
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
23 context->scratch1 = read_word(context->scratch1, context->mem_pointers, &context->opts->gen, context); |
2590
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
24 #ifdef DEBUG_DISASM |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
25 if (tmp == context->pc) { |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
26 m68kinst inst; |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
27 m68k_decode(debug_disasm_fetch, context, &inst, tmp); |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
28 static char disasm_buf[256]; |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
29 m68k_disasm(&inst, disasm_buf); |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
30 printf("Fetch %05X: %04X - %s, d2 = %X, d3 = %X, d4 = %X, d6 = %X, xflag = %d\n", tmp, context->scratch1, disasm_buf, context->dregs[2], context->dregs[3], context->dregs[4], context->dregs[6], context->xflag); |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
31 } |
e602dbf776d8
Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2587
diff
changeset
|
32 #endif |
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
33 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
34 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
35 void m68k_write_8(m68k_context *context) |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
36 { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
37 context->cycles += 4 * context->opts->gen.clock_divider; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
38 write_byte(context->scratch2, context->scratch1, context->mem_pointers, &context->opts->gen, context); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
39 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
40 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
41 void m68k_write_16(m68k_context *context) |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
42 { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
43 context->cycles += 4 * context->opts->gen.clock_divider; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
44 write_word(context->scratch2, context->scratch1, context->mem_pointers, &context->opts->gen, context); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
45 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
46 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
47 void m68k_sync_cycle(m68k_context *context, uint32_t target_cycle) |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
48 { |
2577
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
49 context->sync_cycle = target_cycle; //why? |
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
50 context->sync_components(context, 0); |
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
51 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
52 |
2587
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
53 static void divu(m68k_context *context, uint32_t dividend_reg, uint32_t divisor) |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
54 { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
55 uint32_t dividend = context->dregs[dividend_reg]; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
56 uint32_t divisor_shift = divisor << 16; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
57 uint16_t quotient = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
58 uint8_t force = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
59 uint16_t bit = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
60 uint32_t cycles = 2; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
61 if (divisor_shift < dividend) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
62 context->nflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
63 context->zflag = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
64 context->vflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
65 context->cycles += 6 * context->opts->gen.clock_divider; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
66 return; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
67 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
68 for (int i = 0; i < 16; i++) |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
69 { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
70 force = dividend >> 31; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
71 quotient = quotient << 1 | bit; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
72 dividend = dividend << 1; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
73 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
74 if (force || dividend >= divisor_shift) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
75 dividend -= divisor_shift; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
76 cycles += force ? 4 : 6; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
77 bit = 1; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
78 } else { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
79 bit = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
80 cycles += 8; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
81 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
82 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
83 cycles += force ? 6 : bit ? 4 : 2; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
84 context->cycles += cycles * context->opts->gen.clock_divider; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
85 quotient = quotient << 1 | bit; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
86 context->dregs[dividend_reg] = dividend | quotient; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
87 context->vflag = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
88 context->nflag = quotient >> 8 & 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
89 context->zflag = quotient == 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
90 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
91 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
92 static void divs(m68k_context *context, uint32_t dividend_reg, uint32_t divisor) |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
93 { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
94 uint32_t dividend = context->dregs[dividend_reg]; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
95 uint32_t divisor_shift = divisor << 16; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
96 uint32_t orig_divisor = divisor_shift, orig_dividend = dividend; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
97 if (divisor_shift & 0x80000000) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
98 divisor_shift = 0 - divisor_shift; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
99 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
100 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
101 uint32_t cycles = 8; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
102 if (dividend & 0x80000000) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
103 //dvs10 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
104 dividend = 0 - dividend; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
105 cycles += 2; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
106 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
107 if (divisor_shift <= dividend) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
108 context->vflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
109 context->nflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
110 context->zflag = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
111 cycles += 4; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
112 context->cycles += cycles * context->opts->gen.clock_divider; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
113 return; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
114 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
115 uint16_t quotient = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
116 uint16_t bit = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
117 for (int i = 0; i < 15; i++) |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
118 { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
119 quotient = quotient << 1 | bit; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
120 dividend = dividend << 1; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
121 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
122 if (dividend >= divisor_shift) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
123 dividend -= divisor_shift; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
124 cycles += 6; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
125 bit = 1; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
126 } else { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
127 bit = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
128 cycles += 8; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
129 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
130 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
131 quotient = quotient << 1 | bit; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
132 dividend = dividend << 1; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
133 if (dividend >= divisor_shift) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
134 dividend -= divisor_shift; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
135 quotient = quotient << 1 | 1; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
136 } else { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
137 quotient = quotient << 1; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
138 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
139 cycles += 4; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
140 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
141 context->vflag = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
142 if (orig_divisor & 0x80000000) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
143 cycles += 16; //was 10 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
144 if (orig_dividend & 0x80000000) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
145 if (quotient & 0x8000) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
146 context->vflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
147 context->nflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
148 context->zflag = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
149 context->cycles += cycles * context->opts->gen.clock_divider; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
150 return; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
151 } else { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
152 dividend = -dividend; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
153 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
154 } else { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
155 quotient = -quotient; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
156 if (quotient && !(quotient & 0x8000)) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
157 context->vflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
158 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
159 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
160 } else if (orig_dividend & 0x80000000) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
161 cycles += 18; // was 12 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
162 quotient = -quotient; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
163 if (quotient && !(quotient & 0x8000)) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
164 context->vflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
165 } else { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
166 dividend = -dividend; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
167 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
168 } else { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
169 cycles += 14; //was 10 |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
170 if (quotient & 0x8000) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
171 context->vflag= 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
172 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
173 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
174 if (context->vflag) { |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
175 context->nflag = 128; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
176 context->zflag = 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
177 context->cycles += cycles * context->opts->gen.clock_divider; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
178 return; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
179 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
180 context->nflag = (quotient & 0x8000) ? 128 : 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
181 context->zflag = quotient == 0; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
182 //V was cleared above, C is cleared by the generated machine code |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
183 context->cycles += cycles * context->opts->gen.clock_divider; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
184 context->dregs[dividend_reg] = dividend | quotient; |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
185 } |
e04c7e753bf6
Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2580
diff
changeset
|
186 |
2577
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
187 static sync_fun *sync_comp_tmp; |
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
188 static int_ack_fun int_ack_tmp; |
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
189 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun *sync_components, int_ack_fun int_ack) |
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
190 { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
191 memset(opts, 0, sizeof(*opts)); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
192 opts->gen.memmap = memmap; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
193 opts->gen.memmap_chunks = num_chunks; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
194 opts->gen.address_mask = 0xFFFFFF; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
195 opts->gen.byte_swap = 1; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
196 opts->gen.max_address = 0x1000000; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
197 opts->gen.bus_cycles = 4; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
198 opts->gen.clock_divider = clock_divider; |
2577
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
199 sync_comp_tmp = sync_components; |
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
200 int_ack_tmp = int_ack; |
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
201 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
202 |
2577
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
203 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler *reset_handler) |
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
204 { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
205 m68k_context *context = calloc(1, sizeof(m68k_context)); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
206 context->opts = opts; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
207 context->reset_handler = reset_handler; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
208 context->int_cycle = 0xFFFFFFFFU; |
2580
939b818df589
Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents:
2577
diff
changeset
|
209 context->int_pending = 255; |
2577
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
210 context->sync_components = sync_comp_tmp; |
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
211 sync_comp_tmp = NULL; |
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
212 context->int_ack_handler = int_ack_tmp; |
5f725429d08f
WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents:
2500
diff
changeset
|
213 int_ack_tmp = NULL; |
1951
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
214 return context; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
215 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
216 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
217 void m68k_reset(m68k_context *context) |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
218 { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
219 //read initial SP |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
220 context->scratch1 = 0; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
221 m68k_read_16(context); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
222 context->aregs[7] = context->scratch1 << 16; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
223 context->scratch1 = 2; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
224 m68k_read_16(context); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
225 context->aregs[7] |= context->scratch1; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
226 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
227 //read initial PC |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
228 context->scratch1 = 4; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
229 m68k_read_16(context); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
230 context->pc = context->scratch1 << 16; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
231 context->scratch1 = 6; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
232 m68k_read_16(context); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
233 context->pc |= context->scratch1; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
234 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
235 context->scratch1 = context->pc; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
236 m68k_read_16(context); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
237 context->prefetch = context->scratch1; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
238 context->pc += 2; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
239 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
240 context->status = 0x27; |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
241 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
242 |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
243 void m68k_print_regs(m68k_context *context) |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
244 { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
245 printf("XNZVC\n%d%d%d%d%d\n", context->xflag != 0, context->nflag != 0, context->zflag != 0, context->vflag != 0, context->cflag != 0); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
246 for (int i = 0; i < 8; i++) { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
247 printf("d%d: %X\n", i, context->dregs[i]); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
248 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
249 for (int i = 0; i < 8; i++) { |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
250 printf("a%d: %X\n", i, context->aregs[i]); |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
251 } |
8494fe8d6b65
Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
252 } |
2499
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
253 |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
254 void m68k_serialize(m68k_context *context, uint32_t pc, serialize_buffer *buf) |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
255 { |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
256 //TODO: implement me |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
257 } |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
258 |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
259 void m68k_deserialize(deserialize_buffer *buf, void *vcontext) |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
260 { |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
261 //TODO: implement me |
d74d3998482c
Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2447
diff
changeset
|
262 } |
2500
d44fe974fb85
Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2499
diff
changeset
|
263 |
d44fe974fb85
Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2499
diff
changeset
|
264 void start_68k_context(m68k_context *context, uint32_t pc) |
d44fe974fb85
Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2499
diff
changeset
|
265 { |
d44fe974fb85
Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2499
diff
changeset
|
266 context->scratch1 = context->pc = pc; |
d44fe974fb85
Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2499
diff
changeset
|
267 m68k_read_16(context); |
d44fe974fb85
Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2499
diff
changeset
|
268 context->prefetch = context->scratch1; |
d44fe974fb85
Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2499
diff
changeset
|
269 context->pc += 2; |
d44fe974fb85
Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
2499
diff
changeset
|
270 } |