Mercurial > repos > blastem
annotate m68k_to_x86.c @ 71:f80fa1776507
Implement more instructions and address modes
author | Mike Pavone <pavone@retrodev.com> |
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date | Fri, 21 Dec 2012 01:00:52 -0800 |
parents | cebd0b5ac7f0 |
children | 8da611e69b32 |
rev | line source |
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1 #include "gen_x86.h" |
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2 #include "m68k_to_x86.h" |
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3 #include <stdio.h> |
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4 #include <stddef.h> |
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5 #include <stdlib.h> |
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6 #include <string.h> |
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7 |
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8 #define BUS 4 |
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9 #define PREDEC_PENALTY 2 |
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10 #define CYCLES RAX |
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11 #define LIMIT RBP |
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12 #define SCRATCH1 RCX |
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13 #define SCRATCH2 RDI |
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14 #define CONTEXT RSI |
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15 |
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16 #define FLAG_N RBX |
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17 #define FLAG_V BH |
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18 #define FLAG_Z RDX |
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19 #define FLAG_C DH |
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20 |
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21 typedef struct { |
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22 int32_t disp; |
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23 uint8_t mode; |
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24 uint8_t base; |
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25 uint8_t index; |
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26 uint8_t cycles; |
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27 } x86_ea; |
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28 |
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29 void handle_cycle_limit(); |
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30 void m68k_read_word_scratch1(); |
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31 void m68k_read_long_scratch1(); |
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32 void m68k_read_byte_scratch1(); |
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33 void m68k_write_word(); |
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34 void m68k_write_long_lowfirst(); |
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35 void m68k_write_long_highfirst(); |
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36 void m68k_write_byte(); |
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37 void m68k_save_context(); |
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38 void m68k_modified_ret_addr(); |
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39 void m68k_native_addr(); |
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40 void m68k_start_context(uint8_t * addr, m68k_context * context); |
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41 |
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42 uint8_t * cycles(uint8_t * dst, uint32_t num) |
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43 { |
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44 dst = add_ir(dst, num, CYCLES, SZ_D); |
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45 } |
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46 |
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47 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) |
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48 { |
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49 if (op->addr_mode == MODE_REG) { |
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50 return opts->dregs[op->params.regs.pri]; |
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51 } |
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52 if (op->addr_mode == MODE_AREG) { |
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53 return opts->aregs[op->params.regs.pri]; |
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54 } |
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55 return -1; |
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56 } |
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57 |
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58 //must be called with an m68k_op_info that uses a register |
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59 size_t reg_offset(m68k_op_info *op) |
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60 { |
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61 if (op->addr_mode == MODE_REG) { |
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62 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri; |
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63 } |
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64 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri; |
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65 } |
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66 |
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67 void print_regs_exit(m68k_context * context) |
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68 { |
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69 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]); |
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70 for (int i = 0; i < 8; i++) { |
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71 printf("d%d: %X\n", i, context->dregs[i]); |
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72 } |
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73 for (int i = 0; i < 8; i++) { |
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74 printf("a%d: %X\n", i, context->aregs[i]); |
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75 } |
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76 exit(0); |
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77 } |
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78 |
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79 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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80 { |
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81 int8_t reg = native_reg(&(inst->src), opts); |
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82 int32_t dec_amount,inc_amount; |
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83 if (reg >= 0) { |
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84 ea->mode = MODE_REG_DIRECT; |
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85 ea->base = reg; |
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86 return out; |
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87 } |
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88 switch (inst->src.addr_mode) |
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89 { |
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90 case MODE_REG: |
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91 case MODE_AREG: |
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92 //We only get one memory parameter, so if the dst operand is a register in memory, |
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93 //we need to copy this to a temp register first |
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94 reg = native_reg(&(inst->dst), opts); |
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95 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode == MODE_AREG) |
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96 || inst->op == M68K_EXG) { |
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97 |
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98 ea->mode = MODE_REG_DISPLACE8; |
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99 ea->base = CONTEXT; |
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100 ea->disp = reg_offset(&(inst->src)); |
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101 } else { |
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102 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size); |
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103 ea->mode = MODE_REG_DIRECT; |
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104 ea->base = SCRATCH1; |
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105 } |
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106 break; |
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107 case MODE_AREG_PREDEC: |
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108 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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109 out = cycles(out, PREDEC_PENALTY); |
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110 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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111 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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112 } else { |
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113 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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114 } |
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115 case MODE_AREG_INDIRECT: |
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116 case MODE_AREG_POSTINC: |
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117 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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118 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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119 } else { |
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120 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
18
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121 } |
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122 switch (inst->extra.size) |
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123 { |
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124 case OPSIZE_BYTE: |
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125 out = call(out, (char *)m68k_read_byte_scratch1); |
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126 break; |
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127 case OPSIZE_WORD: |
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128 out = call(out, (char *)m68k_read_word_scratch1); |
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129 break; |
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130 case OPSIZE_LONG: |
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131 out = call(out, (char *)m68k_read_long_scratch1); |
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132 break; |
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133 } |
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134 |
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135 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
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136 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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137 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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138 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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139 } else { |
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140 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
18
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141 } |
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142 } |
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143 ea->mode = MODE_REG_DIRECT; |
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144 ea->base = SCRATCH1; |
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145 break; |
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146 case MODE_AREG_DISPLACE: |
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147 out = cycles(out, BUS); |
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148 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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149 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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150 } else { |
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151 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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152 } |
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153 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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154 switch (inst->extra.size) |
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155 { |
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156 case OPSIZE_BYTE: |
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157 out = call(out, (char *)m68k_read_byte_scratch1); |
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158 break; |
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159 case OPSIZE_WORD: |
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160 out = call(out, (char *)m68k_read_word_scratch1); |
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161 break; |
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162 case OPSIZE_LONG: |
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163 out = call(out, (char *)m68k_read_long_scratch1); |
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164 break; |
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165 } |
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166 ea->mode = MODE_REG_DIRECT; |
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167 ea->base = SCRATCH1; |
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168 break; |
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169 case MODE_PC_DISPLACE: |
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170 out = cycles(out, BUS); |
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171 out = mov_ir(out, inst->src.params.regs.displacement + inst->address, SCRATCH1, SZ_D); |
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172 switch (inst->extra.size) |
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173 { |
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174 case OPSIZE_BYTE: |
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175 out = call(out, (char *)m68k_read_byte_scratch1); |
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176 break; |
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177 case OPSIZE_WORD: |
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178 out = call(out, (char *)m68k_read_word_scratch1); |
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179 break; |
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180 case OPSIZE_LONG: |
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181 out = call(out, (char *)m68k_read_long_scratch1); |
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182 break; |
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183 } |
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184 ea->mode = MODE_REG_DIRECT; |
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185 ea->base = SCRATCH1; |
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186 break; |
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187 case MODE_ABSOLUTE: |
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188 case MODE_ABSOLUTE_SHORT: |
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189 if (inst->src.addr_mode == MODE_ABSOLUTE) { |
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190 out = cycles(out, BUS*2); |
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191 } else { |
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192 out = cycles(out, BUS); |
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193 } |
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194 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D); |
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195 switch (inst->extra.size) |
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196 { |
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197 case OPSIZE_BYTE: |
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198 out = call(out, (char *)m68k_read_byte_scratch1); |
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199 break; |
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200 case OPSIZE_WORD: |
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201 out = call(out, (char *)m68k_read_word_scratch1); |
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202 break; |
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203 case OPSIZE_LONG: |
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204 out = call(out, (char *)m68k_read_long_scratch1); |
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205 break; |
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206 } |
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207 ea->mode = MODE_REG_DIRECT; |
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208 ea->base = SCRATCH1; |
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209 break; |
18
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210 case MODE_IMMEDIATE: |
61
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59
diff
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|
211 case MODE_IMMEDIATE_WORD: |
18
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212 if (inst->variant != VAR_QUICK) { |
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2b1a65f4b85d
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213 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
18
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214 } |
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215 ea->mode = MODE_IMMED; |
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216 ea->disp = inst->src.params.immed; |
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217 break; |
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218 default: |
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219 printf("address mode %d not implemented (src)\n", inst->src.addr_mode); |
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220 exit(1); |
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221 } |
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222 return out; |
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223 } |
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|
224 |
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225 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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226 { |
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227 int8_t reg = native_reg(&(inst->dst), opts); |
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228 int32_t dec_amount, inc_amount; |
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229 if (reg >= 0) { |
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230 ea->mode = MODE_REG_DIRECT; |
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231 ea->base = reg; |
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232 return out; |
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233 } |
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234 switch (inst->dst.addr_mode) |
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235 { |
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236 case MODE_REG: |
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237 case MODE_AREG: |
18
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238 ea->mode = MODE_REG_DISPLACE8; |
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239 ea->base = CONTEXT; |
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240 ea->disp = reg_offset(&(inst->dst)); |
18
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241 break; |
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242 case MODE_AREG_PREDEC: |
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243 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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244 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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245 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
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246 } else { |
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247 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
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248 } |
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249 case MODE_AREG_INDIRECT: |
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250 case MODE_AREG_POSTINC: |
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251 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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252 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
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253 } else { |
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254 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
18
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255 } |
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256 switch (inst->extra.size) |
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257 { |
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258 case OPSIZE_BYTE: |
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259 out = call(out, (char *)m68k_read_byte_scratch1); |
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260 break; |
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261 case OPSIZE_WORD: |
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262 out = call(out, (char *)m68k_read_word_scratch1); |
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263 break; |
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264 case OPSIZE_LONG: |
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265 out = call(out, (char *)m68k_read_long_scratch1); |
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266 break; |
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267 } |
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268 //save reg value in SCRATCH2 so we can use it to save the result in memory later |
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269 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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270 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
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271 } else { |
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272 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
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273 } |
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274 |
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275 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
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276 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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277 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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278 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
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279 } else { |
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280 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
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281 } |
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282 } |
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283 ea->mode = MODE_REG_DIRECT; |
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284 ea->base = SCRATCH1; |
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285 break; |
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286 case MODE_AREG_DISPLACE: |
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287 out = cycles(out, BUS); |
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288 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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289 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
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290 } else { |
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291 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
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292 } |
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293 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
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294 out = push_r(out, SCRATCH1); |
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295 switch (inst->extra.size) |
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296 { |
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297 case OPSIZE_BYTE: |
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298 out = call(out, (char *)m68k_read_byte_scratch1); |
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299 break; |
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300 case OPSIZE_WORD: |
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301 out = call(out, (char *)m68k_read_word_scratch1); |
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302 break; |
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303 case OPSIZE_LONG: |
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304 out = call(out, (char *)m68k_read_long_scratch1); |
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305 break; |
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306 } |
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307 out = pop_r(out, SCRATCH2); |
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308 ea->mode = MODE_REG_DIRECT; |
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309 ea->base = SCRATCH1; |
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310 break; |
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311 case MODE_PC_DISPLACE: |
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312 out = cycles(out, BUS); |
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313 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address, SCRATCH1, SZ_D); |
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314 out = push_r(out, SCRATCH1); |
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315 switch (inst->extra.size) |
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316 { |
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317 case OPSIZE_BYTE: |
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318 out = call(out, (char *)m68k_read_byte_scratch1); |
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319 break; |
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320 case OPSIZE_WORD: |
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321 out = call(out, (char *)m68k_read_word_scratch1); |
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322 break; |
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323 case OPSIZE_LONG: |
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324 out = call(out, (char *)m68k_read_long_scratch1); |
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325 break; |
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326 } |
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327 out = pop_r(out, SCRATCH2); |
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328 ea->mode = MODE_REG_DIRECT; |
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329 ea->base = SCRATCH1; |
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330 break; |
61
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331 case MODE_ABSOLUTE: |
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332 case MODE_ABSOLUTE_SHORT: |
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333 //Add cycles for reading address from instruction stream |
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334 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
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335 out = cycles(out, BUS*2); |
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336 } else { |
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337 out = cycles(out, BUS); |
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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338 } |
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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339 out = mov_ir(out, inst->dst.params.immed, SCRATCH1, SZ_D); |
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340 out = push_r(out, SCRATCH1); |
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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341 switch (inst->extra.size) |
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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342 { |
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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343 case OPSIZE_BYTE: |
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344 out = call(out, (char *)m68k_read_byte_scratch1); |
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345 break; |
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346 case OPSIZE_WORD: |
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347 out = call(out, (char *)m68k_read_word_scratch1); |
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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348 break; |
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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349 case OPSIZE_LONG: |
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350 out = call(out, (char *)m68k_read_long_scratch1); |
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351 break; |
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352 } |
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353 out = pop_r(out, SCRATCH2); |
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354 ea->mode = MODE_REG_DIRECT; |
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355 ea->base = SCRATCH1; |
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356 break; |
18
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357 default: |
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358 printf("address mode %d not implemented (dst)\n", inst->dst.addr_mode); |
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359 exit(1); |
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360 } |
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361 return out; |
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362 } |
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363 |
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364 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts) |
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365 { |
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366 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
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367 switch (inst->extra.size) |
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368 { |
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369 case OPSIZE_BYTE: |
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370 out = call(out, (char *)m68k_write_byte); |
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371 break; |
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372 case OPSIZE_WORD: |
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373 out = call(out, (char *)m68k_write_word); |
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374 break; |
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375 case OPSIZE_LONG: |
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376 out = call(out, (char *)m68k_write_long_lowfirst); |
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377 break; |
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378 } |
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379 } |
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380 return out; |
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381 } |
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382 |
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383 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address) |
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384 { |
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385 address &= 0xFFFFFF; |
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386 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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387 if (!native_code_map[chunk].base) { |
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388 return NULL; |
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389 } |
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390 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
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391 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
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392 return NULL; |
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393 } |
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394 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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395 } |
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396 |
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|
397 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest) |
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398 { |
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|
399 deferred_addr * new_head = malloc(sizeof(deferred_addr)); |
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|
400 new_head->next = old_head; |
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|
401 new_head->address = address & 0xFFFFFF; |
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|
402 new_head->dest = dest; |
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|
403 return new_head; |
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|
404 } |
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changeset
|
405 |
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|
406 void process_deferred(x86_68k_options * opts) |
3e7bfde7606e
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|
407 { |
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|
408 deferred_addr * cur = opts->deferred; |
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|
409 deferred_addr **last_next = &(opts->deferred); |
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|
410 while(cur) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
411 { |
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|
412 uint8_t * native = get_native_address(opts->native_code_map, cur->address); |
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|
413 if (native) { |
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|
414 int32_t disp = native - (cur->dest + 4); |
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|
415 printf("Native dest: %p, Offset address: %p, displacement: %X\n", native, cur->dest, disp); |
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|
416 uint8_t * out = cur->dest; |
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|
417 *(out++) = disp; |
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|
418 disp >>= 8; |
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|
419 *(out++) = disp; |
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|
420 disp >>= 8; |
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|
421 *(out++) = disp; |
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|
422 disp >>= 8; |
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|
423 *out = disp; |
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|
424 *last_next = cur->next; |
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changeset
|
425 free(cur); |
3e7bfde7606e
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|
426 cur = *last_next; |
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|
427 } else { |
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changeset
|
428 last_next = &(cur->next); |
3e7bfde7606e
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|
429 cur = cur->next; |
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|
430 } |
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|
431 } |
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|
432 } |
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|
433 |
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|
434 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr) |
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|
435 { |
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|
436 //FIXME: This probably isn't going to work with real code in a lot of cases, no guarantee that |
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|
437 //all the code in 1KB block is going to be translated at the same time |
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|
438 address &= 0xFFFFFF; |
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|
439 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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changeset
|
440 if (!native_code_map[chunk].base) { |
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|
441 native_code_map[chunk].base = native_addr; |
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|
442 native_code_map[chunk].offsets = malloc(sizeof(uint16_t) * NATIVE_CHUNK_SIZE); |
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|
443 memset(native_code_map[chunk].offsets, 0xFF, sizeof(uint16_t) * NATIVE_CHUNK_SIZE); |
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14
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|
444 } |
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14
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|
445 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
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14
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|
446 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base; |
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14
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|
447 } |
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14
diff
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|
448 |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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changeset
|
449 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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14
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|
450 { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
451 int8_t reg, flags_reg; |
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|
452 uint8_t dir = 0; |
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14
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|
453 int32_t offset; |
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14
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|
454 int32_t inc_amount, dec_amount; |
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14
diff
changeset
|
455 x86_ea src; |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
456 dst = translate_m68k_src(inst, &src, dst, opts); |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
457 reg = native_reg(&(inst->dst), opts); |
54
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Get Flavio's color bar demo kind of sort of working
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53
diff
changeset
|
458 //update statically set flags |
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53
diff
changeset
|
459 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
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53
diff
changeset
|
460 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
3b79cbcf6846
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53
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|
461 |
18
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14
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changeset
|
462 if (src.mode == MODE_REG_DIRECT) { |
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14
diff
changeset
|
463 flags_reg = src.base; |
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14
diff
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|
464 } else { |
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14
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changeset
|
465 if (reg >= 0) { |
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14
diff
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|
466 flags_reg = reg; |
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14
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|
467 } else { |
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14
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|
468 printf("moving %d to temp register %d\n", src.disp, SCRATCH1); |
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14
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|
469 dst = mov_ir(dst, src.disp, SCRATCH1, SZ_D); |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
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|
470 src.mode = MODE_REG_DIRECT; |
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14
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|
471 flags_reg = src.base = SCRATCH1; |
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14
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|
472 } |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
473 } |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
474 switch(inst->dst.addr_mode) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
475 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
476 case MODE_REG: |
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14
diff
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|
477 case MODE_AREG: |
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parents:
14
diff
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|
478 if (reg >= 0) { |
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14
diff
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|
479 if (src.mode == MODE_REG_DIRECT) { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
480 dst = mov_rr(dst, src.base, reg, inst->extra.size); |
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14
diff
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|
481 } else if (src.mode == MODE_REG_DISPLACE8) { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
482 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size); |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
483 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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14
diff
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|
484 dst = mov_ir(dst, src.disp, reg, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
485 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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14
diff
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|
486 } else if(src.mode == MODE_REG_DIRECT) { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
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parents:
51
diff
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|
487 printf("mov_rrdisp8 from reg %d to offset %d from reg %d (%d)\n", src.base, (int)reg_offset(&(inst->dst)), CONTEXT, inst->dst.params.regs.pri); |
f02ba3808757
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51
diff
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|
488 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); |
18
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diff
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|
489 } else { |
52
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51
diff
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|
490 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); |
18
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14
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|
491 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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53
diff
changeset
|
492 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
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Get Flavio's color bar demo kind of sort of working
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diff
changeset
|
493 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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Get Flavio's color bar demo kind of sort of working
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53
diff
changeset
|
494 dst = setcc_r(dst, CC_S, FLAG_N); |
14
2bdad0f52f42
x86 code gen, initial work on translator
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diff
changeset
|
495 break; |
18
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14
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|
496 case MODE_AREG_PREDEC: |
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14
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|
497 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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14
diff
changeset
|
498 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
499 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
500 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
501 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
502 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
503 case MODE_AREG_INDIRECT: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
504 case MODE_AREG_POSTINC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
505 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
506 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
507 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
508 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
509 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
510 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
511 if (src.base != SCRATCH1) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
512 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
513 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
514 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
515 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
516 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
517 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
518 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
519 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
520 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
521 dst = setcc_r(dst, CC_S, FLAG_N); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
522 switch (inst->extra.size) |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
523 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
524 case OPSIZE_BYTE: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
525 dst = call(dst, (char *)m68k_write_byte); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
526 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
527 case OPSIZE_WORD: |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
528 dst = call(dst, (char *)m68k_write_word); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
529 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
530 case OPSIZE_LONG: |
3e7bfde7606e
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parents:
14
diff
changeset
|
531 dst = call(dst, (char *)m68k_write_long_highfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
532 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
533 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
534 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
535 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
536 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
537 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
538 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
539 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
540 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
541 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
543 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
544 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
545 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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546 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
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diff
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547 } else { |
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diff
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548 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
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549 } |
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|
550 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
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diff
changeset
|
551 if (src.mode == MODE_REG_DIRECT) { |
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70
diff
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552 if (src.base != SCRATCH1) { |
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Mike Pavone <pavone@retrodev.com>
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70
diff
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|
553 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
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Mike Pavone <pavone@retrodev.com>
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diff
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554 } |
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diff
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|
555 } else if (src.mode == MODE_REG_DISPLACE8) { |
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diff
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|
556 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
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diff
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557 } else { |
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diff
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558 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
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559 } |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
560 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
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diff
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|
561 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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diff
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|
562 dst = setcc_r(dst, CC_S, FLAG_N); |
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70
diff
changeset
|
563 switch (inst->extra.size) |
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diff
changeset
|
564 { |
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diff
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|
565 case OPSIZE_BYTE: |
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|
566 dst = call(dst, (char *)m68k_write_byte); |
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diff
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567 break; |
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diff
changeset
|
568 case OPSIZE_WORD: |
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diff
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569 dst = call(dst, (char *)m68k_write_word); |
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diff
changeset
|
570 break; |
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|
571 case OPSIZE_LONG: |
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|
572 dst = call(dst, (char *)m68k_write_long_highfirst); |
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diff
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|
573 break; |
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|
574 } |
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575 break; |
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576 case MODE_PC_DISPLACE: |
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|
577 dst = cycles(dst, BUS); |
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578 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address, SCRATCH2, SZ_D); |
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579 if (src.mode == MODE_REG_DIRECT) { |
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diff
changeset
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580 if (src.base != SCRATCH1) { |
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|
581 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
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diff
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582 } |
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diff
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583 } else if (src.mode == MODE_REG_DISPLACE8) { |
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diff
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584 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
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70
diff
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585 } else { |
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586 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
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diff
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|
587 } |
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588 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
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589 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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diff
changeset
|
590 dst = setcc_r(dst, CC_S, FLAG_N); |
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diff
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|
591 switch (inst->extra.size) |
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|
592 { |
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diff
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|
593 case OPSIZE_BYTE: |
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changeset
|
594 dst = call(dst, (char *)m68k_write_byte); |
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diff
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|
595 break; |
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diff
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596 case OPSIZE_WORD: |
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|
597 dst = call(dst, (char *)m68k_write_word); |
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diff
changeset
|
598 break; |
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diff
changeset
|
599 case OPSIZE_LONG: |
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diff
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|
600 dst = call(dst, (char *)m68k_write_long_highfirst); |
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diff
changeset
|
601 break; |
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diff
changeset
|
602 } |
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diff
changeset
|
603 break; |
54
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53
diff
changeset
|
604 case MODE_ABSOLUTE: |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
605 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
606 if (src.mode == MODE_REG_DIRECT) { |
3b79cbcf6846
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diff
changeset
|
607 if (src.base != SCRATCH1) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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53
diff
changeset
|
608 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3b79cbcf6846
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53
diff
changeset
|
609 } |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
610 } else if (src.mode == MODE_REG_DISPLACE8) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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53
diff
changeset
|
611 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
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diff
changeset
|
612 } else { |
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diff
changeset
|
613 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
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53
diff
changeset
|
614 } |
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diff
changeset
|
615 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
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53
diff
changeset
|
616 dst = cycles(dst, BUS*2); |
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diff
changeset
|
617 } else { |
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53
diff
changeset
|
618 dst = cycles(dst, BUS); |
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diff
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|
619 } |
3b79cbcf6846
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53
diff
changeset
|
620 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
3b79cbcf6846
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53
diff
changeset
|
621 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
3b79cbcf6846
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53
diff
changeset
|
622 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b79cbcf6846
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diff
changeset
|
623 dst = setcc_r(dst, CC_S, FLAG_N); |
3b79cbcf6846
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53
diff
changeset
|
624 switch (inst->extra.size) |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
625 { |
3b79cbcf6846
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53
diff
changeset
|
626 case OPSIZE_BYTE: |
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53
diff
changeset
|
627 dst = call(dst, (char *)m68k_write_byte); |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
628 break; |
3b79cbcf6846
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53
diff
changeset
|
629 case OPSIZE_WORD: |
3b79cbcf6846
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53
diff
changeset
|
630 dst = call(dst, (char *)m68k_write_word); |
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
631 break; |
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53
diff
changeset
|
632 case OPSIZE_LONG: |
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parents:
53
diff
changeset
|
633 dst = call(dst, (char *)m68k_write_long_highfirst); |
3b79cbcf6846
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parents:
53
diff
changeset
|
634 break; |
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53
diff
changeset
|
635 } |
3b79cbcf6846
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parents:
53
diff
changeset
|
636 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
637 default: |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
changeset
|
638 printf("address mode %d not implemented (move dst)\n", inst->dst.addr_mode); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
639 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
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parents:
diff
changeset
|
640 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
641 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
642 //add cycles for prefetch |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
643 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
644 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
645 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
646 |
71
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70
diff
changeset
|
647 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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70
diff
changeset
|
648 { |
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diff
changeset
|
649 int8_t bit,reg; |
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70
diff
changeset
|
650 uint8_t early_cycles; |
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|
651 if(inst->src.addr_mode == MODE_REG) { |
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diff
changeset
|
652 //reg to mem |
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diff
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|
653 early_cycles = 8; |
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diff
changeset
|
654 int8_t dir; |
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|
655 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
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diff
changeset
|
656 reg = 15; |
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changeset
|
657 dir = -1; |
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diff
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|
658 } else { |
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changeset
|
659 reg = 0; |
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|
660 } |
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diff
changeset
|
661 switch (inst->dst.addr_mode) |
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changeset
|
662 { |
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diff
changeset
|
663 case MODE_AREG_INDIRECT: |
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diff
changeset
|
664 case MODE_AREG_PREDEC: |
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diff
changeset
|
665 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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666 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
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667 } else { |
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668 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
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669 } |
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670 break; |
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671 case MODE_ABSOLUTE: |
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672 early_cycles += 4; |
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673 case MODE_ABSOLUTE_SHORT: |
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674 early_cycles += 4; |
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675 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
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676 break; |
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677 default: |
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678 printf("address mode %d not implemented (movem dst)\n", inst->dst.addr_mode); |
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679 exit(1); |
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680 } |
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681 dst = cycles(dst, early_cycles); |
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682 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) { |
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683 if (inst->src.params.immed & (1 << bit)) { |
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684 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
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685 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
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686 } |
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687 dst = push_r(dst, SCRATCH2); |
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|
688 if (reg > 7) { |
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689 if (opts->aregs[reg-8] >= 0) { |
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690 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size); |
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691 } else { |
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692 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size); |
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693 } |
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694 } else { |
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695 if (opts->dregs[reg] >= 0) { |
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696 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size); |
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697 } else { |
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698 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size); |
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699 } |
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700 } |
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701 if (inst->extra.size == OPSIZE_LONG) { |
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702 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst); |
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diff
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703 } else { |
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704 dst = call(dst, (uint8_t *)m68k_write_word); |
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diff
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705 } |
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diff
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706 dst = pop_r(dst, SCRATCH2); |
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707 if (inst->dst.addr_mode != MODE_AREG_PREDEC) { |
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708 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
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709 } |
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|
710 } |
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|
711 } |
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|
712 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
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713 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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diff
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714 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
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|
715 } else { |
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|
716 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
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diff
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|
717 } |
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diff
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|
718 } |
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diff
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|
719 } else { |
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diff
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|
720 //mem to reg |
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70
diff
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|
721 early_cycles = 4; |
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70
diff
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|
722 switch (inst->src.addr_mode) |
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diff
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|
723 { |
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diff
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|
724 case MODE_AREG_INDIRECT: |
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diff
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|
725 case MODE_AREG_POSTINC: |
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diff
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|
726 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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diff
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|
727 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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diff
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|
728 } else { |
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70
diff
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|
729 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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diff
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|
730 } |
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diff
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|
731 break; |
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70
diff
changeset
|
732 case MODE_ABSOLUTE: |
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70
diff
changeset
|
733 early_cycles += 4; |
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70
diff
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|
734 case MODE_ABSOLUTE_SHORT: |
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diff
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|
735 early_cycles += 4; |
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diff
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|
736 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
f80fa1776507
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70
diff
changeset
|
737 break; |
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diff
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|
738 default: |
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70
diff
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|
739 printf("address mode %d not implemented (movem src)\n", inst->src.addr_mode); |
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70
diff
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|
740 exit(1); |
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70
diff
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|
741 } |
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diff
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|
742 dst = cycles(dst, early_cycles); |
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70
diff
changeset
|
743 for(reg = 0; reg < 16; reg ++) { |
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70
diff
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|
744 if (inst->src.params.immed & (1 << reg)) { |
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70
diff
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|
745 dst = push_r(dst, SCRATCH1); |
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70
diff
changeset
|
746 if (inst->extra.size == OPSIZE_LONG) { |
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diff
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|
747 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
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70
diff
changeset
|
748 } else { |
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70
diff
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|
749 dst = call(dst, (uint8_t *)m68k_read_word_scratch1); |
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70
diff
changeset
|
750 } |
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70
diff
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|
751 if (reg > 7) { |
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70
diff
changeset
|
752 if (opts->aregs[reg-8] >= 0) { |
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70
diff
changeset
|
753 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size); |
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70
diff
changeset
|
754 } else { |
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70
diff
changeset
|
755 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size); |
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70
diff
changeset
|
756 } |
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70
diff
changeset
|
757 } else { |
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70
diff
changeset
|
758 if (opts->dregs[reg] >= 0) { |
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70
diff
changeset
|
759 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size); |
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70
diff
changeset
|
760 } else { |
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70
diff
changeset
|
761 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size); |
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70
diff
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|
762 } |
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diff
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|
763 } |
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diff
changeset
|
764 dst = pop_r(dst, SCRATCH1); |
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diff
changeset
|
765 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D); |
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70
diff
changeset
|
766 } |
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70
diff
changeset
|
767 } |
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70
diff
changeset
|
768 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
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70
diff
changeset
|
769 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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70
diff
changeset
|
770 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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70
diff
changeset
|
771 } else { |
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70
diff
changeset
|
772 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
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70
diff
changeset
|
773 } |
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diff
changeset
|
774 } |
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70
diff
changeset
|
775 } |
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diff
changeset
|
776 //prefetch |
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70
diff
changeset
|
777 dst = cycles(dst, 4); |
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diff
changeset
|
778 return dst; |
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70
diff
changeset
|
779 } |
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diff
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|
780 |
52
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51
diff
changeset
|
781 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
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51
diff
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|
782 { |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
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51
diff
changeset
|
783 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
784 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
785 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
786 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
787 uint8_t reg = native_reg(&(inst->dst), opts); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
788 if (reg >= 0) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
789 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
790 return xor_rr(dst, reg, reg, inst->extra.size); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
791 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
792 int32_t dec_amount,inc_amount; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
793 switch (inst->dst.addr_mode) |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
794 { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
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parents:
51
diff
changeset
|
795 case MODE_REG: |
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Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
796 case MODE_AREG: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
797 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
798 dst = mov_irdisp8(dst, 0, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
799 break; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
800 case MODE_AREG_PREDEC: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
801 dst = cycles(dst, PREDEC_PENALTY); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
802 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
803 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
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51
diff
changeset
|
804 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
805 } else { |
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Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
806 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
807 } |
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
808 case MODE_AREG_INDIRECT: |
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Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
809 case MODE_AREG_POSTINC: |
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Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
810 //add cycles for prefetch and wasted read |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
811 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 12 : 8)); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
812 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
813 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
814 } else { |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
815 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
816 } |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
817 dst = xor_rr(dst, SCRATCH1, SCRATCH1, SZ_D); |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
818 switch (inst->extra.size) |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
819 { |
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
820 case OPSIZE_BYTE: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
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51
diff
changeset
|
821 dst = call(dst, (char *)m68k_write_byte); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
822 break; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
823 case OPSIZE_WORD: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
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51
diff
changeset
|
824 dst = call(dst, (char *)m68k_write_word); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
825 break; |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
826 case OPSIZE_LONG: |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
827 dst = call(dst, (char *)m68k_write_long_highfirst); |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
828 break; |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
829 } |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
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51
diff
changeset
|
830 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
f02ba3808757
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parents:
51
diff
changeset
|
831 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
f02ba3808757
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parents:
51
diff
changeset
|
832 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f02ba3808757
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51
diff
changeset
|
833 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
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51
diff
changeset
|
834 } else { |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
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51
diff
changeset
|
835 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
836 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
837 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
838 break; |
71
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70
diff
changeset
|
839 default: |
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diff
changeset
|
840 printf("address mode %d not implemented (clr dst)\n", inst->dst.addr_mode); |
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diff
changeset
|
841 exit(1); |
52
f02ba3808757
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51
diff
changeset
|
842 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
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parents:
51
diff
changeset
|
843 return dst; |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
844 } |
f02ba3808757
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Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
845 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
846 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
847 { |
71
f80fa1776507
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70
diff
changeset
|
848 int8_t dst_reg = native_reg(&(inst->dst), opts); |
f80fa1776507
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70
diff
changeset
|
849 switch(inst->src.addr_mode) |
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
850 { |
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70
diff
changeset
|
851 case MODE_AREG_INDIRECT: |
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70
diff
changeset
|
852 dst = cycles(dst, BUS); |
f80fa1776507
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70
diff
changeset
|
853 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
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70
diff
changeset
|
854 if (dst_reg >= 0) { |
f80fa1776507
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70
diff
changeset
|
855 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
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70
diff
changeset
|
856 } else { |
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70
diff
changeset
|
857 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
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70
diff
changeset
|
858 } |
f80fa1776507
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70
diff
changeset
|
859 } else { |
f80fa1776507
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70
diff
changeset
|
860 if (dst_reg >= 0) { |
f80fa1776507
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70
diff
changeset
|
861 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D); |
f80fa1776507
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diff
changeset
|
862 } else { |
f80fa1776507
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70
diff
changeset
|
863 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
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Implement more instructions and address modes
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70
diff
changeset
|
864 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
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70
diff
changeset
|
865 } |
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parents:
70
diff
changeset
|
866 } |
f80fa1776507
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70
diff
changeset
|
867 break; |
f80fa1776507
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70
diff
changeset
|
868 case MODE_AREG_DISPLACE: |
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parents:
70
diff
changeset
|
869 dst = cycles(dst, 8); |
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parents:
70
diff
changeset
|
870 if (dst_reg >= 0) { |
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70
diff
changeset
|
871 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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70
diff
changeset
|
872 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
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70
diff
changeset
|
873 } else { |
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diff
changeset
|
874 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); |
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parents:
70
diff
changeset
|
875 } |
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70
diff
changeset
|
876 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); |
f80fa1776507
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70
diff
changeset
|
877 } else { |
f80fa1776507
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diff
changeset
|
878 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
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70
diff
changeset
|
879 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
880 } else { |
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Mike Pavone <pavone@retrodev.com>
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70
diff
changeset
|
881 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
f80fa1776507
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70
diff
changeset
|
882 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
883 } |
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parents:
70
diff
changeset
|
884 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
f80fa1776507
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70
diff
changeset
|
885 } |
f80fa1776507
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70
diff
changeset
|
886 break; |
f80fa1776507
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diff
changeset
|
887 case MODE_PC_DISPLACE: |
f80fa1776507
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70
diff
changeset
|
888 dst = cycles(dst, 8); |
f80fa1776507
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70
diff
changeset
|
889 if (dst_reg >= 0) { |
f80fa1776507
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70
diff
changeset
|
890 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address, dst_reg, SZ_D); |
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
891 } else { |
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70
diff
changeset
|
892 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
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70
diff
changeset
|
893 } |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
894 break; |
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70
diff
changeset
|
895 case MODE_ABSOLUTE: |
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70
diff
changeset
|
896 case MODE_ABSOLUTE_SHORT: |
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70
diff
changeset
|
897 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
898 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
899 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
900 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
901 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
902 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
903 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
904 default: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
905 printf("address mode %d not implemented (lea src)\n", inst->src.addr_mode); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
906 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
907 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
908 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
909 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
910 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
911 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
912 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
913 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
914 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
915 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
916 dst = mov_ir(dst, after, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
917 dst = push_r(dst, SCRATCH1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
918 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
919 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
920 dst = call(dst, (char *)m68k_write_long_highfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
921 printf("bsr@%X: after=%X, disp=%X, dest=%X\n", inst->address, after, disp, after+disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
922 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
923 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
924 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
925 //dummy address to be replaced later |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
926 dest_addr = dst + 5; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
927 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
928 dst = call(dst, (char *)dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
929 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
930 dst = pop_r(dst, SCRATCH1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
931 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
932 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
933 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
934 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
935 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
936 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
937 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
938 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
939 printf("bcc@%X: after=%X, disp=%X, dest=%X\n", inst->address, after, disp, after+disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
940 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
941 if (inst->extra.cond == COND_TRUE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
942 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
943 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
944 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
945 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
946 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
947 dst = jmp(dst, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
948 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
949 uint8_t cond = CC_NZ; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
950 switch (inst->extra.cond) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
951 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
952 case COND_HIGH: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
953 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
954 case COND_LOW_SAME: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
955 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
956 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
957 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
958 case COND_CARRY_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
959 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
960 case COND_CARRY_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
961 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
962 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
963 case COND_NOT_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
964 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
965 case COND_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
966 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
967 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
968 case COND_OVERF_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
969 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
970 case COND_OVERF_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
971 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
972 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
973 case COND_PLUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
974 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
975 case COND_MINUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
976 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
977 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
978 case COND_GREATER_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
979 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
980 case COND_LESS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
981 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
982 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
983 case COND_GREATER: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
984 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
985 case COND_LESS_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
986 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
987 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
988 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
989 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
990 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
991 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
992 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
993 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
994 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
995 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
996 dst = jcc(dst, cond, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
997 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
998 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
999 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1000 |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1001 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1002 { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1003 uint8_t * dest_addr; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1004 switch(inst->src.addr_mode) |
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70
diff
changeset
|
1005 { |
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diff
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|
1006 case MODE_AREG_INDIRECT: |
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70
diff
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|
1007 dst = cycles(dst, BUS); |
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70
diff
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|
1008 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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70
diff
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|
1009 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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70
diff
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|
1010 } else { |
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diff
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|
1011 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
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70
diff
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|
1012 } |
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70
diff
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|
1013 dst = call(dst, (uint8_t *)m68k_native_addr); |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
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|
1014 //TODO: Finish me |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
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|
1015 //TODO: Fix timing |
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Mike Pavone <pavone@retrodev.com>
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70
diff
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|
1016 break; |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
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|
1017 case MODE_ABSOLUTE: |
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Mike Pavone <pavone@retrodev.com>
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70
diff
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|
1018 case MODE_ABSOLUTE_SHORT: |
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Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
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70
diff
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|
1019 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
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Implement more instructions and address modes
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70
diff
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|
1020 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed); |
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70
diff
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|
1021 if (!dest_addr) { |
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70
diff
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|
1022 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1023 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1024 dest_addr = dst + 256; |
71
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parents:
70
diff
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|
1025 } |
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Mike Pavone <pavone@retrodev.com>
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70
diff
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|
1026 dst = jmp(dst, dest_addr); |
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1027 break; |
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70
diff
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|
1028 } |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1029 return dst; |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1030 } |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1031 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1032 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1033 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1034 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1035 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1036 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1037 dst = call(dst, (char *)m68k_read_long_scratch1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1038 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1039 dst = jcc(dst, CC_NZ, dst+3); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1040 dst = retn(dst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1041 dst = jmp(dst, (char *)m68k_modified_ret_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1042 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
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19
diff
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|
1045 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1046 { |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1047 //best case duration |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1048 dst = cycles(dst, 10); |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1049 uint8_t * skip_loc = NULL; |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1050 //TODO: Check if COND_TRUE technically valid here even though |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
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|
1051 //it's basically a slow NOP |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
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|
1052 if (inst->extra.cond != COND_FALSE) { |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
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|
1053 uint8_t cond = CC_NZ; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1054 switch (inst->extra.cond) |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1055 { |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1056 case COND_HIGH: |
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Mike Pavone <pavone@retrodev.com>
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19
diff
changeset
|
1057 cond = CC_Z; |
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parents:
19
diff
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|
1058 case COND_LOW_SAME: |
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parents:
19
diff
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|
1059 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1060 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
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Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1061 break; |
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Mike Pavone <pavone@retrodev.com>
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19
diff
changeset
|
1062 case COND_CARRY_CLR: |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1063 cond = CC_Z; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1064 case COND_CARRY_SET: |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1065 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1066 break; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1067 case COND_NOT_EQ: |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1068 cond = CC_Z; |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1069 case COND_EQ: |
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Mike Pavone <pavone@retrodev.com>
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19
diff
changeset
|
1070 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1071 break; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1072 case COND_OVERF_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1073 cond = CC_Z; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1074 case COND_OVERF_SET: |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1075 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1076 break; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1077 case COND_PLUS: |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1078 cond = CC_Z; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1079 case COND_MINUS: |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1080 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
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parents:
19
diff
changeset
|
1081 break; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1082 case COND_GREATER_EQ: |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1083 cond = CC_Z; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1084 case COND_LESS: |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1085 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
f2aaaf36c875
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parents:
19
diff
changeset
|
1086 break; |
f2aaaf36c875
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parents:
19
diff
changeset
|
1087 case COND_GREATER: |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1088 cond = CC_Z; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1089 case COND_LESS_EQ: |
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parents:
19
diff
changeset
|
1090 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
f2aaaf36c875
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parents:
19
diff
changeset
|
1091 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1092 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1093 break; |
f2aaaf36c875
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parents:
19
diff
changeset
|
1094 } |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1095 skip_loc = dst + 1; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1096 dst = jcc(dst, cond, dst + 2); |
f2aaaf36c875
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parents:
19
diff
changeset
|
1097 } |
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parents:
19
diff
changeset
|
1098 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
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parents:
19
diff
changeset
|
1099 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
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19
diff
changeset
|
1100 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
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19
diff
changeset
|
1101 } else { |
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parents:
19
diff
changeset
|
1102 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
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parents:
19
diff
changeset
|
1103 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
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parents:
19
diff
changeset
|
1104 } |
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parents:
19
diff
changeset
|
1105 uint8_t *loop_end_loc = dst+1; |
f2aaaf36c875
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parents:
19
diff
changeset
|
1106 dst = jcc(dst, CC_Z, dst+2); |
f2aaaf36c875
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parents:
19
diff
changeset
|
1107 uint32_t after = inst->address + 2; |
f2aaaf36c875
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parents:
19
diff
changeset
|
1108 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed); |
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parents:
19
diff
changeset
|
1109 if (!dest_addr) { |
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19
diff
changeset
|
1110 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1); |
f2aaaf36c875
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parents:
19
diff
changeset
|
1111 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
f2aaaf36c875
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parents:
19
diff
changeset
|
1112 dest_addr = dst + 256; |
f2aaaf36c875
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1113 } |
f2aaaf36c875
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parents:
19
diff
changeset
|
1114 dst = jmp(dst, dest_addr); |
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parents:
19
diff
changeset
|
1115 *loop_end_loc = dst - (loop_end_loc+1); |
f2aaaf36c875
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parents:
19
diff
changeset
|
1116 if (skip_loc) { |
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Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1117 dst = cycles(dst, 2); |
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parents:
19
diff
changeset
|
1118 *skip_loc = dst - (skip_loc+1); |
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19
diff
changeset
|
1119 dst = cycles(dst, 2); |
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19
diff
changeset
|
1120 } else { |
f2aaaf36c875
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19
diff
changeset
|
1121 dst = cycles(dst, 4); |
f2aaaf36c875
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19
diff
changeset
|
1122 } |
52
f02ba3808757
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parents:
51
diff
changeset
|
1123 return dst; |
46
f2aaaf36c875
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19
diff
changeset
|
1124 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1125 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1126 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1127 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1128 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1129 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1130 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1131 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1132 { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1133 uint8_t * end_off = NULL; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1134 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1135 dst = cycles(dst, BUS); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1136 //Memory shift |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1137 dst = shift_ir(dst, 1, dst_op->base, SZ_W); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1138 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1139 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1140 if (src_op->mode == MODE_IMMED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1141 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1142 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1143 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1144 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1145 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1146 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1147 if (src_op->base != RCX) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1148 if (src_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1149 dst = mov_rr(dst, src_op->base, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1150 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1151 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1152 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1153 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1154 dst = and_ir(dst, 63, RCX, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1155 //add 2 cycles for every bit shifted |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1156 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1157 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1158 //x86 shifts modulo 32 for operand sizes less than 64-bits |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1159 //but M68K shifts modulo 64, so we need to check for large shifts here |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1160 dst = cmp_ir(dst, 32, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1161 uint8_t * norm_shift_off = dst + 1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1162 dst = jcc(dst, CC_L, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1163 if (special) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1164 if (inst->extra.size == OPSIZE_LONG) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1165 uint8_t * neq_32_off = dst + 1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1166 dst = jcc(dst, CC_NZ, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1167 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1168 //set the carry bit to the lsb |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1169 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1170 dst = special(dst, 1, dst_op->base, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1171 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1172 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1173 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1174 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1175 dst = jmp(dst, dst+4); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1176 *neq_32_off = dst - (neq_32_off+1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1177 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1178 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1179 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1180 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1181 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1182 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1183 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1184 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1185 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1186 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1187 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1188 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1189 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1190 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1191 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1192 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1193 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1194 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1195 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1196 end_off = dst+1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1197 dst = jmp(dst, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1198 *norm_shift_off = dst - (norm_shift_off+1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1199 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1200 dst = shift_clr(dst, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1201 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1202 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1203 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1204 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1205 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1206 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1207 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1208 if (!special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1209 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1210 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1211 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1212 dst = setcc_r(dst, CC_Z, FLAG_Z); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1213 dst = setcc_r(dst, CC_S, FLAG_N); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1214 if (special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1215 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1216 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1217 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1218 //set X flag to same as C flag |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1219 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1220 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1221 dst = m68k_save_result(inst, dst, opts); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1222 } |
66 | 1223 return dst; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1224 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1225 |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1226 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1227 { |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1228 uint8_t * end_off; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1229 map_native_address(opts->native_code_map, inst->address, dst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1230 if (inst->op == M68K_MOVE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1231 return translate_m68k_move(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1232 } else if(inst->op == M68K_LEA) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1233 return translate_m68k_lea(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1234 } else if(inst->op == M68K_BSR) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1235 return translate_m68k_bsr(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1236 } else if(inst->op == M68K_BCC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1237 return translate_m68k_bcc(dst, inst, opts); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1238 } else if(inst->op == M68K_JMP) { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1239 return translate_m68k_jmp(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1240 } else if(inst->op == M68K_RTS) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1241 return translate_m68k_rts(dst, inst, opts); |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1242 } else if(inst->op == M68K_DBCC) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1243 return translate_m68k_dbcc(dst, inst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1244 } else if(inst->op == M68K_CLR) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1245 return translate_m68k_clr(dst, inst, opts); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1246 } else if(inst->op == M68K_MOVEM) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1247 return translate_m68k_movem(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1248 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1249 x86_ea src_op, dst_op; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1250 if (inst->src.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1251 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1252 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1253 if (inst->dst.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1254 dst = translate_m68k_dst(inst, &dst_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1255 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1256 switch(inst->op) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1257 { |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1258 //case M68K_ABCD: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1259 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1260 case M68K_ADD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1261 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1262 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1263 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1264 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1265 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1266 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1267 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1268 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1269 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1270 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1271 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1272 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1273 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1274 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1275 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1276 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1277 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1278 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1279 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1280 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1281 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1282 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1283 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1284 //case M68K_ADDX: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1285 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1286 case M68K_AND: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1287 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1288 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1289 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1290 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1291 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1292 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1293 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1294 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1295 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1296 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1297 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1298 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1299 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1300 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1301 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1302 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1303 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1304 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1305 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1306 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1307 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1308 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1309 //case M68K_ANDI_CCR: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1310 //case M68K_ANDI_SR: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1311 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1312 case M68K_ASL: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1313 case M68K_LSL: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1314 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1315 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1316 case M68K_ASR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1317 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1318 break; |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1319 case M68K_LSR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1320 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1321 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1322 /*case M68K_BCHG: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1323 case M68K_BCLR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1324 case M68K_BSET: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1325 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1326 case M68K_BTST: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1327 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6); |
67 | 1328 if (src_op.mode == MODE_IMMED) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1329 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1330 src_op.disp &= 0x7; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1331 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1332 if (dst_op.mode == MODE_REG_DIRECT) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1333 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1334 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1335 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1336 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1337 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1338 if (src_op.mode == MODE_REG_DISPLACE8) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1339 if (dst_op.base == SCRATCH1) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1340 dst = push_r(dst, SCRATCH2); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1341 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1342 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1343 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1344 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1345 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1346 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1347 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1348 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1349 dst = and_ir(dst, 0x7, src_op.base, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1350 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1351 if (dst_op.mode == MODE_REG_DIRECT) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1352 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1353 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1354 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1355 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1356 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1357 //x86 sets the carry flag to the value of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1358 //68K sets the zero flag to the complement of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1359 dst = setcc_r(dst, CC_NC, FLAG_Z); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1360 if (src_op.base == SCRATCH2) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1361 dst = pop_r(dst, SCRATCH2); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1362 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1363 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1364 /*case M68K_CHK: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1365 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1366 case M68K_CMP: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1367 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1368 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1369 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1370 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1371 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1372 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1373 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1374 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1375 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1376 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1377 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1378 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1379 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1380 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1381 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1382 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1383 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1384 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1385 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1386 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1387 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1388 /*case M68K_DIVS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1389 case M68K_DIVU: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1390 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1391 case M68K_EOR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1392 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1393 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1394 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1395 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1396 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1397 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1398 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1399 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1400 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1401 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1402 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1403 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1404 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1405 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1406 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1407 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1408 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1409 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1410 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1411 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1412 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1413 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1414 /*case M68K_EORI_CCR: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1415 case M68K_EORI_SR:*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1416 case M68K_EXG: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1417 dst = cycles(dst, 6); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1418 if (dst_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1419 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1420 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1421 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1422 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1423 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1424 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1425 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1426 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1427 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1428 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1429 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1430 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1431 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1432 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1433 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1434 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1435 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1436 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1437 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1438 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1439 case M68K_EXT: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1440 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1441 case M68K_ILLEGAL: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1442 dst = call(dst, (uint8_t *)m68k_save_context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1443 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1444 dst = call(dst, (uint8_t *)print_regs_exit); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1445 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1446 /*case M68K_JSR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1447 case M68K_LEA: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1448 case M68K_LINK: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1449 case M68K_MOVE_FROM_SR: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1450 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1451 case M68K_MOVE_CCR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1452 case M68K_MOVE_SR: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1453 //TODO: Privilege check for MOVE to SR |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1454 if (src_op.mode == MODE_IMMED) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1455 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1456 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1457 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1458 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1459 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1460 if (inst->op == M68K_MOVE_SR) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1461 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1462 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1463 dst = cycles(dst, 12); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1464 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1465 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1466 dst = mov_rr(dst, src_op.base, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1467 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1468 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1469 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1470 dst = mov_rr(dst, FLAG_C, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1471 dst = and_ir(dst, 1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1472 dst = shr_ir(dst, 1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1473 dst = mov_rr(dst, FLAG_V, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1474 dst = and_ir(dst, 1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1475 dst = shr_ir(dst, 1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1476 dst = mov_rr(dst, FLAG_Z, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1477 dst = and_ir(dst, 1, FLAG_Z, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1478 dst = shr_ir(dst, 1, FLAG_N, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1479 dst = mov_rr(dst, 1, SCRATCH2, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1480 dst = shr_ir(dst, 1, SCRATCH2, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1481 dst = and_ir(dst, 1, SCRATCH2, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1482 dst = mov_rrind(dst, SCRATCH2, CONTEXT, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1483 dst = cycles(dst, 12); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1484 if (inst->op == M68K_MOVE_SR) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1485 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1486 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_W); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1487 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1488 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1489 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1490 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1491 dst = shr_ir(dst, 8, SCRATCH2, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1492 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, status), SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1493 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1494 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1495 /*case M68K_MOVE_USP: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1496 case M68K_MOVEP: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1497 case M68K_MULS: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1498 case M68K_MULU: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1499 case M68K_NBCD: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1500 case M68K_NEG: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1501 case M68K_NEGX: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1502 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1503 case M68K_NOP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1504 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1505 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1506 case M68K_NOT: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1507 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1508 case M68K_OR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1509 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1510 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1511 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1512 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1513 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1514 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1515 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1516 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1517 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1518 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1519 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1520 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1521 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1522 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1523 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1524 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1525 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1526 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1527 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1528 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1529 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1530 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1531 /*case M68K_ORI_CCR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1532 case M68K_ORI_SR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1533 case M68K_PEA: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1534 case M68K_RESET: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1535 case M68K_ROL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1536 case M68K_ROR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1537 case M68K_ROXL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1538 case M68K_ROXR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1539 case M68K_RTE: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1540 case M68K_RTR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1541 case M68K_SBCD: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1542 case M68K_SCC: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1543 case M68K_STOP: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1544 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1545 case M68K_SUB: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1546 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1547 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1548 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1549 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1550 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1551 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1552 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1553 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1554 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1555 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1556 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1557 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1558 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1559 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1560 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1561 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1562 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1563 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1564 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1565 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1566 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1567 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1568 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1569 //case M68K_SUBX: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1570 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1571 case M68K_SWAP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1572 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1573 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1574 dst = rol_ir(dst, 16, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1575 } else{ |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1576 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1577 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1578 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1579 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1580 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1581 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1582 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1583 /*case M68K_TAS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1584 case M68K_TRAP: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1585 case M68K_TRAPV:*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1586 case M68K_TST: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1587 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
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|
1588 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
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|
1589 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1590 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1591 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
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|
1592 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
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|
1593 dst = setcc_r(dst, CC_C, FLAG_C); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
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|
1594 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
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|
1595 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
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|
1596 dst = setcc_r(dst, CC_O, FLAG_V); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
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|
1597 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
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|
1598 /*case M68K_UNLK: |
14
2bdad0f52f42
x86 code gen, initial work on translator
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parents:
diff
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|
1599 case M68K_INVALID: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
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67
diff
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|
1600 break;*/ |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
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67
diff
changeset
|
1601 default: |
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Make the translator bail out if it hits an instruction I haven't implemented yet
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parents:
67
diff
changeset
|
1602 printf("instruction %d not yet implemented\n", inst->op); |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
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67
diff
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|
1603 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1604 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1605 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1606 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1607 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1608 uint8_t * translate_m68k_stream(uint8_t * dst, uint8_t * dst_end, uint32_t address, m68k_context * context) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1609 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1610 m68kinst instbuf; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
1611 x86_68k_options * opts = context->options; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
1612 char disbuf[1024]; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1613 uint16_t *encoded = context->mem_pointers[0] + address/2, *next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1614 do { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1615 do { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1616 if (dst_end-dst < 128) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1617 puts("out of code memory"); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
1618 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1619 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1620 next = m68k_decode(encoded, &instbuf, address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
1621 address += (next-encoded)*2; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
1622 encoded = next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1623 m68k_disasm(&instbuf, disbuf); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1624 printf("%X: %s\n", instbuf.address, disbuf); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1625 dst = translate_m68k(dst, &instbuf, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1626 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1627 process_deferred(opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1628 if (opts->deferred) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1629 address = opts->deferred->address; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1630 encoded = context->mem_pointers[0] + address/2; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1631 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1632 encoded = NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1633 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1634 } while(encoded != NULL); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1635 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1636 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1637 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1638 void start_68k_context(m68k_context * context, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1639 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1640 uint8_t * addr = get_native_address(context->native_code_map, address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1641 m68k_start_context(addr, context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1642 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1643 |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1644 void m68k_reset(m68k_context * context) |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1645 { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1646 //TODO: Make this actually use the normal read functions |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1647 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1]; |
f80fa1776507
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parents:
70
diff
changeset
|
1648 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3]; |
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Implement more instructions and address modes
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70
diff
changeset
|
1649 start_68k_context(context, address); |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1650 } |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1651 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1652 void init_x86_68k_opts(x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1653 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1654 opts->flags = 0; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1655 for (int i = 0; i < 8; i++) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1656 opts->dregs[i] = opts->aregs[i] = -1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1657 opts->dregs[0] = R10; |
3e7bfde7606e
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parents:
14
diff
changeset
|
1658 opts->dregs[1] = R11; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1659 opts->dregs[2] = R12; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1660 opts->aregs[0] = R13; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1661 opts->aregs[1] = R14; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1662 opts->aregs[7] = R15; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1663 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
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parents:
14
diff
changeset
|
1664 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1665 opts->deferred = NULL; |
3e7bfde7606e
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parents:
14
diff
changeset
|
1666 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1667 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1668 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1669 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1670 memset(context, 0, sizeof(m68k_context)); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1671 context->native_code_map = native_code_map; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1672 context->options = opts; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1673 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1674 |