repos/blastem: z80.cpu annotate

annotate z80.cpu @ 1719:fb5ae8c20b85

Fix cp instruction in new Z80 core and implement its DD/FD prefixes

author	Michael Pavone <pavone@retrodev.com>
date	Wed, 30 Jan 2019 21:47:35 -0800
parents	c7d18b8ec29a
children	1648c685083a

rev	line source
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 info
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2 prefix z80_
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	3 opcode_size 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	4 extra_tables cb ed dded fded dd fd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	5 body z80_run_op
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	6 include z80_util.c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	7 header z80.h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	9 regs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	10 main 8 b c d e h l f a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	11 alt 8 b' c' d' e' h' l' f' a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	12 i 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	13 r 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	14 iff1 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	15 iff2 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	16 imode 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	17 sp 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	18 ix 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	19 iy 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	20 pc 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	21 wz 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	22 nflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	23 last_flag_result 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	24 pvflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	25 chflags 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	26 zflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	27 scratch1 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	28 scratch2 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	29
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	30 flags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	31 register f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	32 S 7 sign last_flag_result.7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	33 Z 6 zero zflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	34 Y 5 bit-5 last_flag_result.5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	35 H 4 half-carry chflags.3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	36 P 2 parity pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	37 V 2 overflow pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	38 X 3 bit-3 last_flag_result.3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	39 N 1 none nflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	40 C 0 carry chflags.7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	41
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	42
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	43 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	44 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	45 add 1 r r
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	46 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	47 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	48 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	49
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	50 z80_run_op
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	51 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	52 dispatch scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	53
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	54 11001011 cb_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	55 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	56 dispatch scratch1 cb
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	57
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	58 11011101 dd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	59 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	60 dispatch scratch1 dd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	61
1712 0a9a88b3d061 Fix ED prefix in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1706 diff changeset	62 11101101 ed_prefix
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	63 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	64 dispatch scratch1 ed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	65
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	66 11111101 fd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	67 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	68 dispatch scratch1 fd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	69
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	70 z80_check_cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	71 arg cond 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	72 local invert 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	73 switch cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	74 case 0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	75 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	76 lnot zflag invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	77
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	78 case 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	79 meta istrue zflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	80
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	81 case 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	82 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	83 not chflags invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	84 and 0x80 invert invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	85
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	86 case 3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	87 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	88 and 0x80 invert invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	89
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	90 case 4
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	91 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	92 lnot pvflag invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	93
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	94 case 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	95 meta istrue pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	96
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	97 case 6
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	98 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	99 not last_flag_result invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	100 and 0x80 invert invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	101
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	102 case 7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	103 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	104 and 0x80 last_flag_result invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	105
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	106 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	107
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	108 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	109 lsl h 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	110 or l scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	111 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	112
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	113 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	114 lsl h 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	115 or l scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	116 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	117
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	118 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	119 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	120 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	121 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	122
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	123 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	124 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	125 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	126 mov scratch1 wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	127 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	128 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	129 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	130 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	131 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	132 or scratch1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	133
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	134 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	135 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	136 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	137 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	138 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	139 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	140 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	141 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	142 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	143
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	144 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	145 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	146 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	147 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	148 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	149 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	150 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	151 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	152 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	153 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	154
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	155 01RRR110 ld_from_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	156 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	157 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	158
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	159 01DDDSSS ld_from_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	160 mov main.S main.D
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	161
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	162 z80_calc_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	163 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	164 mov index wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	165 z80_fetch_immed
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	166 sext 16 scratch1 scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	167 add scratch1 wz wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	168
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	169 z80_fetch_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	170 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	171 z80_calc_index index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	172 mov wz scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	173 cycles 5
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	174 ocall read_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	175
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	176 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	177 mov wz scratch2
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	178 ocall write_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	179
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	180 dd 01RRR110 ld_from_ix
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	181 z80_fetch_index ix
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	182 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	183
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	184 fd 01RRR110 ld_from_iy
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	185 z80_fetch_index iy
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	186 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	187
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	188 00RRR110 ld_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	189 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	190 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	191
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	192 01110RRR ld_to_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	193 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	194 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	195
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	196 dd 01110RRR ld_to_ix
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	197 z80_calc_index ix
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	198 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	199 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	200 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	201
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	202 fd 01110RRR ld_to_iy
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	203 z80_calc_index iy
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	204 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	205 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	206 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	207
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	208 00110110 ld_to_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	209 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	210 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	211
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	212 00001010 ld_a_from_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	213 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	214 or c scratch2 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	215 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	216 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	217
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	218 00011010 ld_a_from_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	219 lsl d 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	220 or e scratch2 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	221 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	222 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	223
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	224 00111010 ld_a_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	225 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	226 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	227 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	228 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	229
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	230 00000010 ld_a_to_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	231 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	232 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	233 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	234 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	235
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	236 00010010 ld_a_to_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	237 lsl d 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	238 or e scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	239 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	240 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	241
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	242 00110010 ld_a_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	243 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	244 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	245 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	246 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	247
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	248 ed 01000111 ld_i_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	249 mov a i
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	250 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	251
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	252 ed 01001111 ld_r_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	253 mov a r
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	254 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	255
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	256 00000001 ld_bc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	257 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	258 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	259 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	260
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	261 00010001 ld_de_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	262 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	263 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	264 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	265
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	266 00100001 ld_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	267 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	268 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	269 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	270
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	271 00110001 ld_sp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	272 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	273 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	274
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	275 dd 00100001 ld_ix_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	276 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	277 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	278
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	279 fd 00100001 ld_iy_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	280 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	281 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	282
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	283 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	284 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	285 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	286 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	287 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	288 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	289 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	290 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	291 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	292
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	293 00101010 ld_hl_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	294 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	295 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	296 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	297
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	298 ed 01001011 ld_bc_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	299 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	300 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	301 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	302
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	303 ed 01011011 ld_de_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	304 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	305 meta high c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	306 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	307
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	308 ed 01101011 ld_hl_from_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	309 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	310 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	311 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	312
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	313 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	314 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	315 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	316 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	317 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	318 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	319 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	320 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	321 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	322 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	323
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	324 ed 01111011 ld_sp_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	325 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	326 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	327
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	328 dd 00101010 ld_ix_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	329 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	330 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	331
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	332 fd 00101010 ld_iy_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	333 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	334 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	335
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	336 00100010 ld_hl_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	337 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	338 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	339 mov l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	340 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	341 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	342 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	343 mov h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	344 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	345
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	346 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	347 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	348 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	349 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	350 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	351 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	352 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	353 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	354 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	355
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	356 ed 01000011 ld_bc_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	357 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	358 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	359 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	360
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	361 ed 01010011 ld_de_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	362 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	363 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	364 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	365
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	366 ed 01100011 ld_hl_to_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	367 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	368 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	369 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	370
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	371 ed 01110011 ld_sp_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	372 meta low sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	373 local sph 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	374 lsr sp 8 sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	375 meta high sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	376 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	377
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	378 11111001 ld_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	379 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	380 lsl h 8 sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	381 or l sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	382 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	383 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	384 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	385 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	386 lsr sp 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	387 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	388 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	389
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	390 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	391 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	392 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	393 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	394 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	395 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	396 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	397 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	398 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	399 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	400
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	401 11000101 push_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	402 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	403 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	404 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	405
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	406 11010101 push_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	407 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	408 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	409 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	410
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	411 11100101 push_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	412 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	413 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	414 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	415
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	416 11110101 push_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	417 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	418 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	419 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	420
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	421 dd 11100101 push_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	422 local ixh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	423 lsr ix 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	424 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	425 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	426 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	427
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	428 fd 11100101 push_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	429 local iyh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	430 lsr iy 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	431 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	432 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	433 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	434
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	435 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	436 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	437 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	438 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	439 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	440 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	441 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	442 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	443 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	444
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	445 11000001 pop_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	446 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	447 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	448 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	449
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	450 11010001 pop_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	451 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	452 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	453 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	454
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	455 11100001 pop_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	456 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	457 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	458 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	459
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	460 11110001 pop_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	461 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	462 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	463 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	464
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	465 dd 11100001 pop_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	466 local ixh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	467 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	468 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	469 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	470 lsl ixh 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	471 or ixh ix ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	472
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	473 fd 11100001 pop_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	474 local iyh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	475 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	476 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	477 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	478 lsl iyh 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	479 or iyh iy iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	480
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	481 11101011 ex_de_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	482 xchg e l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	483 xchg d h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	484
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	485 00001000 ex_af_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	486 xchg a a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	487 xchg f f'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	488
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	489 11011001 exx
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	490 xchg b b'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	491 xchg c c'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	492 xchg d d'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	493 xchg e e'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	494 xchg h h'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	495 xchg l l'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	496
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	497 11100011 ex_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	498 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	499 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	500 xchg l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	501 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	502 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	503 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	504 add 1 sp wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	505 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	506 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	507 xchg h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	508 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	509 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	510 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	511
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	512 10000RRR add_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	513 add a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	514 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	515
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	516 dd 10000100 add_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	517 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	518 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	519 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	520
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	521 dd 10000101 add_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	522 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	523 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	524 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	525
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	526 fd 10000100 add_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	527 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	528 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	529 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	530
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	531 fd 10000101 add_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	532 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	533 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	534 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	535
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	536 10000110 add_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	537 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	538 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	539 update_flags SZYHVXN0C
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	540
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	541 dd 10000110 add_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	542 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	543 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	544 update_flags SZYHVXN0C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	545
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	546 fd 10000110 add_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	547 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	548 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	549 update_flags SZYHVXN0C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	550
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	551 11000110 add_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	552 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	553 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	554 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	555
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	556 z80_add16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	557 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	558 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	559 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	560 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	561 add src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	562 update_flags YHXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	563 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	564 lsr hlt 8 h
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	565
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	566 00001001 add_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	567 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	568 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	569 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	570 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	571 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	572 z80_add16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	573
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	574 00011001 add_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	575 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	576 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	577 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	578 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	579 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	580 z80_add16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	581
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	582 00101001 add_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	583 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	584 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	585 z80_add16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	586
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	587 00111001 add_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	588 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	589 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	590 z80_add16_hl sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	591
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	592 dd 00001001 add_ix_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	593 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	594 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	595 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	596 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	597
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	598 dd 00011001 add_ix_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	599 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	600 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	601 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	602 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	603
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	604 dd 00101001 add_ix_ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	605 add ix ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	606 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	607
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	608 dd 00111001 add_ix_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	609 add sp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	610 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	611
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	612 fd 00001001 add_iy_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	613 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	614 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	615 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	616 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	617
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	618 fd 00011001 add_iy_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	619 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	620 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	621 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	622 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	623
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	624 fd 00101001 add_iy_iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	625 add iy iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	626 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	627
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	628 fd 00111001 add_iy_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	629 add sp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	630 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	631
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	632 10001RRR adc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	633 adc a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	634 update_flags SZYHVXN0C
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	635
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	636 dd 10001100 adc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	637 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	638 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	639 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	640
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	641 dd 10001101 adc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	642 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	643 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	644 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	645
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	646 fd 10001100 adc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	647 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	648 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	649 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	650
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	651 fd 10001101 adc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	652 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	653 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	654 update_flags SZYHVXN0C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	655
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	656 10001110 adc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	657 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	658 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	659 update_flags SZYHVXN0C
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	660
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	661 dd 10001110 adc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	662 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	663 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	664 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	665
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	666 fd 10001110 adc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	667 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	668 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	669 update_flags SZYHVXN0C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	670
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	671 11001110 adc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	672 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	673 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	674 update_flags SZYHVXN0C
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	675
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	676 z80_adc16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	677 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	678 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	679 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	680 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	681 adc src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	682 update_flags SZYHVXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	683 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	684 lsr hlt 8 h
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	685
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	686 ed 01001010 adc_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	687 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	688 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	689 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	690 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	691 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	692 z80_adc16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	693
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	694 ed 01011010 adc_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	695 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	696 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	697 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	698 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	699 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	700 z80_adc16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	701
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	702 ed 01101010 adc_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	703 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	704 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	705 z80_adc16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	706
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	707
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	708 ed 01111010 adc_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	709 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	710 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	711 z80_adc16_hl sp
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	712
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	713 10010RRR sub_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	714 sub main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	715 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	716
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	717 dd 10010100 sub_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	718 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	719 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	720 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	721
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	722 dd 10010101 sub_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	723 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	724 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	725 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	726
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	727 fd 10010100 sub_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	728 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	729 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	730 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	731
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	732 fd 10010101 sub_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	733 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	734 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	735 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	736
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	737 10010110 sub_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	738 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	739 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	740 update_flags SZYHVXN1C
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	741
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	742 dd 10010110 sub_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	743 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	744 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	745 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	746
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	747 fd 10010110 sub_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	748 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	749 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	750 update_flags SZYHVXN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	751
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	752 11010110 sub_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	753 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	754 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	755 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	756
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	757 10011RRR sbc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	758 sbc main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	759 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	760
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	761 dd 10011100 sbc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	762 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	763 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	764 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	765
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	766 dd 10011101 sbc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	767 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	768 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	769 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	770
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	771 fd 10011100 sbc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	772 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	773 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	774 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	775
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	776 fd 10011101 sbc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	777 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	778 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	779 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	780
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	781
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	782 10011110 sbc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	783 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	784 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	785 update_flags SZYHVXN1C
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	786
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	787 dd 10011110 sbc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	788 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	789 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	790 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	791
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	792 fd 10011110 sbc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	793 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	794 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	795 update_flags SZYHVXN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	796
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	797 11011110 sbc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	798 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	799 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	800 update_flags SZYHVXN1C
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	801
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	802 z80_sbc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	803 arg src 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	804 lsl h 8 hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	805 or l hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	806 add 1 hlt wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	807 sbc src hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	808 update_flags SZYHVXN1C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	809 mov hlt l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	810 lsr hlt 8 h
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	811
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	812 ed 01000010 sbc_hl_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	813 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	814 local bcw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	815 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	816 lsl b 8 bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	817 or c bcw bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	818 z80_sbc16_hl bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	819
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	820 ed 01010010 sbc_hl_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	821 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	822 local dew 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	823 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	824 lsl d 8 dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	825 or e dew dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	826 z80_sbc16_hl dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	827
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	828 ed 01100010 sbc_hl_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	829 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	830 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	831 z80_sbc16_hl hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	832
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	833
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	834 ed 01110010 sbc_hl_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	835 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	836 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	837 z80_sbc16_hl sp
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	838
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	839 10100RRR and_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	840 and a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	841 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	842
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	843 10100110 and_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	844 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	845 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	846 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	847
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	848 11100110 and_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	849 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	850 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	851 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	852
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	853 10110RRR or_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	854 or a main.R a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	855 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	856
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	857 10110110 or_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	858 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	859 or a scratch1 a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	860 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	861
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	862 11110110 or_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	863 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	864 or a scratch1 a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	865 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	866
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	867 10101RRR xor_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	868 xor a main.R a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	869 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	870
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	871 10101110 xor_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	872 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	873 xor a scratch1 a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	874 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	875
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	876 11101110 xor_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	877 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	878 xor a scratch1 a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	879 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	880
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	881 10111RRR cp_reg
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	882 mov main.R last_flag_result
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	883 cmp main.R a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	884 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	885
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	886 dd 10111100 cp_ixh
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	887 lsr ix 8 last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	888 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	889 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	890
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	891 dd 10111101 cp_ixl
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	892 mov ix last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	893 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	894 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	895
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	896 fd 10111100 cp_iyh
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	897 lsr iy 8 last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	898 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	899 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	900
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	901 fd 10111101 cp_iyl
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	902 mov iy last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	903 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	904 update_flags SZHVN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	905
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	906 10111110 cp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	907 z80_fetch_hl
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	908 mov scratch1 last_flag_result
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	909 cmp scratch1 a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	910 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	911
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	912 dd 10111110 cp_ixd
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	913 z80_fetch_index ix
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	914 mov scratch1 last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	915 cmp scratch1 a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	916 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	917
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	918 fd 10111110 cp_iyd
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	919 z80_fetch_index iy
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	920 mov scratch1 last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	921 cmp scratch1 a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	922 update_flags SZHVN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	923
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	924 11111110 cp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	925 z80_fetch_immed
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	926 mov scratch1 last_flag_result
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	927 cmp scratch1 a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	928 update_flags SZHVN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	929
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	930 00RRR100 inc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	931 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	932 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	933
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	934 dd 00100100 inc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	935 add 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	936 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	937
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	938 dd 00101100 inc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	939 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	940 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	941 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	942 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	943 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	944 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	945
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	946 fd 00100100 inc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	947 add 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	948 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	949
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	950 fd 00101100 inc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	951 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	952 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	953 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	954 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	955 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	956 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	957
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	958 00110100 inc_hl
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	959 local tmp 8
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	960 z80_fetch_hl
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	961 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	962 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	963 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	964 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	965 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	966 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	967 z80_store_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	968
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	969 dd 00110100 inc_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	970 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	971 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	972 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	973 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	974 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	975 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	976 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	977 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	978 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	979 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	980
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	981 fd 00110100 inc_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	982 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	983 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	984 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	985 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	986 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	987 add 1 tmp tmp
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	988 update_flags SZYHVXN0
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	989 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	990 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	991 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	992
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	993 z80_inc_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	994 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	995 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	996 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	997 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	998 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	999 add 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1000 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1001 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1002
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1003 00000011 inc_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1004 z80_inc_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1005
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1006 00010011 inc_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1007 z80_inc_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1008
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1009 00100011 inc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1010 z80_inc_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1011
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1012 00110011 inc_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1013 add 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1014
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1015 dd 00100011 inc_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1016 add 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1017
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1018 fd 00100011 inc_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1019 add 1 iy iy
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1020
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1021 00RRR101 dec_reg
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1022 sub 1 main.R main.R
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1023 update_flags SZYHVXN1
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1024
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1025 dd 00100101 dec_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1026 sub 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1027 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1028
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1029 dd 00101101 dec_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1030 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1031 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1032 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1033 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1034 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1035 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1036
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1037 fd 00100101 dec_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1038 sub 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1039 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1040
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1041 fd 00101101 dec_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1042 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1043 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1044 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1045 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1046 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1047 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1048
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1049 00110101 dec_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1050 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1051 #TODO: fix size
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1052 sub 1 scratch1 scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1053 update_flags SZYHVXN1
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1054 z80_store_hl
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1055
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1056 dd 00110101 dec_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1057 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1058 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1059 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1060 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1061 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1062 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1063 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1064 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1065 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1066 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1067
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1068 fd 00110101 dec_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1069 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1070 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1071 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1072 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1073 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1074 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1075 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1076 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1077 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1078 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1079
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1080 z80_dec_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1081 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1082 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1083 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1084 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1085 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1086 sub 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1087 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1088 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1089
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1090 00001011 dec_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1091 z80_dec_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1092
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1093 00011011 dec_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1094 z80_dec_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1095
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1096 00101011 dec16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1097 z80_dec_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1098
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1099 00111011 dec_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1100 sub 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1101
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1102 dd 00101011 dec_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1103 sub 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1104
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1105 fd 00101011 dec_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1106 sub 1 iy iy
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1107
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1108 00101111 cpl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1109 not a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1110 update_flags YH1XN1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1111
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1112 11101101 neg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1113 neg a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1114 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1115
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1116 00111111 ccf
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1117 xor 0x80 chflags chflags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1118
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1119 00111111 scf
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1120 or 0x80 chflags chflags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1121
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1122 00000000 nop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1123
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1124 11110011 di
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1125 mov 0 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1126 mov 0 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1127 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1128
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1129 11111011 ei
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1130 mov 1 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1131 mov 1 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1132 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1133
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1134 ed 01000110 im0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1135 mov 0 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1136
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1137 ed 01010110 im1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1138 mov 1 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1139
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1140 ed 01011110 im2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1141 mov 2 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1142
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1143 11000011 jp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1144 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1145 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1146
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1147 11CCC010 jp_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1148 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1149 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1150 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1151
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1152 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1153
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1154 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1155
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1156 00011000 jr
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1157 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1158 #TODO: determine if this updates wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1159 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1160 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1161 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1162
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1163 001CC000 jr_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1164 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1165 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1166
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1167 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1168
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1169 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1170 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1171 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1172
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1173 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1174
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1175 00010000 djnz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1176 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1177 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1178 sub 1 b b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1179
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1180 if b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1181
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1182 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1183 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1184 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1185
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1186 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1187
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1188
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1189 11001101 call_uncond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1190 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1191 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1192 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1193 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1194 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1195 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1196 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1197
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1198 11TTT111 rst
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1199 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1200 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1201 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1202 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1203 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1204 lsl T 3 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1205 mov scratch1 pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1206
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1207 11001001 ret
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1208 #TODO: confirm this goes through wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1209 local wzh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1210 meta high wzh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1211 meta low wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1212 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1213 lsl wzh 8 wzh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1214 or wzh wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1215 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1216
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1217 11011011 in_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1218 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1219 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1220 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1221
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1222 ed 01RRR000 in_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1223 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1224 or c scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1225 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1226 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1227
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1228 11010011 out_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1229 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1230 mov scratch1 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1231 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1232 ocall io_write8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1233
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1234 ed 01RRR001 out_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1235 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1236 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1237 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1238 ocall io_write8

Mercurial > repos > blastem

annotate z80.cpu @ 1719:fb5ae8c20b85