repos/blastem: upd78k2_util.c annotate

annotate upd78k2_util.c @ 2724:8d21e109e163 default tip

Fix mov sfr, a in uPD78K/II disassembler

author	Michael Pavone <pavone@retrodev.com>
date	Thu, 17 Jul 2025 15:03:08 -0700
parents	8ce5d1a7ef54
children

rev	line source
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 #include <string.h>
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	2
2718 8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	3 //#define FETCH_DEBUG
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	4 void upd78k2_read_8(upd78k2_context *upd)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	5 {
2718 8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	6 #ifdef FETCH_DEBUG
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	7 uint32_t tmp = upd->scratch1;
2718 8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	8 #endif
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	9 upd->scratch1 = read_byte(upd->scratch1, (void **)upd->mem_pointers, &upd->opts->gen, upd);
2718 8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	10 #ifdef FETCH_DEBUG
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	11 if (tmp == upd->pc) {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	12 printf("uPD78K/II fetch %04X: %02X, AX=%02X%02X BC=%02X%02X DE=%02X%02X HL=%02X%02X SP=%04X\n", tmp, upd->scratch1,
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	13 upd->main[1], upd->main[0], upd->main[3], upd->main[2], upd->main[5], upd->main[4], upd->main[7], upd->main[6], upd->sp);
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	14 }
2718 8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	15 #endif
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	16 //FIXME: cycle count
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	17 upd->cycles += 2 * upd->opts->gen.clock_divider;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	18 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	19
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	20 void upd78k2_write_8(upd78k2_context *upd)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	21 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	22 write_byte(upd->scratch2, upd->scratch1, (void **)upd->mem_pointers, &upd->opts->gen, upd);
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	23 //FIXME: cycle count
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	24 upd->cycles += 2 * upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	25 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	26
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	27 #define CE0 0x08
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	28 #define CE1 0x08
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	29 #define CIF00 0x0010
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	30 #define CIF01 0x0020
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	31 #define CIF10 0x0040
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	32 #define CIF11 0x0080
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	33
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	34 void upd78k2_update_timer0(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	35 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	36 uint32_t diff = (upd->cycles - upd->tm0_cycle) / upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	37 upd->tm0_cycle += (diff & ~7) * upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	38 diff >>= 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	39 if (upd->tmc0 & CE0) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	40 uint32_t tmp = upd->tm0 + diff;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	41 //TODO: the rest of the CR00/CR01 stuff
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	42 if (upd->tm0 < upd->cr00 && tmp >= upd->cr00) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	43 upd->if0 \|= CIF00;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	44 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	45 if (upd->tm0 < upd->cr01 && tmp >= upd->cr01) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	46 upd->if0 \|= CIF01;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	47 if (upd->crc0 & 8) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	48 //CR01 clear is enabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	49 if (upd->cr01) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	50 while (tmp >= upd->cr01) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	51 tmp -= upd->cr01;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	52 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	53 } else {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	54 tmp = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	55 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	56 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	57 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	58 if (tmp > 0xFFFF) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	59 upd->tmc0 \|= 4;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	60 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	61 upd->tm0 = tmp;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	62 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	63 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	64
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	65 uint8_t upd78k2_tm1_scale(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	66 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	67 uint8_t scale = upd->prm1 & 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	68 if (scale < 2) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	69 scale = 2;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	70 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	71 scale++;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	72 return scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	73 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	74
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	75 void upd78k2_update_timer1(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	76 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	77 uint8_t scale = upd78k2_tm1_scale(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	78 uint32_t diff = (upd->cycles - upd->tm1_cycle) / upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	79 upd->tm1_cycle += (diff & ~((1 << scale) - 1)) * upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	80 diff >>= scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	81 if (upd->tmc1 & CE1) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	82 //tm1 count enabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	83 uint32_t tmp = upd->tm1 + diff;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	84 if (upd->tm1 < upd->cr10 && tmp >= upd->cr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	85 upd->if0 \|= CIF10;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	86 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	87 if (upd->tm1 < upd->cr11 && tmp >= upd->cr11) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	88 upd->if0 \|= CIF11;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	89 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	90 uint8_t do_clr11 = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	91 if (upd->crc1 & 2) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	92 //clr10 enabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	93 uint8_t do_clr10 = 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	94 if ((upd->crc1 & 0xC) == 8) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	95 //clr11 also enabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	96 if (upd->cr11 < upd->cr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	97 do_clr10 = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	98 do_clr11 = 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	99
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	100 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	101 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	102 if (do_clr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	103 if (upd->cr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	104 while (tmp >= upd->cr10) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	105 tmp -= upd->cr10;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	106 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	107 } else {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	108 tmp = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	109 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	110 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	111 } else if ((upd->crc1 & 0xC) == 8) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	112 do_clr11 = 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	113 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	114 if (do_clr11) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	115 if (upd->cr11) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	116 while (tmp >= upd->cr11) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	117 tmp -= upd->cr11;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	118 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	119 } else {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	120 tmp = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	121 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	122 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	123 if (tmp > 0xFF) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	124 upd->tmc1 \|= 4;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	125 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	126 upd->tm1 = tmp;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	127 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	128 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	129
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	130 #define CMK00 CIF00
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	131 #define CMK01 CIF01
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	132 #define CMK10 CIF10
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	133 #define CMK11 CIF11
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	134
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	135 void upd78k2_calc_next_int(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	136 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	137 uint32_t next_int = 0xFFFFFFFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	138 if (!upd->int_enable) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	139 //maskable interrupts disabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	140 //TODO: NMIs
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	141 upd->int_cycle = next_int;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	142 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	143 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	144 if (upd->if0 & (~upd->mk0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	145 //unmasked interrupt is pending
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	146 upd->int_cycle = upd->cycles;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	147 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	148 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	149 uint32_t cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	150 if (!(upd->mk0 & CMK00) && (upd->tmc0 & CE0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	151 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	152 cycle = ((uint16_t)(upd->cr00 - upd->tm0)) << 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	153 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	154 cycle += upd->tm0_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	155 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	156 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	157 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	158 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	159 if (!(upd->mk0 & CMK01) && (upd->tmc0 & CE0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	160 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	161 cycle = ((uint16_t)(upd->cr01 - upd->tm0)) << 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	162 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	163 cycle += upd->tm0_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	164 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	165 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	166 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	167 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	168 uint8_t scale = upd78k2_tm1_scale(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	169 if (!(upd->mk0 & CMK10) && (upd->tmc1 & CE1)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	170 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	171 cycle = ((uint8_t)(upd->cr10 - upd->tm1)) << scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	172 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	173 cycle += upd->tm1_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	174 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	175 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	176 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	177 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	178 if (!(upd->mk0 & CMK11) && (upd->tmc1 & CE1)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	179 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	180 cycle = ((uint8_t)(upd->cr11 - upd->tm1)) << scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	181 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	182 cycle += upd->tm1_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	183 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	184 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	185 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	186 }
2718 8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	187 #ifdef FETCH_DEBUG
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	188 if (next_int != upd->int_cycle) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	189 printf("UPD78K/II int cycle: %u, cur cycle %u\n", next_int, upd->cycles);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	190 }
2718 8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	191 #endif
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	192 upd->int_cycle = next_int;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	193 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	194
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	195 uint8_t upd78237_sfr_read(uint32_t address, void *context)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	196 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	197 upd78k2_context *upd = context;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	198 switch (address)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	199 {
2716 033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	200 case 0x00:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	201 case 0x04:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	202 case 0x05:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	203 case 0x06:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	204 return upd->port_data[address];
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	205 case 0x02:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	206 case 0x07:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	207 //input only
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	208 if (upd->io_read) {
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	209 upd->io_read(upd, address);
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	210 }
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	211 return upd->port_input[address];
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	212 break;
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	213 case 0x01:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	214 case 0x03:
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	215 if (upd->io_read) {
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	216 upd->io_read(upd, address);
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	217 }
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	218 return (upd->port_input[address] & upd->port_mode[address]) \| (upd->port_data[address] & ~upd->port_mode[address]);
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	219 case 0x10:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	220 return upd->cr00;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	221 case 0x11:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	222 return upd->cr00 >> 8;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	223 case 0x12:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	224 return upd->cr01;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	225 case 0x13:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	226 return upd->cr01 >> 8;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	227 case 0x14:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	228 return upd->cr10;
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	229 case 0x1C:
d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	230 return upd->cr11;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	231 case 0x21:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	232 case 0x26:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	233 return upd->port_mode[address & 0x7];
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	234 case 0x5D:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	235 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	236 printf("TMC0 Read: %02X\n", upd->tmc0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	237 return upd->tmc0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	238 case 0x5F:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	239 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	240 printf("TMC1 Read: %02X\n", upd->tmc1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	241 return upd->tmc1;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	242 case 0xC4:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	243 return upd->mm;
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	244 case 0xE0:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	245 return upd->if0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	246 case 0xE1:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	247 return upd->if0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	248 case 0xE4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	249 return upd->mk0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	250 case 0xE5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	251 return upd->mk0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	252 case 0xE8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	253 return upd->pr0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	254 case 0xE9:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	255 return upd->pr0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	256 case 0xEC:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	257 return upd->ism0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	258 case 0xED:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	259 return upd->ism0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	260 case 0xF4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	261 return upd->intm0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	262 case 0xF5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	263 return upd->intm1;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	264 case 0xF8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	265 return upd->ist;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	266 default:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	267 fprintf(stderr, "Unhandled uPD78237 SFR read %02X\n", address);
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	268 return 0xFF;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	269 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	270 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	271
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	272 void upd78237_sfr_write(uint32_t address, void context, uint8_t value)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	273 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	274 upd78k2_context *upd = context;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	275 if (address < 8 && address != 2 && address != 7) {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	276 upd->port_data[address] = value;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	277 } else {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	278 switch (address)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	279 {
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	280 case 0x00:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	281 case 0x01:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	282 case 0x03:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	283 case 0x04:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	284 case 0x05:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	285 case 0x06:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	286 printf("P%X: %02X\n", address & 7, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	287 upd->port_data[address & 7] = value;
2716 033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	288 if (upd->io_write) {
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	289 upd->io_write(upd, address);
033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	290 }
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	291 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	292 case 0x10:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	293 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	294 upd->cr00 &= 0xFF00;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	295 upd->cr00 \|= value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	296 printf("CR00: %04X\n", upd->cr00);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	297 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	298 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	299 case 0x11:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	300 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	301 upd->cr00 &= 0xFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	302 upd->cr00 \|= value << 8;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	303 printf("CR00: %04X\n", upd->cr00);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	304 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	305 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	306 case 0x12:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	307 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	308 upd->cr01 &= 0xFF00;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	309 upd->cr01 \|= value;
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	310 printf("CR01: %04X\n", upd->cr01);
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	311 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	312 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	313 case 0x13:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	314 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	315 upd->cr01 &= 0xFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	316 upd->cr01 \|= value << 8;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	317 printf("CR01: %04X\n", upd->cr01);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	318 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	319 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	320 case 0x14:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	321 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	322 upd->cr10 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	323 printf("CR10: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	324 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	325 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	326 case 0x1C:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	327 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	328 upd->cr11 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	329 printf("CR11: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	330 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	331 break;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	332 case 0x20:
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	333 case 0x21:
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	334 case 0x23:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	335 case 0x25:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	336 case 0x26:
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	337 printf("PM%X: %02X\n", address & 0x7, value);
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	338 upd->port_mode[address & 7] = value;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	339 break;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	340 case 0x30:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	341 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	342 upd->crc0 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	343 printf("CRC0 CLR01: %X, MOD: %X, Other: %X\n", value >> 3 & 1, value >> 6, value & 0x37);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	344 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	345 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	346 case 0x32:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	347 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	348 upd->crc1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	349 printf("CRC1 CLR11: %X, CM: %X, CLR10: %X\n", value >> 3 & 1, value >> 2 & 1, value >> 1 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	350 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	351 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	352 case 0x40:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	353 upd->puo = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	354 printf("PUO: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	355 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	356 case 0x43:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	357 upd->pmc3 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	358 printf("PMC3 TO: %X, SO: %X, SCK: %X, TxD: %X, RxD: %X\n", value >> 4, value >> 3 & 1, value >> 2 & 1, value >> 1 & 1, value & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	359 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	360 case 0x5D:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	361 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	362 upd->tmc0 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	363 printf("TMC0 CE0: %X, OVF0: %X - TM3 CE3: %X\n", value >> 3 & 1, value >> 2 & 1, value >> 7 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	364 if (!(value & 0x8)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	365 upd->tm0 = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	366 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	367 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	368 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	369 case 0x5E:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	370 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	371 upd->prm1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	372 printf("PRM1: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	373 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	374 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	375 case 0x5F:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	376 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	377 upd->tmc1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	378 printf("TMC1 CE2: %X, OVF2: %X, CMD2: %X, CE1: %X, OVF1: %X\n", value >> 7, value >> 6 & 1, value >> 5 & 1, value >> 3 & 1, value >> 2 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	379 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	380 break;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	381 case 0xC4:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	382 upd->mm = value;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	383 break;
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	384 case 0xE0:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	385 upd->if0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	386 upd->if0 \|= value;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	387 upd78k2_calc_next_int(upd);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	388 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	389 case 0xE1:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	390 upd->if0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	391 upd->if0 \|= value << 8;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	392 upd78k2_calc_next_int(upd);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	393 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	394 case 0xE4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	395 upd->mk0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	396 upd->mk0 \|= value;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	397 printf("MK0: %04X (low: %02X)\n", upd->mk0, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	398 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	399 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	400 case 0xE5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	401 upd->mk0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	402 upd->mk0 \|= value << 8;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	403 printf("MK0: %04X (hi: %02X)\n", upd->mk0, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	404 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	405 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	406 case 0xE8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	407 upd->pr0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	408 upd->pr0 \|= value;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	409 printf("PR0: %04X\n", upd->pr0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	410 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	411 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	412 case 0xE9:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	413 upd->pr0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	414 upd->pr0 \|= value << 8;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	415 printf("PR0: %04X\n", upd->pr0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	416 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	417 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	418 case 0xEC:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	419 upd->ism0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	420 upd->ism0 \|= value;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	421 printf("ISM0: %04X\n", upd->ism0);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	422 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	423 case 0xED:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	424 upd->ism0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	425 upd->ism0 \|= value << 8;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	426 printf("ISM0: %04X\n", upd->ism0);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	427 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	428 case 0xF4:
2716 033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	429 printf("INTM0: %02X\n", value);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	430 upd->intm0 = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	431 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	432 case 0xF5:
2716 033d8d4308e3 Fix enough issues in uPD78K/II core so that LaserActive firmware regularly polls front-panel button state Michael Pavone <pavone@retrodev.com> parents: 2714 diff changeset	433 printf("INTM1: %02X\n", value);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	434 upd->intm1 = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	435 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	436 case 0xF8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	437 upd->ist = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	438 break;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	439 default:
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	440 fprintf(stderr, "Unhandled uPD78237 SFR write %02X: %02X\n", address, value);
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	441 break;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	442 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	443 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	444 return context;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	445 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	446
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	447 void init_upd78k2_opts(upd78k2_options opts, memmap_chunk const chunks, uint32_t num_chunks)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	448 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	449 memset(opts, 0, sizeof(*opts));
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	450 opts->gen.memmap = chunks;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	451 opts->gen.memmap_chunks = num_chunks;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	452 opts->gen.address_mask = 0xFFFFF;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	453 opts->gen.max_address = 0xFFFFF;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	454 opts->gen.clock_divider = 1;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	455 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	456
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	457 upd78k2_context init_upd78k2_context(upd78k2_options opts)
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	458 {
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	459 upd78k2_context *context = calloc(1, sizeof(upd78k2_context));
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	460 context->opts = opts;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	461 memset(context->port_mode, 0xFF, sizeof(context->port_mode));
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	462 context->crc0 = 0x10;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	463 context->mm = 0x20;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	464 context->mk0 = 0xFFFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	465 context->pr0 = 0xFFFF;
2705 ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	466 return context;
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	467 }
ab2d916380bf WIP uPD78K/II CPU core Michael Pavone <pavone@retrodev.com> parents: diff changeset	468
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	469 void upd78k2_sync_cycle(upd78k2_context *upd, uint32_t target_cycle)
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	470 {
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	471 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	472 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	473 upd->sync_cycle = target_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	474 upd78k2_calc_next_int(upd);
2706 0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop Michael Pavone <pavone@retrodev.com> parents: 2705 diff changeset	475 }
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	476
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	477 void upd78k2_calc_vector(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	478 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	479 uint32_t pending_enabled = upd->scratch1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	480 uint32_t vector = 0x6;
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	481 uint32_t bit = 1;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	482 while (pending_enabled)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	483 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	484 if (pending_enabled & 1) {
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	485 upd->if0 &= ~bit;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	486 upd->scratch1 = vector;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	487 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	488 }
2714 d30e7f605ff8 Get uPD78k/II timer interrupts actually working and implement instructions needed for them to run to completion Michael Pavone <pavone@retrodev.com> parents: 2713 diff changeset	489 bit <<= 1;
2713 a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	490 pending_enabled >>= 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	491 vector += 2;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	492 if (vector == 0xE) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	493 vector = 0x14;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	494 } else if (vector == 0x20) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	495 vector = 0xE;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	496 } else if (vector == 0x14) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	497 vector = 0x20;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	498 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	499 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	500 fatal_error("upd78k2_calc_vector: %X\n", upd->scratch1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts Michael Pavone <pavone@retrodev.com> parents: 2706 diff changeset	501 }
2718 8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	502
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	503 void upd78k2_adjust_cycles(upd78k2_context *upd, uint32_t deduction)
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	504 {
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	505 upd78k2_update_timer0(upd);
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	506 upd78k2_update_timer1(upd);
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	507 if (upd->cycles <= deduction) {
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	508 upd->cycles = 0;
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	509 } else {
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	510 upd->cycles -= deduction;
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	511 }
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	512 if (upd->tm0_cycle <= deduction) {
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	513 upd->tm0_cycle = 0;
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	514 } else {
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	515 upd->tm0_cycle -= deduction;
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	516 }
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	517 if (upd->tm1_cycle <= deduction) {
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	518 upd->tm1_cycle = 0;
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	519 } else {
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	520 upd->tm1_cycle -= deduction;
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	521 }
8ce5d1a7ef54 Initial work to integrate PAC-less LaserActive emulation Michael Pavone <pavone@retrodev.com> parents: 2716 diff changeset	522 }

Mercurial > repos > blastem

annotate upd78k2_util.c @ 2724:8d21e109e163 default tip