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Wed, 26 Mar 2025 01:20:09 -0700 Michael Pavone Fix small bug in goto dispatch output of CPU dsl
Sat, 15 Mar 2025 23:15:05 -0700 Michael Pavone Implement breakpoints in new 68K core
Sat, 08 Mar 2025 20:20:23 -0800 Michael Pavone Fix mulu nflag when compiling with optimization enabled
Fri, 07 Mar 2025 23:40:58 -0800 Michael Pavone Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Mon, 24 Feb 2025 23:38:32 -0800 Michael Pavone Fix flags for mulu/muls in new 68K core
Sat, 22 Feb 2025 01:31:51 -0800 Michael Pavone Fix V flag for asl in new CPU core
Fri, 21 Feb 2025 01:45:04 -0800 Michael Pavone Implement stop in new 68K core
Mon, 17 Feb 2025 23:40:36 -0800 Michael Pavone Fix some issues with constant folding in CPU DSL
Sat, 15 Feb 2025 23:06:49 -0800 Michael Pavone Fix asr and lsr in new 68K core
Sat, 15 Feb 2025 19:11:40 -0800 Michael Pavone Fix lsl in new CPU core and make asl less broken
Sat, 15 Feb 2025 01:35:38 -0800 Michael Pavone Fix issues in CPU DSL that caused regressions in Z80 core
Thu, 13 Feb 2025 02:18:30 -0800 Michael Pavone Basic emscripten support
Sun, 09 Feb 2025 22:46:07 -0800 Michael Pavone Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd
Sun, 09 Feb 2025 22:37:41 -0800 Michael Pavone Fix masking issues in CPU DSL sext instruction
Sun, 09 Feb 2025 22:13:24 -0800 Michael Pavone Fix bug in sbc in CPU DSL impacting 68K subx and sbcd
Sun, 09 Feb 2025 18:07:40 -0800 Michael Pavone Fix some rotate instruction issues in new 68K core
Sun, 09 Feb 2025 16:54:38 -0800 Michael Pavone Fix regression in better unimplemented instruction error in CPU dsl
Sun, 09 Feb 2025 14:15:22 -0800 Michael Pavone Cut down on code bloat in 68K core a little
Sun, 09 Feb 2025 02:56:50 -0800 Michael Pavone Low confidence fix for edge case in CPU DSL not currently hit
Sat, 08 Feb 2025 20:04:18 -0800 Michael Pavone Implement divs and divu in new CPU core
Sat, 08 Feb 2025 12:51:35 -0800 Michael Pavone Better unimplemented instruction error message in CPU DSL
Sat, 08 Feb 2025 11:40:42 -0800 Michael Pavone Get 68K interrupts working in new CPU core
Fri, 07 Feb 2025 19:58:20 -0800 Michael Pavone Fix rol and ror in new CPU core
Fri, 07 Feb 2025 08:57:24 -0800 Michael Pavone WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Sat, 25 Jan 2025 21:25:01 -0800 Michael Pavone Implement exg, muls and mulu in new 68K core
Tue, 16 Jul 2024 20:21:08 -0700 Michael Pavone Partially functional asr/asl implementations in new 68K core
Tue, 30 Apr 2024 22:32:08 -0700 Michael Pavone Get blastem compiling with new 68K core
Tue, 30 Apr 2024 00:02:14 -0700 Michael Pavone Make some progress on compiling full emulator with new 68K core
Mon, 29 Apr 2024 22:57:33 -0700 Michael Pavone Fix constant propagation for sext instruction
Thu, 07 Mar 2024 00:53:11 -0800 Michael Pavone Implement lea and pea in new 68K core
Sat, 24 Feb 2024 22:54:36 -0800 Michael Pavone Implement ext instruction in new 68K core
Fri, 23 Feb 2024 23:09:07 -0800 Michael Pavone Fix carry flag calculation for neg instruction in CPU DSL
Mon, 19 Feb 2024 18:14:12 -0800 Michael Pavone Allow more if statements to be constant folded in CPU DSL
Mon, 19 Feb 2024 17:55:45 -0800 Michael Pavone Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Thu, 15 Feb 2024 21:49:17 -0800 Michael Pavone Fix some issues in new 68K core and add implementations of negx and clr instructions
Mon, 12 Feb 2024 07:42:32 -0800 Michael Pavone Sugar for unary operators in CPU DSL
Sun, 11 Feb 2024 20:41:28 -0800 Michael Pavone Sugar for some basic conditionals in CPU DSL
Sun, 11 Feb 2024 20:15:00 -0800 Michael Pavone Sugar for binary operators in CPU DSL
Sun, 11 Feb 2024 17:26:52 -0800 Michael Pavone Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Sat, 13 Jun 2020 00:37:22 -0700 Michael Pavone Somewhat buggy implementations of shift instructions in new 68K core
Thu, 23 Apr 2020 20:57:14 -0700 Michael Pavone Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Sat, 21 Sep 2019 10:48:10 -0700 Michael Pavone Implement interrupts in call dispatch mode in CPU DSL
Thu, 18 Apr 2019 19:47:50 -0700 Michael Pavone WIP new 68K core using CPU DSL
Wed, 20 Feb 2019 00:34:52 -0800 Michael Pavone Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Tue, 19 Feb 2019 22:51:33 -0800 Michael Pavone Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Fri, 15 Feb 2019 23:58:34 -0800 Michael Pavone Basic support for string operands in CPU DSL
Tue, 12 Feb 2019 09:58:04 -0800 Michael Pavone Integration of new Z80 core is sort of working now
Sun, 10 Feb 2019 11:58:23 -0800 Michael Pavone Initial attempt at interrupts in new Z80 core and integrating it into main executable
Sat, 09 Feb 2019 11:34:31 -0800 Michael Pavone Optimization to memory access in new Z80 core
Fri, 08 Feb 2019 23:09:58 -0800 Michael Pavone Added option to CPU DSL to produce a threaded interpreter using computed goto
Thu, 07 Feb 2019 09:43:25 -0800 Michael Pavone Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Wed, 06 Feb 2019 09:13:24 -0800 Michael Pavone Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Wed, 06 Feb 2019 08:54:09 -0800 Michael Pavone Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Tue, 05 Feb 2019 19:29:54 -0800 Michael Pavone Fixed half-carry flag calcuation for adc/sbc in new Z80 core
Mon, 04 Feb 2019 23:46:35 -0800 Michael Pavone Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Mon, 04 Feb 2019 22:20:51 -0800 Michael Pavone Implement DD/FD prefixes for instructions that don't reference HL
Mon, 04 Feb 2019 21:43:43 -0800 Michael Pavone Fixed some issues involving conditional execution and temporaries/constant folding
Sun, 03 Feb 2019 11:05:40 -0800 Michael Pavone Get new Z80 core running in CPM harness
Sun, 03 Feb 2019 10:40:41 -0800 Michael Pavone Implemented the rest of the block move instructions in new Z80 core
Sat, 02 Feb 2019 23:02:19 -0800 Michael Pavone Implemented LDI in new Z80 core
Sat, 02 Feb 2019 15:35:15 -0800 Michael Pavone Implemented RES instruction in new Z80 core
Fri, 01 Feb 2019 22:16:56 -0800 Michael Pavone Miscellaneous small fixes to new Z80 core
Thu, 31 Jan 2019 23:33:36 -0800 Michael Pavone Implemented shift instructions in new Z80 core
Thu, 31 Jan 2019 23:03:51 -0800 Michael Pavone Implemented the rest of the rotate instructions in new Z80 core
Thu, 31 Jan 2019 22:41:37 -0800 Michael Pavone Implementation of some of the rotate instructions in new Z80 core
Wed, 30 Jan 2019 21:47:35 -0800 Michael Pavone Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Wed, 30 Jan 2019 09:32:01 -0800 Michael Pavone Better error reporting when an instruction is given an insufficient number of parameters
Tue, 29 Jan 2019 23:56:48 -0800 Michael Pavone Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Tue, 29 Jan 2019 22:16:57 -0800 Michael Pavone Implement parity flag calculation type
Tue, 29 Jan 2019 21:26:39 -0800 Michael Pavone Actually correct overflow flag calculation in CPU DSL
Mon, 28 Jan 2019 22:56:43 -0800 Michael Pavone Fix sbc and implement carry/overflow flags for it in CPU DSL
Mon, 28 Jan 2019 22:49:02 -0800 Michael Pavone Implementation of carry/overflow flags for adc instructions in CPU DSL
Mon, 28 Jan 2019 22:37:46 -0800 Michael Pavone Fixed flag calculation for sub instructions in CPU DSL
Mon, 28 Jan 2019 21:30:23 -0800 Michael Pavone Less broken flag calulcation for sub instructions in CPU DSL
Mon, 28 Jan 2019 21:15:27 -0800 Michael Pavone Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Mon, 28 Jan 2019 20:54:55 -0800 Michael Pavone First stab at carry and half-carry calculation in CPU DSL
Mon, 28 Jan 2019 19:24:04 -0800 Michael Pavone Fix zero flag calculation in CPU DSL
Sun, 27 Jan 2019 14:37:37 -0800 Michael Pavone Implemented sbc instruction in CPU DSL
Sun, 27 Jan 2019 05:55:08 -0800 Michael Pavone Added adc instruction to CPU DSL
Fri, 25 Jan 2019 14:30:55 -0800 Michael Pavone Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Fri, 25 Jan 2019 14:13:46 -0800 Michael Pavone Fix constant propagation to a non-ephemeral destination in CPU DSL
Fri, 25 Jan 2019 13:55:30 -0800 Michael Pavone Fixed missing semicolon in coalesceFlags
Fri, 25 Jan 2019 13:45:58 -0800 Michael Pavone Added new sext instruction for sign extension to CPU sdl
Sat, 06 Oct 2018 17:33:15 -0700 Michael Pavone Implement program ROM reads
Thu, 04 Oct 2018 19:12:56 -0700 Michael Pavone Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Mon, 01 Oct 2018 19:16:54 -0700 Michael Pavone Clean up warnings from -1 case
Mon, 01 Oct 2018 19:11:17 -0700 Michael Pavone Getting SVP core closer to compiling
Tue, 25 Sep 2018 09:33:46 -0700 Michael Pavone Fix implementation cmp+condition version of if in CPU DSL
Mon, 24 Sep 2018 19:09:16 -0700 Michael Pavone Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Fri, 21 Sep 2018 09:26:12 -0700 Michael Pavone Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Tue, 18 Sep 2018 09:06:42 -0700 Michael Pavone Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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