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changeset 1055:ac4615d16226

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Implement undocumented flag bits for shift instructions
author Michael Pavone <pavone@retrodev.com>
date Fri, 29 Jul 2016 22:06:45 -0700
parents ca38a29d2d76
children 47c748455365
files z80_to_x86.c
diffstat 1 files changed, 9 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/z80_to_x86.c	Fri Jul 29 20:59:19 2016 -0700
+++ b/z80_to_x86.c	Fri Jul 29 22:06:45 2016 -0700
@@ -1673,8 +1673,11 @@
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
 		if (dst_op.mode == MODE_REG_DIRECT) {
+			mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_ir(code, 0, dst_op.base, SZ_B);
 		} else {
+			mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
+			mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
 		}
 		setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
@@ -1716,8 +1719,11 @@
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
 		if (dst_op.mode == MODE_REG_DIRECT) {
+			mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_ir(code, 0, dst_op.base, SZ_B);
 		} else {
+			mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
+			mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
 		}
 		setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
@@ -1759,8 +1765,11 @@
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
 		if (dst_op.mode == MODE_REG_DIRECT) {
+			mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_ir(code, 0, dst_op.base, SZ_B);
 		} else {
+			mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
+			mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 			cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
 		}
 		setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));