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Add code for converting IL into x86 machine code
author Mike Pavone <pavone@retrodev.com>
date Wed, 28 Aug 2013 01:05:45 -0700
parents 3b13ced3b562
children a8dffa4d4b54
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1 {
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2 regnames <- #["rax" "rcx" "rdx" "rbx" "rsp" "rbp" "rsi" "rdi" "r8" "r9" "r10" "r11" "r12" "r13" "r14" "r15"]
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3 uppernames <- #["ah" "ch" "dh" "bh"]
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4 ireg <- :regnum {
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5 #{
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6 num <- { regnum }
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7 reg <- { regnum and 7u8}
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8 string <- { regnames get: regnum }
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9 rm <- :tail { reg or 0xC0u8 | tail }
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10 validforSize? <- :size { true }
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11 isInteger? <- { false }
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12 isString? <- { false }
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13 register? <- { true }
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14 label? <- { false }
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15 upper? <- { false }
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16 needsRex? <- { regnum >= 8u8 }
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17 rexBitReg <- {
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18 if: needsRex? {
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19 4u8
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20 } else: {
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21 0u8
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22 }
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23 }
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24 rexBitRM <- {
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25 if: needsRex? {
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26 1u8
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27 } else: {
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28 0u8
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29 }
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30 }
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31 = <- :other {
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32 (not: (other isInteger?)) && (other register?) && (not: (other upper?)) && regnum = (other num)
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33 }
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34 }
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35 }
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36
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37 upper <- :regnum {
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38 #{
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39 num <- { regnum }
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40 reg <- { regnum }
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41 string <- { uppernames get: regnum - 4 }
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42 rm <- :tail { regnum or 0xC0u8 | tail }
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43 validforSize? <- :size {
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44 size = byte
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45 }
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46 isInteger? <- { false }
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47 register? <- { true }
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48 label? <- { false }
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49 upper? <- { true }
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50 needsRex? <- { false }
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51 = <- :other {
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52 (not: (other isInteger?)) && (other register?) && (other upper?) && regnum = (other num)
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53 }
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54 }
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55 }
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56 fakesrc <- #{
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57 needsRex? <- { false }
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58 rexBitReg <- { 0u8 }
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59 rexBitRM <- { 0u8 }
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60 }
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61 _size <- :s {
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62 #{
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63 num <- { s }
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64 = <- :other {
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65 s = (other num)
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66 }
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67 > <- :other {
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68 s > (other num)
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69 }
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70 >= <- :other {
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71 s >= (other num)
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72 }
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73 < <- :other {
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74 s < (other num)
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75 }
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76 <= <- :other {
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77 s <= (other num)
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78 }
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79 needsRex? <- { s = 3 }
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80 rexBit <- {
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81 if: needsRex? {
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82 0x08u8
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83 } else: {
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84 0u8
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85 }
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86 }
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87 }
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88 }
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89 byte <- _size: 0
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90 word <- _size: 1
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91 dword <- _size: 2
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92 qword <- _size: 3
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93
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94 condition <- :num {
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95 #{
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96 cc <- { num }
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97 }
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98 }
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99 _o <- condition: 0u8
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100 _no <- condition: 1u8
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101 _c <- condition: 2u8
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102 _nc <- condition: 3u8
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103 _z <- condition: 4u8
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104 _nz <- condition: 5u8
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105 _be <- condition: 6u8
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106 _nbe <- condition: 7u8
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107 _s <- condition: 8u8
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108 _ns <- condition: 9u8
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109 _p <- condition: 10u8
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110 _np <- condition: 11u8
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111 _l <- condition: 12u8
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112 _nl <- condition: 13u8
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113 _le <- condition: 14u8
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114 _nle <- condition: 15u8
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115
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116
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117 size_bit <- :opcode size {
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118 if: size = byte {
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119 opcode
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120 } else: {
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121 opcode or 1u8
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122 }
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123 }
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124 opex <- :val {
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125 #{
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126 reg <- { val }
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127 string <- { "opex " . val}
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128 }
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129 }
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130
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131 mod_rm:withTail <- :register regmem :end {
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132 list <- regmem rm: end
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133 (list value) or ( lshift: (register reg) by: 3u8) | (list tail)
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134 }
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135
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136 mod_rm <- :reg rm {
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137 mod_rm: reg rm withTail: []
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138 }
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139
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140 int_op:withTail <- :value size :tail {
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141 if: size >= dword {
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142 tail <- (uint8: (rshift: value by: 16u64)) | (uint8: (rshift: value by: 24u64)) | tail
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143 }
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144 if: size >= word {
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145 tail <- (uint8: (rshift: value by: 8u64)) | tail
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146 }
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147 (uint8: value) | tail
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148 }
175
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149 int_op <- :value size {
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150 int_op: value size withTail: []
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151 }
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152 //used for mov instructions that support 64-bit immediate operands/offsets
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153 int_op64 <- :value size {
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154 tail <- []
183
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155 value <- uint64: value
175
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156 if: size = qword {
179
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157 tail <- (uint8: (rshift: value by: 32u64)) | (uint8: (rshift: value by: 40u64)) | (uint8: (rshift: value by: 48u64)) | (uint8: (rshift: value by: 56u64)) | tail
175
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158 }
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159 int_op: value size withTail: tail
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160 }
174
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161
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162 prefix:withInstruction <- :reg rm size :inst {
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163 if: size = word {
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164 inst <- 0x66u8 | inst
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165 }
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166 if: (size needsRex?) || (reg needsRex?) || (rm needsRex?) {
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167 rex <- 0x40u8 or (size rexBit) or (reg rexBitReg) or (rm rexBitRM)
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168 inst <- rex | inst
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169 }
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170 inst
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171 }
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172
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173 _rax <- ireg: 0u8
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174 _rcx <- ireg: 1u8
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175 _rdx <- ireg: 2u8
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176 _rbx <- ireg: 3u8
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177 _rsp <- ireg: 4u8
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178 _rbp <- ireg: 5u8
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179 _rsi <- ireg: 6u8
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180 _rdi <- ireg: 7u8
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181 _r8 <- ireg: 8u8
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182 _r9 <- ireg: 9u8
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183 _r10 <- ireg: 10u8
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184 _r11 <- ireg: 11u8
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185 _r12 <- ireg: 12u8
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186 _r13 <- ireg: 13u8
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187 _r14 <- ireg: 14u8
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188 _r15 <- ireg: 15u8
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189 _ah <- upper: 4u8
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190 _ch <- upper: 5u8
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191 _dh <- upper: 6u8
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192 _bh <- upper: 7u8
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193
193
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194 //AMD64 convention
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195 _argregs <- #[
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196 _rdi
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197 _rsi
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198 _rdx
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199 _rcx
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200 _r8
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201 _r9
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202 ]
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203 _calleesave <- #[
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204 _rbx
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205 _rbp
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206 _r12
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207 _r13
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208 _r14
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209 _r15
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210 ]
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211 _tempregs <- #[
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212 _r10
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213 _r11
194
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214 //TODO: Add rax back in once there's logic in il to properly
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215 //allocate it for the instances in which it's live
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216 //_rax
193
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217 ]
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218
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219
180
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220 inst <- :ilist {
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221 #{
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222 length <- { ilist length }
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223 flattenTo:at <- :dest :idx {
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224 ilist fold: idx with: :idx byte {
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225 dest set: idx byte
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226 idx + 1
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227 }
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228 }
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229 }
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230 }
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231
175
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232 op:withCode:withImmed:withOpEx <- :src dst size :normal :immed :myopex {
174
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233 reg <- src
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234 rm <- dst
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235 base <- if: (src isInteger?) {
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236 reg <- fakesrc
175
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237 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
174
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238 } else: {
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239 if: (src register?) {
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240 (size_bit: normal size) | (mod_rm: src dst)
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241 } else: {
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242 reg <- dst
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243 rm <- src
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244 (size_bit: normal or 0x02u8 size) | (mod_rm: dst src)
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245 }
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246 }
180
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247 inst: (prefix: reg rm size withInstruction: base)
174
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248 }
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249
175
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250 op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt {
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251 reg <- src
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252 rm <- dst
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253 if: (src isInteger?) {
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254 reg <- fakesrc
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255 base <- if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) {
179
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256 byteExt | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)])
175
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257 } else: {
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258 if: dst = _rax {
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259 (size_bit: immedRax size) | (int_op: src size)
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260 } else: {
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261 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
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262 }
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263 }
180
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264 inst: (prefix: reg rm size withInstruction: base)
175
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265 } else: {
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266 op: src dst size withCode: normal withImmed: immed withOpEx: myopex
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267 }
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268 }
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269
183
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270 _jmprel <- :op jmpDest {
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271 }
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272
174
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273 #{
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274 rax <- { _rax }
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275 rcx <- { _rcx }
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276 rdx <- { _rdx }
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277 rbx <- { _rbx }
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278 rsp <- { _rsp }
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279 rbp <- { _rbp }
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280 rsi <- { _rsi }
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281 rdi <- { _rdi }
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282 r8 <- { _r8 }
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283 r9 <- { _r9 }
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284 r10 <- { _r10 }
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285 r11 <- { _r11 }
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286 r12 <- { _r12 }
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287 r13 <- { _r13 }
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288 r14 <- { _r14 }
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289 r15 <- { _r15 }
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290 ah <- { _ah }
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291 ch <- { _ch }
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292 dh <- { _dh }
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293 bh <- { _bh }
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294
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295 b <- { byte }
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296 w <- { word }
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297 d <- { dword }
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298 q <- { qword }
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299
183
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300 o <- { _o }
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301 no <- { _no }
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302 c <- { _c }
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303 nc <- { _nc }
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304 ae <- { _nc }
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305 z <- { _z }
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306 e <- { _z }
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307 nz <- { _nz }
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308 ne <- { _nz }
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309 be <- { _be }
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310 nbe <- { _nbe }
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311 a <- { _nbe }
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312 s <- { _s }
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313 ns <- { _ns }
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314 p <- { _p }
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315 pe <- { _p }
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316 np <- { _np }
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317 po <- { _np }
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318 l <- { _l }
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319 nl <- { _nl }
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320 ge <- { _nl }
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321 le <- { _le }
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322 nle <- { _nle }
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323 g <- { _nle }
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324
174
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325 add <- :src dst size {
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326 op: src dst size withCode: 0u8 withImmed: 0x80u8 withImmedRax: 0x04u8 withOpEx: 0u8 withByteExtend: 0x83u8
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327 }
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328
175
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329 sub <- :src dst size {
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330 op: src dst size withCode: 0x28u8 withImmed: 0x80u8 withImmedRax: 0x2Cu8 withOpEx: 5u8 withByteExtend: 0x83u8
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331 }
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332
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333 mov <- :src dst size {
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334 rm <- dst
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335 if: (src isInteger?) && (dst register?) {
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336 opval <- if: size = byte { 0xB0u8 } else: { 0xB8u8 }
183
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337 base <- opval or (dst reg) | (int_op64: src size)
180
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338 inst: (prefix: fakesrc rm size withInstruction: base)
175
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339 } else: {
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340 op: src dst size withCode: 0x88u8 withImmed: 0xC6u8 withOpEx: 0u8
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341 }
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342 }
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343
180
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344 ret <- { inst: [ 0xC3u8 ] }
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345
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346 label <- {
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347 _offset <- -1
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348 _forwardRefs <- #[]
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349 #{
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350 length <- { 0 }
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351 hasOffset? <- { _offset >= 0 }
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352 offset <- { _offset }
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353 register? <- { false }
181
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354 label? <- { true }
180
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355 flattenTo:at <- :dest :idx {
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356 if: (not: hasOffset?) {
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357 _offset <- idx
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358 foreach: _forwardRefs :idx fun {
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359 fun: _offset
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360 }
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361 _forwardRefs <- #[]
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362 }
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363 idx
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364 }
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365 withOffset:else <- :fun :elsefun {
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366 if: hasOffset? {
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367 fun: _offset
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368 } else: {
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369 _forwardRefs append: fun
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370 elsefun:
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371 }
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372 }
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373 }
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374 }
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375
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376 jmp <- :jmpDest {
181
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377 if: (jmpDest label?) {
180
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378 _size <- -1
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379 #{
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380 length <- { if: _size < 0 { 5 } else: { _size } }
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381 flattenTo:at <- :dest :idx {
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382 jmpDest withOffset: :off {
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383 if: _size < 0 {
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384 rel <- off - (idx + 2)
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385 if: rel < 128 && rel >= -128 {
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386 _size <- 2
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387 } else: {
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388 rel <- rel - 2
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389 if: rel < 32768 && rel >= -32768 {
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390 _size <- 4
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391 } else: {
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392 _size <- 5
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393 }
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394 }
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395 }
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396 rel <- off - (idx + _size)
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397 if: _size = 2 {
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398 dest set: idx 0xEBu8
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399 dest set: (idx + 1) (uint8: rel)
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400 } else: {
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401 if: _size = 4 {
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402 dest set: idx 0x66u8
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403 dest set: (idx + 1) 0xE9u8
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404 dest set: (idx + 2) (uint8: rel)
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405 dest set: (idx + 3) (uint8: (rshift: rel by: 8))
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406 } else: {
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407 dest set: idx 0xE9u8
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408 dest set: (idx + 1) (uint8: rel)
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409 dest set: (idx + 2) (uint8: (rshift: rel by: 8))
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diff changeset
410 dest set: (idx + 3) (uint8: (rshift: rel by: 16))
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411 dest set: (idx + 4) (uint8: (rshift: rel by: 24))
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412 }
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diff changeset
413 }
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414 } else: {
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415 _size <- 5
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416 }
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417 idx + _size
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418 }
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419 }
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420 } else: {
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421 inst: 0xFFu8 | (mod_rm: (opex: 5u8) jmpDest)
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422 }
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423 }
175
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diff changeset
424
183
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diff changeset
425 jcc <- :cond jmpDest {
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diff changeset
426 _size <- -1
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diff changeset
427 #{
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parents: 181
diff changeset
428 length <- { if: _size < 0 { 5 } else: { _size } }
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parents: 181
diff changeset
429 flattenTo:at <- :dest :idx {
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parents: 181
diff changeset
430 jmpDest withOffset: :off {
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parents: 181
diff changeset
431 if: _size < 0 {
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parents: 181
diff changeset
432 rel <- off - (idx + 2)
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parents: 181
diff changeset
433 if: rel < 128 && rel >= -128 {
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parents: 181
diff changeset
434 _size <- 2
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parents: 181
diff changeset
435 } else: {
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parents: 181
diff changeset
436 _size <- 6
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parents: 181
diff changeset
437 }
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parents: 181
diff changeset
438 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
439 rel <- off - (idx + _size)
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parents: 181
diff changeset
440 if: _size = 2 {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
441 dest set: idx 0x70u8 or (cond cc)
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parents: 181
diff changeset
442 dest set: (idx + 1) (uint8: rel)
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parents: 181
diff changeset
443 } else: {
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parents: 181
diff changeset
444 dest set: idx 0x0Fu8
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parents: 181
diff changeset
445 dest set: (idx + 1) 0x80u8 or (cond cc)
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parents: 181
diff changeset
446 dest set: (idx + 2) (uint8: rel)
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parents: 181
diff changeset
447 dest set: (idx + 3) (uint8: (rshift: rel by: 8))
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
448 dest set: (idx + 4) (uint8: (rshift: rel by: 16))
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parents: 181
diff changeset
449 dest set: (idx + 5) (uint8: (rshift: rel by: 24))
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
450 }
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parents: 181
diff changeset
451 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
452 _size <- 6
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parents: 181
diff changeset
453 }
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parents: 181
diff changeset
454 idx + _size
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parents: 181
diff changeset
455 }
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parents: 181
diff changeset
456 }
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parents: 181
diff changeset
457 }
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parents: 181
diff changeset
458
181
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
459 call <- :callDest {
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parents: 180
diff changeset
460 if: (callDest label?) {
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
461 #{
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
462 length <- { 5 }
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parents: 180
diff changeset
463 flattenTo:at <- :dest :idx {
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parents: 180
diff changeset
464 dest set: idx 0xE8u8
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parents: 180
diff changeset
465 callDest withOffset: :off {
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parents: 180
diff changeset
466 rel <- off - (idx + 5)
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parents: 180
diff changeset
467 dest set: (idx + 1) (uint8: rel)
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parents: 180
diff changeset
468 dest set: (idx + 2) (uint8: (rshift: rel by: 8))
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
469 dest set: (idx + 3) (uint8: (rshift: rel by: 16))
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
470 dest set: (idx + 4) (uint8: (rshift: rel by: 24))
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
471 } else: {
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
472 }
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
473 idx + 5
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
474 }
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
475 }
f188723c15b4 Add call instruction to x86 module
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
476 } else: {
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
477 inst: 0xFFu8 | (mod_rm: (opex: 2u8) callDest)
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
478 }
f188723c15b4 Add call instruction to x86 module
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
479 }
174
8b5829372ad1 Initial work on x86 instruction encoding module
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parents:
diff changeset
480
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
481 push <- :src {
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parents: 181
diff changeset
482 if: (src isInteger?) {
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parents: 181
diff changeset
483 if: src < 128 && src > -128 {
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parents: 181
diff changeset
484 inst: 0x6Au8 | (uint8: src)
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parents: 181
diff changeset
485 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
486 inst: 0x68u8 | (uint8: src) | (uint8: (rshift: src by: 8)) | (uint8: (rshift: src by: 16)) | (uint8: (rshift: src by: 24))
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
487 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
488 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
489 base <- if: (src register?) {
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parents: 181
diff changeset
490 [0x50u8 or (src reg)]
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
491 } else: {
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parents: 181
diff changeset
492 0xFFu8 | (mod_rm: (opex: 6u8) src)
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parents: 181
diff changeset
493 }
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parents: 181
diff changeset
494 inst: (prefix: fakesrc src d withInstruction: base)
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parents: 181
diff changeset
495 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
496 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
497
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
498 pop <- :dst {
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parents: 181
diff changeset
499 base <- if: (dst register?) {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
500 [0x58u8 or (dst reg)]
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parents: 181
diff changeset
501 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
502 0x8Fu8 | (mod_rm: (opex: 0u8) dst)
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parents: 181
diff changeset
503 }
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parents: 181
diff changeset
504 inst: (prefix: fakesrc dst d withInstruction: base)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
505 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
506
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
507 //TODO: support multiple calling conventions
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parents: 183
diff changeset
508 regSource <- {
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parents: 183
diff changeset
509 _used <- 0
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parents: 183
diff changeset
510 _usedAllTime <- 0
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parents: 183
diff changeset
511 _nextStackOff <- 0
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parents: 183
diff changeset
512 _findUnused <- :size reglists{
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parents: 183
diff changeset
513 found <- -1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
514 foundlist <- -1
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parents: 183
diff changeset
515 curlist <- 0
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
516 ll <- reglists length
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
517 while: { found < 0 && curlist < ll } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
518 cur <- 0
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
519 regs <- reglists get: curlist
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
520 len <- regs length
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
521 while: { found < 0 && cur < len } do: {
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
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parents: 194
diff changeset
522 bit <- lshift: 1 by: ((regs get: cur) num)
193
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parents: 183
diff changeset
523 if: (_used and bit) = 0 {
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parents: 183
diff changeset
524 found <- cur
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parents: 183
diff changeset
525 foundlist <- regs
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
526 _used <- _used or bit
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parents: 183
diff changeset
527 _usedAllTime <- _usedAllTime or bit
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parents: 183
diff changeset
528 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
529 cur <- cur + 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
530 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
531 curlist <- curlist + 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
532 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
533 if: found >= 0 {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
534 foundlist get: found
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
535 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
536 myoff <- _nextStackOff
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
537 _nextStackOff <- _nextStackOff + size
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
538 il base: _rsp offset: myoff
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
539 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
540 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
541 #{
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parents: 183
diff changeset
542 alloc <- :size {
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parents: 183
diff changeset
543 _findUnused: size #[
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parents: 183
diff changeset
544 _calleesave
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
545 _tempregs
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parents: 183
diff changeset
546 _argregs
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parents: 183
diff changeset
547 ]
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
548 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
549 //used to allocate a register
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parents: 183
diff changeset
550 //that will be returned before a call
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parents: 183
diff changeset
551 allocTemp <- :size {
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parents: 183
diff changeset
552 _findUnused: size #[
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parents: 183
diff changeset
553 _tempregs
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parents: 183
diff changeset
554 _argregs
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parents: 183
diff changeset
555 _calleesave
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parents: 183
diff changeset
556 ]
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
557 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
558 //allocated the return register
194
30bed95cbb18 Apply register assignments in il module
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parents: 193
diff changeset
559 allocRet <- {
193
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560 bit <- (lshift: 1 by: (_rax num))
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diff changeset
561 _used <- _used or bit
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562 _usedAllTime <- _usedAllTime or bit
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563 _rax
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564 }
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565 allocArg <- :argnum {
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566 if: argnum < (_argregs length) {
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567 reg <- _argregs get: argnum
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diff changeset
568 bit <- (lshift: 1 by: (reg num))
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diff changeset
569 _used <- _used or bit
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diff changeset
570 _usedAllTime <- _usedAllTime or bit
194
30bed95cbb18 Apply register assignments in il module
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diff changeset
571 reg
193
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572 } else: {
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diff changeset
573 il base: _rsp offset: _nextStackOff + 8 * (argnum - (_argregs length))
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574 }
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575 }
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diff changeset
576 allocSpecific <- :reg {
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diff changeset
577 if: (reg register?) {
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diff changeset
578 bit <- (lshift: 1 by: (reg num))
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diff changeset
579 _used <- _used or bit
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580 }
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581 }
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582 stackSize <- { _nextStackOff }
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583 return <- :reg {
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584 _used <- _used and (0xF xor (lshift: 1 by: (reg num)))
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585 }
198
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586 returnAll <- { _used <- 0 }
193
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587 needSaveProlog <- {
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588 retval <- #[]
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diff changeset
589 foreach: _calleesave :idx reg {
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
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590 bit <- lshift: 1 by: (reg num)
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591 if: (_usedAllTime and bit) != 0 {
193
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diff changeset
592 retval append: reg
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593 }
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594 }
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diff changeset
595 retval
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diff changeset
596 }
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597 needSaveForCall <- {
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diff changeset
598 retval <- #[]
198
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diff changeset
599 foreach: #[(_tempregs) (_argregs)] :_ regs {
193
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diff changeset
600 foreach: regs :_ reg {
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diff changeset
601 if: (_used and (lshift: 1 by: (reg num))) != 0 {
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602 retval append: reg
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603 }
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604 }
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diff changeset
605 }
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diff changeset
606 retval
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diff changeset
607 }
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diff changeset
608 }
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parents: 183
diff changeset
609 }
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diff changeset
610
203
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611 adjustIL <- :ilfun {
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612 il to2Op: (il allocRegs: ilfun withSource: regSource)
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613 }
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614
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diff changeset
615 convertIL:to:withLabels:withSaved <- :inst :outarr :labels :saved {
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616 mapSize <- :ilsize {
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617 if: (ilsize bytes) > 2 {
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618 if: (ilsize bytes) = 8 { q } else: { d }
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diff changeset
619 } else: {
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620 if: (ilsize bytes) = 1 { b } else: { w }
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diff changeset
621 }
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622 }
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diff changeset
623 mapcond <- :ilcond {
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624 ccmap <- #[
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diff changeset
625 e
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diff changeset
626 ne
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diff changeset
627 ge
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diff changeset
628 le
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diff changeset
629 g
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diff changeset
630 l
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diff changeset
631 ae
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diff changeset
632 be
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633 a
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634 c
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diff changeset
635 ]
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diff changeset
636 ccmap get: (ilcond cc)
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diff changeset
637 }
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638 opmap <- #[
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639 { outarr append: (add: (inst in) (inst out) (mapSize: (inst size))) }
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640 { } //and
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641 { } //or
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642 { } //xor
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643 { outarr append: (sub: (inst in) (inst out) (mapSize: (inst size))) }
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644 { } //cmp
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645 { } //not
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646 { } //sl
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diff changeset
647 { } //asr
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diff changeset
648 { } //lsr
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diff changeset
649 { } //rol
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diff changeset
650 { } //ror
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diff changeset
651 { outarr append: (mov: (inst in) (inst out) (mapSize: (inst size))) }
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diff changeset
652 {
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diff changeset
653 //call
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654 arguments <- inst args
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655 cur <- (arguments length) - 1
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diff changeset
656 while: { cur >= 0 } do: {
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diff changeset
657 src <- (arguments get: cur)
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diff changeset
658 if: cur < (_argregs length) {
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diff changeset
659 dst <- _argregs get: cur
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diff changeset
660 if: (not: dst = src) {
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diff changeset
661 //TODO: Handle edge case in which src is a caller saved
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diff changeset
662 //reg that has been pusehd onto the stack to preserve
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diff changeset
663 //it across this call
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diff changeset
664 outarr append: (mov: src dst q)
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diff changeset
665 }
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diff changeset
666 } else: {
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diff changeset
667 outarr append: (push: src)
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668 }
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diff changeset
669 cur <- cur - 1
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670 }
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diff changeset
671 toCall <- inst target
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diff changeset
672 if: (toCall isString?) {
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diff changeset
673 //TODO: Handle call to undefined label
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674 toCall <- labels get: toCall
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diff changeset
675 }
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diff changeset
676 outarr append: (call: toCall)
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diff changeset
677 }
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diff changeset
678 {
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diff changeset
679 //return
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diff changeset
680 if: (not: _rax = (inst arg)) {
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diff changeset
681 outarr append: (mov: (inst arg) _rax q)
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diff changeset
682 }
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diff changeset
683 foreach: saved :_ reg {
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diff changeset
684 outarr append: (pop: reg)
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diff changeset
685 }
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diff changeset
686 outarr append: (ret: )
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diff changeset
687 }
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diff changeset
688 {
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diff changeset
689 //skipIf
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diff changeset
690 endlab <- label:
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diff changeset
691 outarr append: (jcc: (mapcond: (inst cond)) endlab)
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diff changeset
692 foreach: (inst toskip) :_ inst {
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diff changeset
693 convertIL: inst to: outarr withLabels: labels withSaved: saved
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diff changeset
694 }
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diff changeset
695 outarr append: endlab
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diff changeset
696 }
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diff changeset
697 {
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diff changeset
698 //save
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parents: 199
diff changeset
699 newsave <- []
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diff changeset
700 foreach: (inst tosave) :_ reg {
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diff changeset
701 outarr append: (push: reg)
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diff changeset
702 newsave <- reg | newsave
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diff changeset
703 }
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diff changeset
704 foreach: (inst scope) :_ inst {
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parents: 199
diff changeset
705 convertIL: inst to: outarr withLabels: labels withSaved: newsave
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
706 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
707 if: ((inst scope) length) = 0 || (((inst scope) get: ((inst scope) length) - 1) opcode) != 14 {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
708 foreach: newsave :_ reg {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
709 outarr append: (pop: reg)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
710 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
711 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
712 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
713 ]
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
714 fun <- opmap get: (inst opcode)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
715 fun:
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
716 outarr
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
717 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
718
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
719 convertIL:to:withLabels <- :inst :outarr :labels {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
720 convertIL: inst to: outarr withLabels: labels withSaved: []
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
721 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
722
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
723 main <- {
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
724 fib <- label:
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
725 notbase <- label:
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
726 prog <- #[
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
727 fib
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
728 sub: 2 rdi q
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
729 jcc: ge notbase
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
730 mov: 1 rax q
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
731 ret:
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
732
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
733 notbase
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
734 push: rdi
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
735 call: fib
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
736 pop: rdi
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
737 push: rax
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
738 add: 1 rdi q
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
739 call: fib
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
740 pop: rdi
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
741 add: rdi rax q
181
f188723c15b4 Add call instruction to x86 module
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
742 ret:
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
743 ]
180
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
744
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
745 ba <- bytearray executableFromBytes: prog
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
746 res <- ba runWithArg: 30u64
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
747 print: (string: res) . "\n"
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
748 0
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
749 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
750 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
751 }