annotate modules/il.tp @ 243:5b830147c1cd

Use a lightweight substring object in a few places in the parser to improve performance for large files.
author Mike Pavone <pavone@retrodev.com>
date Sun, 05 Jan 2014 23:07:26 -0800
parents 56b2100d9fff
children 2308336790d4
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1 {
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2 //commutative ops
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3 _add <- 0
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4 _and <- 1
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5 _or <- 2
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6 _xor <- 3
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7 //non-commutative ops
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8 _sub <- 4
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9 _cmp <- 5
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10 _not <- 6
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11 _sl <- 7
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12 _asr <- 8
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13 _lsr <- 9
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14 _rol <- 10
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15 _ror <- 11
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16 _mov <- 12
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17 _call <- 13
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18 _ret <- 14
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19 _skipif <- 15
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20 _save <- 16
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21
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22 _names <- #[
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23 "add"
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24 "and"
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25 "or"
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26 "xor"
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27 "sub"
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28 "cmp"
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29 "not"
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30 "sl"
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31 "asr"
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32 "lsr"
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33 "rol"
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34 "ror"
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35 "mov"
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36 "call"
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37 "ret"
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38 "skipIf"
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39 "save"
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40 ]
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41
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42 op3:a:b:out:size <- :_opcode :_ina :_inb :_out :_size {
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43 #{
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44 opcode <- { _opcode }
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45 ina <- { _ina }
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46 inb <- { _inb }
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47 commutative? <- { _opcode < _sub }
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48 out <- { _out }
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49 size <- { _size }
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50 numops <- { 3 }
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51 name <- { _names get: _opcode }
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52 string <- { name . " " . (string: _ina) . " " . (string: _inb) . " " . (string: _out) . " " . (string: _size) }
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53 recordUsage:at <- :tracker :address {
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54 if: (not: (_ina isInteger?)) {
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55 _ina recordUsage: tracker at: 0 | address withSize: _size
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56 }
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57 _inb recordUsage: tracker at: 0 | address withSize: _size
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58 _out recordUsage: tracker at: 1 | address withSize: _size
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59 }
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60 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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61 newa <- if: (not: (_ina isInteger?)) {
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62 _ina assign: assignments withSource: regSrc
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63 } else: { _ina }
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64 newb <- _inb assign: assignments withSource: regSrc
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65 newout <- _out assign: assignments withSource: regSrc
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66 op3: _opcode a: newa b: newb out: newout size: _size
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67 }
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68 }
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69 }
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70 op2:in:out:size <- :_opcode :_in :_out :_size {
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71 #{
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72 opcode <- { _opcode }
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73 in <- { _in }
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74 out <- { _out }
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75 size <- { _size }
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76 numops <- { 2 }
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77 name <- { _names get: _opcode }
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78 string <- { name . " " . (string: _in) . " " . (string: _out) . " " . (string: _size) }
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79 recordUsage:at <- :tracker :address {
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80 if: (not: (_in isInteger?)) {
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81 _in recordUsage: tracker at: 0 | address withSize: _size
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82 }
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83 _out recordUsage: tracker at: 1 | address withSize: _size
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84 }
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85 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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86 newin <- if: (not: (_in isInteger?)) {
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87 _in assign: assignments withSource: regSrc
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88 } else: { _in }
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89 newout <- _out assign: assignments withSource: regSrc
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90 op2: _opcode in: newin out: newout size: _size
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91 }
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92 }
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93 }
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94 op1:arg:size <- :_opcode :_arg :_size {
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95 #{
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96 opcode <- { _opcode }
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97 arg <- { _arg }
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98 size <- { _size }
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99 numops <- { 1 }
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100 name <- { _names get: _opcode }
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101 string <- { name . " " . (string: _arg) . " " . (string: _size) }
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102 recordUsage:at <- :tracker :address {
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103 if: (not: (_arg isInteger?)) {
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104 _arg recordUsage: tracker at: address withSize: _size
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105 }
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106 }
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107 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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108 newarg <- if: (not: (_arg isInteger?)) {
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109 _arg assign: assignments withSource: regSrc
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110 } else: { _arg }
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111 op1: _opcode arg: newarg size: _size
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112 }
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113 }
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114 }
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115
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116 _sizenames <- #["b" "w" "l" "q"]
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117 _size <- :_bytes {
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118 #{
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119 bytes <- { _bytes }
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120 string <- {
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121 idx <- if: _bytes = 8 { 3 } else: { _bytes / 2}
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122 _sizenames get: idx
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123 }
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124 = <- :other {
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125 _bytes = (other bytes)
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126 }
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127 <= <- :other {
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128 _bytes <= (other bytes)
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129 }
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130 >= <- :other {
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131 _bytes >= (other bytes)
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132 }
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133 > <- :other {
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134 _bytes > (other bytes)
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135 }
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136 < <- :other {
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137 _bytes < (other bytes)
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138 }
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139 }
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140 }
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141 byte <- _size: 1
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142 word <- _size: 2
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143 long <- _size: 4
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144 quad <- _size: 8
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145
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146 _retr <- #{
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147 isInteger? <- { false }
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148 register? <- { true }
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149 argument? <- { false }
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150 return? <- { true }
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151 string <- { "retr" }
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152 = <- :other {
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153 (not: (other isInteger?)) && (other register?) && (other return?)
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154 }
189
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155 != <- :other {
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156 not: self = other
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157 }
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158 recordUsage:at:withSize <- :tracker :address :size {
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159 //TODO: Figure out what tracking is necessary here
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160 }
194
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161 assign:withSource <- :assignments :regSrc {
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162 regSrc allocRet
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163 }
185
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164 }
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165
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166 _condnames <- #[
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167 "eq"
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168 "neq"
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169 "ge"
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170 "le"
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171 "gr"
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172 "ls"
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173 "uge"
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174 "ule"
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175 "ugr"
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176 "uls"
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177 ]
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178 condition <- :num {
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179 #{
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180 cc <- { num }
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181 string <- { _condnames get: num }
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182 = <- :other { num = (other cc) }
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183 }
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184 }
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185 _eq <- condition: 0
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186 _neq <- condition: 1
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187 _ge <- condition: 2
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188 _le <- condition: 3
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189 _gr <- condition: 4
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190 _ls <- condition: 5
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191 _uge <- condition: 6
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192 _ule <- condition: 7
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193 _ugr <- condition: 8
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194 _uls <- condition: 9
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195
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196 #{
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197 b <- { byte }
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198 w <- { word }
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199 l <- { long }
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200 q <- { quad }
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201
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202 eq <- { _eq }
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203 neq <- { _neq }
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204
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205 //signed conditions
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206 ge <- { _ge }
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207 le <- { _le }
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208 gr <- { _gr }
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209 ls <- { _ls }
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210
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211 //unsigned conditions
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212 uge <- { _uge }
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213 ule <- { _ule }
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214 ugr <- { _ugr }
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215 uls <- { _uls }
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216
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217
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218 reg <- :num {
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219 #{
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220 isInteger? <- { false }
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221 register? <- { true }
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222 argument? <- { false }
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223 return? <- { false }
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224 regnum <- { num }
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225 string <- { "r" . (string: num) }
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226 = <- :other {
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227 (not: (other isInteger?)) && (other register?) && (not: (other argument?)) && (not: (other return?)) && num = (other regnum)
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228 }
189
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229 != <- :other {
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230 not: self = other
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231 }
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232 recordUsage:at:withSize <- :tracker :address :size {
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233 tracker reg: self usedAt: address withSize: size
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234 }
194
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235 assign:withSource <- :assignments :regSrc {
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236 assignments get: self
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237 }
185
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238 }
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239 }
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240 arg <- :num {
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241 #{
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242 isInteger? <- { false }
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243 register? <- { true }
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244 argument? <- { true }
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245 return? <- { false }
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246 argnum <- { num }
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247 string <- { "a" . (string: num) }
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248 = <- :other {
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249 (not: (other isInteger?)) && (other register?) && (other argument?) && num = (other regnum)
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250 }
189
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251 != <- :other {
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252 not: self = other
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253 }
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254 recordUsage:at:withSize <- :tracker :address :size {
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255 tracker arg: self usedAt: address withSize: size
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256 }
194
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257 assign:withSource <- :assignments :regSrc {
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258 regSrc allocArg: num
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259 }
185
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260 }
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261 }
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262 retr <- { _retr }
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263
189
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264 base:offset <- :_base :_offset {
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265 #{
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266 base <- { _base }
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267 offset <- { _offset }
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268 string <- {
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269 start <- if: _offset = 0 { "" } else: { (string: _offset) }
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270 start . "[" . (string: _base) . "]"
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271 }
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272 recordUsage:at:withSize <- :tracker :address :size {
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273 _base recordUsage: tracker at: address withSize: size
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274 }
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275 }
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276 }
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277
185
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278 add <- :ina inb out size {
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279 op3: _add a: ina b: inb out: out size: size
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280 }
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281
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282 sub <- :ina inb out size {
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283 op3: _sub a: ina b: inb out: out size: size
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284 }
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285
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286 cmp <- :ina inb out size {
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287 op3: _cmp a: ina b: inb out: out size: size
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288 }
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289
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290 and <- :ina inb out size {
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291 op3: _and a: ina b: inb out: out size: size
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292 }
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293
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294 or <- :ina inb out size {
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295 op3: _or a: ina b: inb out: out size: size
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296 }
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297
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298 xor <- :ina inb out size {
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299 op3: _xor a: ina b: inb out: out size: size
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300 }
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301
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302 bnot <- :in out size {
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303 op2: _not in: in out: out size: size
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304 }
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305
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306 sl <- :shift in out size {
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307 op3: _sl a: shift b: in out: out size: size
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308 }
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309
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310 asr <- :shift in out size {
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311 op3: _asr a: shift b: in out: out size: size
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312 }
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313
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314 lsr <- :shift in out size {
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315 op3: _lsr a: shift b: in out: out size: size
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316 }
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317
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318 rol <- :rot in out size {
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319 op3: _rol a: rot b: in out: out size: size
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320 }
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321
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322 ror <- :rot in out size {
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323 op3: _ror a: rot b: in out: out size: size
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324 }
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325
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326 mov <- :in out size {
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327 op2: _mov in: in out: out size: size
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328 }
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329
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330 call:withArgs <- :_target :_args {
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331 #{
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332 opcode <- { _call }
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333 target <- { _target }
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334 args <- { _args }
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335 numops <- { 0 }
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336 name <- { _names get: _call }
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337 string <- {
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338 argstr <- _args map: :el {
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339 string: el
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340 }
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341 name . " " . (string: _target) . " " . (argstr join: " ")
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342 }
189
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343 recordUsage:at <- :tracker :address {
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344 if: (not: (_target isString?)) {
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345 //TODO: use size l for 32-bit targets or an abstract pointer size
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346 _target recordUsage: tracker at: address withSize: q
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347 }
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348 foreach: _args :_ arg {
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349 //TODO: have some mechanism for properly expressing sizes of arguments
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350 arg recordUsage: tracker at: address withSize: q
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351 }
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352 }
200
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353 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
194
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354 newtarget <- if: (_target isString?) { _target } else: {
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355 _target assign: assignments withSource: regSrc
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356 }
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357 newargs <- _args map: :arg {
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358 if: (arg isInteger?) { arg } else: {
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359 arg assign: assignments withSource: regSrc
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360 }
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361 }
200
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362 newcall <- call: newtarget withArgs: newargs
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363 regSrc returnAll
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364 raddress <- address reverse
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365 foreach: (usage liveArgsAt: raddress) :_ arg {
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366 regSrc allocArg: (arg num)
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367 }
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368 foreach: (usage liveRegsAt: raddress) :_ reg {
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369 regSrc allocSpecific: (assignments get: reg)
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370 }
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371 tosave <- regSrc needSaveForCall
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372 if: (tosave length) > 0 {
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373 save: tosave #[newcall]
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374 } else: {
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375 newcall
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376 }
194
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377 }
185
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378 }
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379 }
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380
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381 return <- :val size {
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382 op1: _ret arg: val size: size
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383 }
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384 skipIf <- :_cond _toskip {
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385 #{
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386 opcode <- { _skipif }
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387 toskip <- { _toskip }
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388 cond <- { _cond }
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389 numops <- { 0 }
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390 name <- { _names get: _skipif }
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391 string <- {
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392 block <- (_toskip map: :el { string: el }) join: "\n\t"
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393 if: (_toskip length) > 0 {
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394 block <- "\n\t" . block . "\n"
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395 }
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396 name . " " . (string: _cond) . " {" . block . "}"
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397 }
189
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398 recordUsage:at <- :tracker :address {
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399 foreach: _toskip :idx inst {
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400 inst recordUsage: tracker at: idx | address
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401 }
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402 }
200
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403 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
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diff changeset
404 newskip <- #[]
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diff changeset
405 foreach: _toskip :idx inst {
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diff changeset
406 newskip append: (inst assignRegs: assignments at: idx | address withSource: regSrc andUsage: usage)
194
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407 }
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408 skipIf: _cond newskip
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409 }
200
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diff changeset
410 to2OpInst <- {
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411 skipIf: _cond (to2Op: _toskip)
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diff changeset
412 }
185
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413 }
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414 }
203
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diff changeset
415 save <- :regs :_scope{
195
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416 #{
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417 opcode <- { _save }
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418 numops <- { 0 }
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419 name <- { _names get: _save }
203
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420 tosave <- { regs }
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421 scope <- { _scope }
195
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422 string <- {
203
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423 block <- _scope join: "\n\t"
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diff changeset
424 if: (_scope length) > 0 {
195
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425 block <- "\n\t" . block . "\n"
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426 }
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diff changeset
427 name . " " . (regs join: " ") . " {" . block . "}"
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diff changeset
428 }
200
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diff changeset
429 to2OpInst <- {
203
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diff changeset
430 save: regs (to2Op: _scope)
200
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diff changeset
431 }
195
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diff changeset
432 }
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diff changeset
433 }
185
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diff changeset
434
189
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diff changeset
435 allocRegs:withSource <- :instarr:regSrc {
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diff changeset
436 _regMap <- dict linear
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diff changeset
437 _argMap <- dict linear
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diff changeset
438
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diff changeset
439 _usageTracker <- :_firstUsage {
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diff changeset
440 #{
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diff changeset
441 firstUsage <- _firstUsage
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diff changeset
442 lastUsage <- _firstUsage
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diff changeset
443 useCount <- 0
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diff changeset
444 maxSize <- byte
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diff changeset
445 usedAt:withSize <- :address :size {
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diff changeset
446 useCount <- useCount + 1
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diff changeset
447 lastUsage <- address
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diff changeset
448 if: size > maxSize {
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diff changeset
449 maxSize <- size
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diff changeset
450 }
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diff changeset
451 }
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diff changeset
452 string <- {
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diff changeset
453 "Uses: " . useCount . ", FirstUse: " . (firstUsage join: ":") . ", Last Use: " . (lastUsage join: ":") . ", Max Size: " . maxSize
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diff changeset
454 }
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diff changeset
455 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
456 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
457
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
458 _maxUses <- 0
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
459 liveFrom:to <- :regs :from :to {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
460 live <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
461 foreach: regs :reg usage {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
462 if: ((usage lastUsage) addrGreatEq: from) && ((usage firstUsage) addrLessEq: to) {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
463 live append: reg
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
464 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
465 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
466 live
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
467 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
468 regUsage <- #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
469 reg:usedAt:withSize <- :reg :address :size {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
470 raddress <- address reverse
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
471 usage <- _regMap get: reg elseSet: {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
472 _usageTracker: raddress
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
473 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
474 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
475 if: (usage useCount) > _maxUses {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
476 _maxUses <- usage useCount
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
477 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
478 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
479 arg:usedAt:withSize <- :arg :address :size {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
480 raddress <- address reverse
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
481 usage <- _argMap get: arg elseSet: {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
482 _usageTracker: [0 0]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
483 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
484 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
485 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
486
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
487 liveRegsAt <- :address {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
488 _regMap liveFrom: address to: address
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
489 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
490 liveArgsAt <- :address {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
491 _argMap liveFrom: address to: address
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
492 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
493
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
494 print <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
495 foreach: _regMap :reg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
496 print: (string: reg) . " | " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
497 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
498 foreach: _argMap :arg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
499 print: (string: arg) . " | " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
500 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
501 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
502 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
503 foreach: instarr :idx inst {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
504 inst recordUsage: regUsage at: [idx]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
505 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
506 print: regUsage
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
507
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
508 addrLessEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
509 lesseq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
510 while: { lesseq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
511 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
512 lesseq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
513 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
514 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
515 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
516 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
517 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
518 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
519 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
520 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
521 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
522 lesseq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
523 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
524
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
525 addrGreatEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
526 greateq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
527 while: { greateq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
528 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
529 greateq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
530 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
531 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
532 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
533 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
534 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
535 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
536 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
537 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
538 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
539 greateq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
540 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
541
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
542 _assignments <- dict linear
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
543 curuses <- _maxUses
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
544 while: { curuses > 0 && (_assignments length) < (_regMap length) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
545 foreach: _regMap :reg usage {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
546 if: (usage useCount) = curuses {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
547 liveArgs <- _argMap liveFrom: (usage firstUsage) to: (usage lastUsage)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
548 foreach: liveArgs :_ arg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
549 regSrc allocArg: (arg num)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
550 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
551
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
552 liveRegs <- _regMap liveFrom: (usage firstUsage) to: (usage lastUsage)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
553 print: (string: reg) . " | Live: " . (liveRegs join: ", ") . ", Live Args: " . (liveArgs join: ", ") . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
554 foreach: liveRegs :_ reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
555 if: (_assignments contains?: reg) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
556 regSrc allocSpecific: (_assignments get: reg)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
557 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
558 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
559 _assignments set: reg (regSrc alloc: (usage maxSize))
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
560
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
561 regSrc returnAll
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
562 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
563 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
564 curuses <- curuses - 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
565 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
566 print: "\n\nAssignments:\n\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
567 foreach: _assignments :reg assign {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
568 print: (string: reg) . " = " . assign . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
569 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
570
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
571 withassign <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
572 foreach: instarr :idx inst {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
573 withassign append: (inst assignRegs: _assignments at: [idx] withSource: regSrc andUsage: regUsage)
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
574 }
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
575 psave <- regSrc needSaveProlog
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
576 if: (psave length) > 0 {
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
577 withassign <- #[save: psave withassign]
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
578 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
579 withassign
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
580 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
581
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
582 //used to convert IL to a format suitable for a 2-operand architecture
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
583 //should be run after register allocation (I think....)
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
584 to2Op <- :instarr {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
585 instarr fold: #[] with: :newarr inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
586 if: (inst numops) = 3 {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
587 if: (inst inb) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
588 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
589 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
590 if: (inst commutative?) && (inst ina) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
591 newarr append: (op2: (inst opcode) in: (inst inb) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
592 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
593 newarr append: (mov: (inst inb) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
594 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
595 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
596 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
597 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
598 if: (inst numops) = 2 && (inst opcode) != _mov {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
599 if: (inst in) != (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
600 newarr append: (mov: (inst in) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
601 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
602 newarr append: (op1: (inst opcode) val: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
603 } else: {
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
604 if: (inst opcode) = _skipif || (inst opcode) = _save {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
605 newarr append: (inst to2OpInst)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
606 } else: {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
607 newarr append: inst
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
608 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
609 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
610 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
611 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
612 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
613
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
614 toBackend <- :program :backend {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
615 prepped <- program map: :fun {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
616 backend adjustIL: fun
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
617 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
618 labels <- prepped map: :_ {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
619 backend label
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
620 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
621 outprog <- #[]
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
622 foreach: prepped :name instarr {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
623 outprog append: (labels get: name)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
624 foreach: instarr :_ inst {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
625 backend convertIL: inst to: outprog withLabels: labels
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
626 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
627 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
628 outprog
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
629 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
630
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
631 main <- {
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
632 prog <- dict linear
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
633
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
634 fib <- #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
635 sub: 2 (arg: 0) (reg: 0) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
636 skipIf: ge #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
637 return: 1 q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
638 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
639 call: "fib" withArgs: #[reg: 0]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
640 mov: retr (reg: 1) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
641 add: 1 (reg: 0) (reg: 2) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
642 call: "fib" withArgs: #[reg: 2]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
643 add: retr (reg: 1) (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
644 return: (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
645 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
646 print: "Original:\n\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
647 foreach: fib :idx inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
648 print: (string: inst) . "\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
649 }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
650 prog set: "fib" fib
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
651
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
652 mprog <- prog toBackend: x86
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
653 ba <- bytearray executableFromBytes: mprog
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
654 res <- ba runWithArg: 30u64
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
655 print: (string: res) . "\n"
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
656 0
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
657 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
658 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
659 }