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Fix il and llcompile modules enough that it actually attempts to run the compiled program
author Michael Pavone <pavone@retrodev.com>
date Wed, 15 Apr 2015 20:08:38 -0700
parents a3b06d53bcb9
children 0b4d4f06bf91
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1 {
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2 regnames <- #["rax" "rcx" "rdx" "rbx" "rsp" "rbp" "rsi" "rdi" "r8" "r9" "r10" "r11" "r12" "r13" "r14" "r15"]
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3 uppernames <- #["ah" "ch" "dh" "bh"]
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4 ireg <- :regnum {
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5 #{
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6 num <- { regnum }
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7 reg <- { regnum and 7u8}
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8 string <- { regnames get: regnum }
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9 rm <- :tail { reg or 0xC0u8 | tail }
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10 validforSize? <- :size { true }
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11 isInteger? <- { false }
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12 isString? <- { false }
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13 register? <- { true }
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14 label? <- { false }
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15 upper? <- { false }
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16 needsRex? <- { regnum >= 8u8 }
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17 rexBitReg <- {
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18 if: needsRex? {
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19 4u8
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20 } else: {
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21 0u8
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22 }
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23 }
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24 rexBitRM <- {
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25 if: needsRex? {
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26 1u8
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27 } else: {
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28 0u8
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29 }
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30 }
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31 = <- :other {
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32 (not: (other isInteger?)) && (other register?) && (not: (other upper?)) && regnum = (other num)
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33 }
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34 }
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35 }
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36
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37 upper <- :regnum {
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38 #{
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39 num <- { regnum }
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40 reg <- { regnum }
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41 string <- { uppernames get: regnum - 4 }
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42 rm <- :tail { regnum or 0xC0u8 | tail }
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43 validforSize? <- :size {
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44 size = byte
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45 }
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46 isInteger? <- { false }
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47 register? <- { true }
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48 label? <- { false }
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49 upper? <- { true }
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50 needsRex? <- { false }
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51 = <- :other {
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52 (not: (other isInteger?)) && (other register?) && (other upper?) && regnum = (other num)
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53 }
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54 }
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55 }
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56 fakesrc <- #{
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57 needsRex? <- { false }
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58 rexBitReg <- { 0u8 }
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59 rexBitRM <- { 0u8 }
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60 }
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61 _size <- :s {
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62 #{
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63 num <- { s }
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64 = <- :other {
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65 s = (other num)
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66 }
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67 > <- :other {
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68 s > (other num)
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69 }
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70 >= <- :other {
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71 s >= (other num)
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72 }
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73 < <- :other {
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74 s < (other num)
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75 }
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76 <= <- :other {
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77 s <= (other num)
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78 }
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79 needsRex? <- { s = 3 }
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80 rexBit <- {
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81 if: needsRex? {
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82 0x08u8
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83 } else: {
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84 0u8
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85 }
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86 }
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87 }
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88 }
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89 byte <- _size: 0
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90 word <- _size: 1
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91 dword <- _size: 2
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92 qword <- _size: 3
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93
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94 condition <- :num {
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95 #{
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96 cc <- { num }
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97 }
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98 }
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99 _o <- condition: 0u8
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100 _no <- condition: 1u8
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101 _c <- condition: 2u8
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102 _nc <- condition: 3u8
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103 _z <- condition: 4u8
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104 _nz <- condition: 5u8
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105 _be <- condition: 6u8
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106 _nbe <- condition: 7u8
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107 _s <- condition: 8u8
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108 _ns <- condition: 9u8
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109 _p <- condition: 10u8
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110 _np <- condition: 11u8
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111 _l <- condition: 12u8
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112 _nl <- condition: 13u8
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113 _le <- condition: 14u8
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114 _nle <- condition: 15u8
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115
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116
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117 size_bit <- :opcode size {
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118 if: size = byte {
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119 opcode
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120 } else: {
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121 opcode or 1u8
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122 }
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123 }
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124 opex <- :val {
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125 #{
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126 reg <- { val }
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127 string <- { "opex " . val}
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128 }
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129 }
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130
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131 mod_rm:withTail <- :register regmem :end {
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132 list <- regmem rm: end
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133 (list value) or ( lshift: (register reg) by: 3u8) | (list tail)
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134 }
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135
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136 mod_rm <- :reg rm {
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137 mod_rm: reg rm withTail: []
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138 }
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139
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140 int_op:withTail <- :value size :tail {
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141 if: size >= dword {
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142 tail <- (uint8: (rshift: value by: 16u64)) | (uint8: (rshift: value by: 24u64)) | tail
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143 }
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144 if: size >= word {
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145 tail <- (uint8: (rshift: value by: 8u64)) | tail
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146 }
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147 (uint8: value) | tail
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148 }
175
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149 int_op <- :value size {
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150 int_op: value size withTail: []
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151 }
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152 //used for mov instructions that support 64-bit immediate operands/offsets
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153 int_op64 <- :value size {
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154 tail <- []
183
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155 value <- uint64: value
175
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156 if: size = qword {
179
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157 tail <- (uint8: (rshift: value by: 32u64)) | (uint8: (rshift: value by: 40u64)) | (uint8: (rshift: value by: 48u64)) | (uint8: (rshift: value by: 56u64)) | tail
175
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158 }
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159 int_op: value size withTail: tail
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160 }
174
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161
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162 prefix:withInstruction <- :reg rm size :inst {
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163 if: size = word {
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164 inst <- 0x66u8 | inst
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165 }
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166 if: (size needsRex?) || (reg needsRex?) || (rm needsRex?) {
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167 rex <- 0x40u8 or (size rexBit) or (reg rexBitReg) or (rm rexBitRM)
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168 inst <- rex | inst
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169 }
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170 inst
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171 }
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172
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173 _rax <- ireg: 0u8
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174 _rcx <- ireg: 1u8
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175 _rdx <- ireg: 2u8
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176 _rbx <- ireg: 3u8
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177 _rsp <- ireg: 4u8
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178 _rbp <- ireg: 5u8
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179 _rsi <- ireg: 6u8
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180 _rdi <- ireg: 7u8
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181 _r8 <- ireg: 8u8
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182 _r9 <- ireg: 9u8
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183 _r10 <- ireg: 10u8
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184 _r11 <- ireg: 11u8
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185 _r12 <- ireg: 12u8
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186 _r13 <- ireg: 13u8
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187 _r14 <- ireg: 14u8
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188 _r15 <- ireg: 15u8
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189 _ah <- upper: 4u8
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190 _ch <- upper: 5u8
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191 _dh <- upper: 6u8
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192 _bh <- upper: 7u8
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193
193
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194 //AMD64 convention
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195 _argregs <- #[
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196 _rdi
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197 _rsi
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198 _rdx
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199 _rcx
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200 _r8
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201 _r9
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202 ]
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203 _calleesave <- #[
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204 _rbx
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205 _rbp
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206 _r12
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207 _r13
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208 _r14
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209 _r15
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210 ]
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211 _tempregs <- #[
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212 _r10
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213 _r11
194
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214 //TODO: Add rax back in once there's logic in il to properly
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215 //allocate it for the instances in which it's live
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216 //_rax
193
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217 ]
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218
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219
180
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220 inst <- :ilist {
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221 #{
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222 length <- { ilist length }
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223 flattenTo:at <- :dest :idx {
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224 ilist fold: idx with: :idx byte {
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225 dest set: idx byte
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226 idx + 1
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227 }
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228 }
348
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229 string <- { (ilist map: :el { hex: el}) join: " "}
180
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230 }
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231 }
204
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232 multiInst <- :instarr {
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233 #{
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234 length <- {
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235 instarr fold: 0 with: :acc inst {
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236 acc + (inst length)
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237 }
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238 }
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239 flattenTo:at <- :dest :idx {
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240 instarr fold: idx with: :idx inst {
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241 inst flattenTo: dest at: idx
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242 }
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243 }
348
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244 string <- {
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245 (instarr map: :inst {
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246 (inst map: :el { hex: el}) join: " "
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247 }) join: "\n"
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248 }
204
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249 }
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250 }
180
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251
175
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252 op:withCode:withImmed:withOpEx <- :src dst size :normal :immed :myopex {
174
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253 reg <- src
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254 rm <- dst
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255 base <- if: (src isInteger?) {
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256 reg <- fakesrc
175
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257 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
174
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258 } else: {
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259 if: (src register?) {
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260 (size_bit: normal size) | (mod_rm: src dst)
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261 } else: {
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262 reg <- dst
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263 rm <- src
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264 (size_bit: normal or 0x02u8 size) | (mod_rm: dst src)
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265 }
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266 }
180
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267 inst: (prefix: reg rm size withInstruction: base)
174
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268 }
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269
175
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270 op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt {
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271 reg <- src
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272 rm <- dst
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273 if: (src isInteger?) {
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274 reg <- fakesrc
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275 base <- if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) {
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276 byteExt | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)])
175
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277 } else: {
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278 if: dst = _rax {
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279 (size_bit: immedRax size) | (int_op: src size)
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280 } else: {
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281 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
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282 }
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283 }
180
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284 inst: (prefix: reg rm size withInstruction: base)
175
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285 } else: {
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286 op: src dst size withCode: normal withImmed: immed withOpEx: myopex
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287 }
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288 }
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289
204
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290 shiftRot:withOpEx <- :amount dst size :myopex {
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291 opcode <- 0u8
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292 tail <- []
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293 pre <- #[]
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294 post <- #[]
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295 base <- if: (amount isInteger?) {
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296 if: amount = 1 {
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297 opcode <- 0xD0u8
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298 } else: {
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299 opcode <- 0xC0u8
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300 tail <- [uint8: amount]
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301 }
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302 } else: {
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303 opcode <- 0xD2u8
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304 if: (not: _rcx = amount) {
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305 pre <- #[
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306 x86 push: _rcx
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307 x86 mov: amount _rcx byte
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308 ]
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309 post <- #[
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310 x86 pop: _rcx
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311 ]
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312 }
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313 }
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314 bytes <- prefix: fakesrc dst withInstruction: (size_bit: 0xC0u8 size) | (mod_rm: (opex: myopex) dst withTail: tail)
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315 myinst <- inst: bytes
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316 if: (pre length) > 0 {
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317 pre append: myinst
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318 foreach: post :_ inst {
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319 pre append: inst
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320 }
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321 multiInst: pre
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322 } else: {
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323 myinst
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324 }
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325 }
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326
183
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327 _jmprel <- :op jmpDest {
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328 }
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329
174
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330 #{
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331 rax <- { _rax }
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332 rcx <- { _rcx }
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333 rdx <- { _rdx }
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334 rbx <- { _rbx }
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335 rsp <- { _rsp }
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336 rbp <- { _rbp }
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337 rsi <- { _rsi }
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338 rdi <- { _rdi }
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339 r8 <- { _r8 }
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340 r9 <- { _r9 }
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341 r10 <- { _r10 }
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342 r11 <- { _r11 }
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343 r12 <- { _r12 }
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344 r13 <- { _r13 }
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345 r14 <- { _r14 }
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346 r15 <- { _r15 }
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347 ah <- { _ah }
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348 ch <- { _ch }
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349 dh <- { _dh }
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350 bh <- { _bh }
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351
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352 b <- { byte }
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353 w <- { word }
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354 d <- { dword }
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355 q <- { qword }
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356
183
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357 o <- { _o }
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358 no <- { _no }
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359 c <- { _c }
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360 nc <- { _nc }
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361 ae <- { _nc }
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362 z <- { _z }
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363 e <- { _z }
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364 nz <- { _nz }
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365 ne <- { _nz }
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366 be <- { _be }
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367 nbe <- { _nbe }
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368 a <- { _nbe }
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369 s <- { _s }
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370 ns <- { _ns }
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371 p <- { _p }
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372 pe <- { _p }
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373 np <- { _np }
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374 po <- { _np }
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375 l <- { _l }
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376 nl <- { _nl }
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377 ge <- { _nl }
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378 le <- { _le }
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379 nle <- { _nle }
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380 g <- { _nle }
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381
174
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382 add <- :src dst size {
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383 op: src dst size withCode: 0u8 withImmed: 0x80u8 withImmedRax: 0x04u8 withOpEx: 0u8 withByteExtend: 0x83u8
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384 }
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385
175
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386 sub <- :src dst size {
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387 op: src dst size withCode: 0x28u8 withImmed: 0x80u8 withImmedRax: 0x2Cu8 withOpEx: 5u8 withByteExtend: 0x83u8
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388 }
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389
204
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diff changeset
390 cmp <- :src dst size {
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diff changeset
391 op: src dst size withCode: 0x38u8 withImmed: 0x80u8 withImmedRax: 0x3Cu8 withOpEx: 7u8 withByteExtend: 0x83u8
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392 }
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393
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diff changeset
394 and <- :src dst size {
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diff changeset
395 op: src dst size withCode: 0x20u8 withImmed: 0x80u8 withImmedRax: 0x24u8 withOpEx: 4u8 withByteExtend: 0x83u8
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diff changeset
396 }
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diff changeset
397
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diff changeset
398 or <- :src dst size {
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diff changeset
399 op: src dst size withCode: 0x08u8 withImmed: 0x80u8 withImmedRax: 0x0Cu8 withOpEx: 1u8 withByteExtend: 0x83u8
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diff changeset
400 }
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diff changeset
401
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diff changeset
402 xor <- :src dst size {
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diff changeset
403 op: src dst size withCode: 0x30u8 withImmed: 0x80u8 withImmedRax: 0x34u8 withOpEx: 6u8 withByteExtend: 0x83u8
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diff changeset
404 }
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diff changeset
405
175
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diff changeset
406 mov <- :src dst size {
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diff changeset
407 rm <- dst
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diff changeset
408 if: (src isInteger?) && (dst register?) {
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diff changeset
409 opval <- if: size = byte { 0xB0u8 } else: { 0xB8u8 }
183
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diff changeset
410 base <- opval or (dst reg) | (int_op64: src size)
180
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
411 inst: (prefix: fakesrc rm size withInstruction: base)
175
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diff changeset
412 } else: {
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diff changeset
413 op: src dst size withCode: 0x88u8 withImmed: 0xC6u8 withOpEx: 0u8
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414 }
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diff changeset
415 }
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
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parents: 174
diff changeset
416
204
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diff changeset
417 shl <- :shift dst size {
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diff changeset
418 shiftRot: shift dst size withOpEx: 4u8
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diff changeset
419 }
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
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parents: 203
diff changeset
420
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parents: 203
diff changeset
421 shr <- :shift dst size {
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parents: 203
diff changeset
422 shiftRot: shift dst size withOpEx: 5u8
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parents: 203
diff changeset
423 }
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Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
424
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
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parents: 203
diff changeset
425 sar <- :shift dst size {
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diff changeset
426 shiftRot: shift dst size withOpEx: 7u8
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parents: 203
diff changeset
427 }
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
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parents: 203
diff changeset
428
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
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parents: 203
diff changeset
429 rol <- :shift dst size {
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
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parents: 203
diff changeset
430 shiftRot: shift dst size withOpEx: 0u8
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parents: 203
diff changeset
431 }
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parents: 203
diff changeset
432
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parents: 203
diff changeset
433 ror <- :shift dst size {
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parents: 203
diff changeset
434 shiftRot: shift dst size withOpEx: 1u8
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parents: 203
diff changeset
435 }
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parents: 203
diff changeset
436
180
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diff changeset
437 ret <- { inst: [ 0xC3u8 ] }
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diff changeset
438
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diff changeset
439 label <- {
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diff changeset
440 _offset <- -1
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diff changeset
441 _forwardRefs <- #[]
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diff changeset
442 #{
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diff changeset
443 length <- { 0 }
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diff changeset
444 hasOffset? <- { _offset >= 0 }
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diff changeset
445 offset <- { _offset }
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diff changeset
446 register? <- { false }
181
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diff changeset
447 label? <- { true }
180
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diff changeset
448 flattenTo:at <- :dest :idx {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
449 if: (not: hasOffset?) {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
450 _offset <- idx
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diff changeset
451 foreach: _forwardRefs :idx fun {
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diff changeset
452 fun: _offset
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diff changeset
453 }
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
454 _forwardRefs <- #[]
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
455 }
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
456 idx
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diff changeset
457 }
348
a840e9a068a2 Get sample builtin to il module working again
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diff changeset
458 string <- { "label: " . _offset }
180
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
459 withOffset:else <- :fun :elsefun {
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
460 if: hasOffset? {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
461 fun: _offset
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diff changeset
462 } else: {
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
463 _forwardRefs append: fun
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diff changeset
464 elsefun:
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parents: 179
diff changeset
465 }
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parents: 179
diff changeset
466 }
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
467 }
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
468 }
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
469
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
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diff changeset
470 jmp <- :jmpDest {
181
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diff changeset
471 if: (jmpDest label?) {
180
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
472 _size <- -1
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
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diff changeset
473 #{
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
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diff changeset
474 length <- { if: _size < 0 { 5 } else: { _size } }
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
475 flattenTo:at <- :dest :idx {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
476 jmpDest withOffset: :off {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
477 if: _size < 0 {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
478 rel <- off - (idx + 2)
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
479 if: rel < 128 && rel >= -128 {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
480 _size <- 2
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diff changeset
481 } else: {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
482 rel <- rel - 2
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
483 if: rel < 32768 && rel >= -32768 {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
484 _size <- 4
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diff changeset
485 } else: {
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
486 _size <- 5
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Mike Pavone <pavone@retrodev.com>
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diff changeset
487 }
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Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
488 }
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Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
489 }
270d31c6c4cd Add support for jmps and labels in x86 module
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diff changeset
490 rel <- off - (idx + _size)
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parents: 179
diff changeset
491 if: _size = 2 {
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diff changeset
492 dest set: idx 0xEBu8
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diff changeset
493 dest set: (idx + 1) (uint8: rel)
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parents: 179
diff changeset
494 } else: {
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parents: 179
diff changeset
495 if: _size = 4 {
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parents: 179
diff changeset
496 dest set: idx 0x66u8
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
497 dest set: (idx + 1) 0xE9u8
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parents: 179
diff changeset
498 dest set: (idx + 2) (uint8: rel)
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Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
499 dest set: (idx + 3) (uint8: (rshift: rel by: 8))
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
500 } else: {
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
501 dest set: idx 0xE9u8
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
502 dest set: (idx + 1) (uint8: rel)
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
503 dest set: (idx + 2) (uint8: (rshift: rel by: 8))
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
504 dest set: (idx + 3) (uint8: (rshift: rel by: 16))
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
505 dest set: (idx + 4) (uint8: (rshift: rel by: 24))
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
506 }
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
507 }
270d31c6c4cd Add support for jmps and labels in x86 module
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parents: 179
diff changeset
508 } else: {
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
509 _size <- 5
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
510 }
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
511 idx + _size
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
512 }
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
513 string <- {
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
514 "jmp " . jmpDest
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
515 }
180
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
516 }
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
517 } else: {
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
518 inst: 0xFFu8 | (mod_rm: (opex: 5u8) jmpDest)
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
519 }
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
520 }
175
20b6041a8b23 Small refactor in x86 module. Added a few more instructions.
Mike Pavone <pavone@retrodev.com>
parents: 174
diff changeset
521
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
522 jcc <- :cond jmpDest {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
523 _size <- -1
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
524 #{
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
525 length <- { if: _size < 0 { 5 } else: { _size } }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
526 flattenTo:at <- :dest :idx {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
527 jmpDest withOffset: :off {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
528 if: _size < 0 {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
529 rel <- off - (idx + 2)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
530 if: rel < 128 && rel >= -128 {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
531 _size <- 2
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
532 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
533 _size <- 6
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
534 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
535 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
536 rel <- off - (idx + _size)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
537 if: _size = 2 {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
538 dest set: idx 0x70u8 or (cond cc)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
539 dest set: (idx + 1) (uint8: rel)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
540 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
541 dest set: idx 0x0Fu8
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
542 dest set: (idx + 1) 0x80u8 or (cond cc)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
543 dest set: (idx + 2) (uint8: rel)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
544 dest set: (idx + 3) (uint8: (rshift: rel by: 8))
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
545 dest set: (idx + 4) (uint8: (rshift: rel by: 16))
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
546 dest set: (idx + 5) (uint8: (rshift: rel by: 24))
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
547 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
548 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
549 _size <- 6
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parents: 181
diff changeset
550 }
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parents: 181
diff changeset
551 idx + _size
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parents: 181
diff changeset
552 }
348
a840e9a068a2 Get sample builtin to il module working again
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parents: 315
diff changeset
553 string <- {
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parents: 315
diff changeset
554 "jcc " . jmpDest
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parents: 315
diff changeset
555 }
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
556 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
557 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
558
181
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
559 call <- :callDest {
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
560 if: (callDest label?) {
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
561 #{
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
562 length <- { 5 }
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
563 flattenTo:at <- :dest :idx {
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
564 dest set: idx 0xE8u8
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parents: 180
diff changeset
565 callDest withOffset: :off {
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parents: 180
diff changeset
566 rel <- off - (idx + 5)
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parents: 180
diff changeset
567 dest set: (idx + 1) (uint8: rel)
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parents: 180
diff changeset
568 dest set: (idx + 2) (uint8: (rshift: rel by: 8))
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parents: 180
diff changeset
569 dest set: (idx + 3) (uint8: (rshift: rel by: 16))
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
570 dest set: (idx + 4) (uint8: (rshift: rel by: 24))
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
571 } else: {
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
572 }
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
573 idx + 5
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
574 }
348
a840e9a068a2 Get sample builtin to il module working again
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parents: 315
diff changeset
575 string <- {
a840e9a068a2 Get sample builtin to il module working again
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parents: 315
diff changeset
576 "call " . callDest
a840e9a068a2 Get sample builtin to il module working again
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parents: 315
diff changeset
577 }
181
f188723c15b4 Add call instruction to x86 module
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
578 }
f188723c15b4 Add call instruction to x86 module
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
579 } else: {
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parents: 180
diff changeset
580 inst: 0xFFu8 | (mod_rm: (opex: 2u8) callDest)
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
581 }
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Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
582 }
174
8b5829372ad1 Initial work on x86 instruction encoding module
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parents:
diff changeset
583
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
584 push <- :src {
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parents: 181
diff changeset
585 if: (src isInteger?) {
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parents: 181
diff changeset
586 if: src < 128 && src > -128 {
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parents: 181
diff changeset
587 inst: 0x6Au8 | (uint8: src)
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parents: 181
diff changeset
588 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
589 inst: 0x68u8 | (uint8: src) | (uint8: (rshift: src by: 8)) | (uint8: (rshift: src by: 16)) | (uint8: (rshift: src by: 24))
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
590 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
591 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
592 base <- if: (src register?) {
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parents: 181
diff changeset
593 [0x50u8 or (src reg)]
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
594 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
595 0xFFu8 | (mod_rm: (opex: 6u8) src)
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parents: 181
diff changeset
596 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
597 inst: (prefix: fakesrc src d withInstruction: base)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
598 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
599 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
600
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
601 pop <- :dst {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
602 base <- if: (dst register?) {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
603 [0x58u8 or (dst reg)]
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
604 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
605 0x8Fu8 | (mod_rm: (opex: 0u8) dst)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
606 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
607 inst: (prefix: fakesrc dst d withInstruction: base)
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
608 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
609
204
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
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parents: 203
diff changeset
610 bnot <- :dst size {
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
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parents: 203
diff changeset
611 base <- (size_bit: 0xF6u8 size) | (mod_rm: (opex: 2u8) dst)
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parents: 203
diff changeset
612 inst: (prefix: fakesrc dst size withInstruction: base)
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parents: 203
diff changeset
613 }
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parents: 203
diff changeset
614
193
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parents: 183
diff changeset
615 //TODO: support multiple calling conventions
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parents: 183
diff changeset
616 regSource <- {
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diff changeset
617 _used <- 0
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parents: 183
diff changeset
618 _usedAllTime <- 0
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diff changeset
619 _nextStackOff <- 0
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parents: 183
diff changeset
620 _findUnused <- :size reglists{
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diff changeset
621 found <- -1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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diff changeset
622 foundlist <- -1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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diff changeset
623 curlist <- 0
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diff changeset
624 ll <- reglists length
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diff changeset
625 while: { found < 0 && curlist < ll } do: {
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parents: 183
diff changeset
626 cur <- 0
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parents: 183
diff changeset
627 regs <- reglists get: curlist
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
628 len <- regs length
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
629 while: { found < 0 && cur < len } do: {
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
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parents: 194
diff changeset
630 bit <- lshift: 1 by: ((regs get: cur) num)
193
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parents: 183
diff changeset
631 if: (_used and bit) = 0 {
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parents: 183
diff changeset
632 found <- cur
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
633 foundlist <- regs
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parents: 183
diff changeset
634 _used <- _used or bit
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parents: 183
diff changeset
635 _usedAllTime <- _usedAllTime or bit
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parents: 183
diff changeset
636 }
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parents: 183
diff changeset
637 cur <- cur + 1
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parents: 183
diff changeset
638 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
639 curlist <- curlist + 1
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parents: 183
diff changeset
640 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
641 if: found >= 0 {
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parents: 183
diff changeset
642 foundlist get: found
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
643 } else: {
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parents: 183
diff changeset
644 myoff <- _nextStackOff
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parents: 183
diff changeset
645 _nextStackOff <- _nextStackOff + size
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parents: 183
diff changeset
646 il base: _rsp offset: myoff
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parents: 183
diff changeset
647 }
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parents: 183
diff changeset
648 }
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parents: 183
diff changeset
649 #{
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parents: 183
diff changeset
650 alloc <- :size {
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parents: 183
diff changeset
651 _findUnused: size #[
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parents: 183
diff changeset
652 _calleesave
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parents: 183
diff changeset
653 _tempregs
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parents: 183
diff changeset
654 _argregs
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parents: 183
diff changeset
655 ]
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parents: 183
diff changeset
656 }
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parents: 183
diff changeset
657 //used to allocate a register
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parents: 183
diff changeset
658 //that will be returned before a call
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parents: 183
diff changeset
659 allocTemp <- :size {
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parents: 183
diff changeset
660 _findUnused: size #[
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parents: 183
diff changeset
661 _tempregs
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parents: 183
diff changeset
662 _argregs
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parents: 183
diff changeset
663 _calleesave
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parents: 183
diff changeset
664 ]
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
665 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
666 //allocated the return register
194
30bed95cbb18 Apply register assignments in il module
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parents: 193
diff changeset
667 allocRet <- {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
668 bit <- (lshift: 1 by: (_rax num))
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parents: 183
diff changeset
669 _used <- _used or bit
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parents: 183
diff changeset
670 _usedAllTime <- _usedAllTime or bit
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parents: 183
diff changeset
671 _rax
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parents: 183
diff changeset
672 }
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parents: 183
diff changeset
673 allocArg <- :argnum {
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parents: 183
diff changeset
674 if: argnum < (_argregs length) {
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parents: 183
diff changeset
675 reg <- _argregs get: argnum
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parents: 183
diff changeset
676 bit <- (lshift: 1 by: (reg num))
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parents: 183
diff changeset
677 _used <- _used or bit
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parents: 183
diff changeset
678 _usedAllTime <- _usedAllTime or bit
194
30bed95cbb18 Apply register assignments in il module
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parents: 193
diff changeset
679 reg
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
680 } else: {
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parents: 183
diff changeset
681 il base: _rsp offset: _nextStackOff + 8 * (argnum - (_argregs length))
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parents: 183
diff changeset
682 }
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parents: 183
diff changeset
683 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
684 allocSpecific <- :reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
685 if: (reg register?) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
686 bit <- (lshift: 1 by: (reg num))
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
687 _used <- _used or bit
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
688 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
689 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
690 stackSize <- { _nextStackOff }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
691 return <- :reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
692 _used <- _used and (0xF xor (lshift: 1 by: (reg num)))
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
693 }
198
3606a7cb3999 Fix ireg upper, regSource returnAll and regSource needSaveForCall in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
694 returnAll <- { _used <- 0 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
695 needSaveProlog <- {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
696 retval <- #[]
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
697 foreach: _calleesave :idx reg {
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
698 bit <- lshift: 1 by: (reg num)
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
699 if: (_usedAllTime and bit) != 0 {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
700 retval append: reg
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
701 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
702 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
703 retval
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
704 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
705 needSaveForCall <- {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
706 retval <- #[]
198
3606a7cb3999 Fix ireg upper, regSource returnAll and regSource needSaveForCall in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
707 foreach: #[(_tempregs) (_argregs)] :_ regs {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
708 foreach: regs :_ reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
709 if: (_used and (lshift: 1 by: (reg num))) != 0 {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
710 retval append: reg
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
711 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
712 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
713 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
714 retval
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
715 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
716 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
717 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
718
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
719 adjustIL <- :ilfun {
56b2100d9fff Add code for converting IL into x86 machine code
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parents: 199
diff changeset
720 il to2Op: (il allocRegs: ilfun withSource: regSource)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
721 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
722
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
723 convertIL:to:withLabels:withSaved <- :inst :outarr :labels :saved {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
724 mapSize <- :ilsize {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
725 if: (ilsize bytes) > 2 {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
726 if: (ilsize bytes) = 8 { q } else: { d }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
727 } else: {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
728 if: (ilsize bytes) = 1 { b } else: { w }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
729 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
730 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
731 mapcond <- :ilcond {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
732 ccmap <- #[
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
733 e
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
734 ne
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
735 ge
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
736 le
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
737 g
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
738 l
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
739 ae
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
740 be
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
741 a
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
742 c
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
743 ]
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
744 ccmap get: (ilcond cc)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
745 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
746 opmap <- #[
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
747 { outarr append: (add: (inst in) (inst out) (mapSize: (inst size))) }
204
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
748 { outarr append: (and: (inst in) (inst out) (mapSize: (inst size))) }
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
749 { outarr append: (or: (inst in) (inst out) (mapSize: (inst size))) }
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
750 { outarr append: (xor: (inst in) (inst out) (mapSize: (inst size))) }
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
751 { } //muls
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
752 { } //mulu
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
753 { } //divs
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
754 { } //divu
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
755 { outarr append: (sub: (inst in) (inst out) (mapSize: (inst size))) }
204
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
756 { outarr append: (cmp: (inst in) (inst out) (mapSize: (inst size))) }
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
757 { outarr append: (bnot: (inst arg) (mapSize: (inst size))) }
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
758 { outarr append: (shl: (inst in) (inst out) (mapSize: (inst size))) } //sl
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
759 { outarr append: (sar: (inst in) (inst out) (mapSize: (inst size))) } //asr
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
760 { outarr append: (shr: (inst in) (inst out) (mapSize: (inst size))) } //lsr
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
761 { outarr append: (rol: (inst in) (inst out) (mapSize: (inst size))) }
a8dffa4d4b54 Add support for the rest of the instructions currently defined in the il module in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 203
diff changeset
762 { outarr append: (ror: (inst in) (inst out) (mapSize: (inst size))) }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
763 { outarr append: (mov: (inst in) (inst out) (mapSize: (inst size))) }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
764 {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
765 //call
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
766 arguments <- inst args
350
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
767 arguments foldr: (arguments length) - 1 with: :cur src {
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
768 if: cur < (_argregs length) {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
769 dst <- _argregs get: cur
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
770 if: (not: dst = src) {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
771 //TODO: Handle edge case in which src is a caller saved
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
772 //reg that has been pusehd onto the stack to preserve
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
773 //it across this call
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
774 outarr append: (mov: src dst q)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
775 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
776 } else: {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
777 outarr append: (push: src)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
778 }
350
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
779 cur - 1
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
780 }
350
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
781
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
782 toCall <- inst target
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
783 if: (toCall isString?) {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
784 //TODO: Handle call to undefined label
350
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
785 toCall <- labels get: toCall else: {
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
786 print: "Could not find label " . toCall . "\nDefined labels:\n"
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
787 foreach: labels :key _ {
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
788 print: "\t" . key . "\n"
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
789 }
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
790 false
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
791 }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
792 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
793 outarr append: (call: toCall)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
794 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
795 {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
796 //return
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
797 if: (not: _rax = (inst arg)) {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
798 outarr append: (mov: (inst arg) _rax q)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
799 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
800 foreach: saved :_ reg {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
801 outarr append: (pop: reg)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
802 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
803 outarr append: (ret: )
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
804 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
805 {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
806 //skipIf
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
807 endlab <- label:
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
808 outarr append: (jcc: (mapcond: (inst cond)) endlab)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
809 foreach: (inst toskip) :_ inst {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
810 convertIL: inst to: outarr withLabels: labels withSaved: saved
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
811 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
812 outarr append: endlab
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
813 }
315
f987bb2a1911 WIP native compiler work
Michael Pavone <pavone@retrodev.com>
parents: 204
diff changeset
814 //skipIf:else
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
815 { }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
816 {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
817 //save
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
818 newsave <- []
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
819 foreach: (inst tosave) :_ reg {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
820 outarr append: (push: reg)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
821 newsave <- reg | newsave
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
822 }
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parents: 199
diff changeset
823 foreach: (inst scope) :_ inst {
56b2100d9fff Add code for converting IL into x86 machine code
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parents: 199
diff changeset
824 convertIL: inst to: outarr withLabels: labels withSaved: newsave
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
825 }
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
826 if: ((inst scope) length) = 0 || (((inst scope) get: ((inst scope) length) - 1) opcode) != 18 {
203
56b2100d9fff Add code for converting IL into x86 machine code
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parents: 199
diff changeset
827 foreach: newsave :_ reg {
56b2100d9fff Add code for converting IL into x86 machine code
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parents: 199
diff changeset
828 outarr append: (pop: reg)
56b2100d9fff Add code for converting IL into x86 machine code
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parents: 199
diff changeset
829 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
830 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
831 }
315
f987bb2a1911 WIP native compiler work
Michael Pavone <pavone@retrodev.com>
parents: 204
diff changeset
832 //bool
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
833 { }
203
56b2100d9fff Add code for converting IL into x86 machine code
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parents: 199
diff changeset
834 ]
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
835 print: "Opcode: " . (inst opcode) . "\n"
203
56b2100d9fff Add code for converting IL into x86 machine code
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parents: 199
diff changeset
836 fun <- opmap get: (inst opcode)
56b2100d9fff Add code for converting IL into x86 machine code
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parents: 199
diff changeset
837 fun:
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
838 outarr
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
839 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
840
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
841 convertIL:to:withLabels <- :inst :outarr :labels {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
842 convertIL: inst to: outarr withLabels: labels withSaved: []
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
843 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 199
diff changeset
844
174
8b5829372ad1 Initial work on x86 instruction encoding module
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parents:
diff changeset
845 main <- {
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
846 fib <- label:
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
847 notbase <- label:
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
848 prog <- #[
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
849 fib
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
850 sub: 2 rdi q
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
851 jcc: ge notbase
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
852 mov: 1 rax q
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
853 ret:
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
854
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
855 notbase
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
856 push: rdi
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Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
857 call: fib
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
858 pop: rdi
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
859 push: rax
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
860 add: 1 rdi q
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
861 call: fib
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
862 pop: rdi
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
863 add: rdi rax q
181
f188723c15b4 Add call instruction to x86 module
Mike Pavone <pavone@retrodev.com>
parents: 180
diff changeset
864 ret:
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
865 ]
180
270d31c6c4cd Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents: 179
diff changeset
866
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
867 ba <- bytearray executableFromBytes: prog
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
868 res <- ba runWithArg: 30u64
179
75aca5f87969 A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents: 175
diff changeset
869 print: (string: res) . "\n"
174
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
870 0
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
871 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
872 }
8b5829372ad1 Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
873 }