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Implementation of some of the rotate instructions in new Z80 core
author Michael Pavone <pavone@retrodev.com>
date Thu, 31 Jan 2019 22:41:37 -0800
parents 1648c685083a
children ac809d044cab
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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1 info
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2 prefix z80_
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3 opcode_size 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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parents: 1720
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4 extra_tables cb ed dded fded ddcb fdcb dd fd
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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5 body z80_run_op
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6 include z80_util.c
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7 header z80.h
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8
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9 regs
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10 main 8 b c d e h l f a
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11 alt 8 b' c' d' e' h' l' f' a'
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12 i 8
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13 r 8
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14 iff1 8
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15 iff2 8
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16 imode 8
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17 sp 16
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18 ix 16
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19 iy 16
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20 pc 16
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21 wz 16
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22 nflag 8
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23 last_flag_result 8
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24 pvflag 8
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25 chflags 8
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26 zflag 8
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27 scratch1 16
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28 scratch2 16
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29
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30 flags
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31 register f
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32 S 7 sign last_flag_result.7
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33 Z 6 zero zflag
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34 Y 5 bit-5 last_flag_result.5
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35 H 4 half-carry chflags.3
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36 P 2 parity pvflag
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37 V 2 overflow pvflag
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38 X 3 bit-3 last_flag_result.3
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39 N 1 none nflag
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40 C 0 carry chflags.7
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41
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42
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43 z80_op_fetch
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44 cycles 1
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45 add 1 r r
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46 mov pc scratch1
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47 ocall read_8
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48 add 1 pc pc
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49
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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50 z80_run_op
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51 z80_op_fetch
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52 dispatch scratch1
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53
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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54 11001011 cb_prefix
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55 z80_op_fetch
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56 dispatch scratch1 cb
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57
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58 11011101 dd_prefix
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59 z80_op_fetch
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60 dispatch scratch1 dd
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61
1712
0a9a88b3d061 Fix ED prefix in new Z80 core
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62 11101101 ed_prefix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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63 z80_op_fetch
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64 dispatch scratch1 ed
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65
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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66 11111101 fd_prefix
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67 z80_op_fetch
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68 dispatch scratch1 fd
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69
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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70 dd 11001011 ddcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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71 z80_calc_index ix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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72 cycles 2
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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73 mov pc scratch1
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74 ocall read_8
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75 add 1 pc pc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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76 dispatch scratch1 ddcb
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77
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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78 fd 11001011 fdcb_prefix
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79 z80_calc_index iy
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80 cycles 2
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
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81 mov pc scratch1
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82 ocall read_8
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83 add 1 pc pc
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84 dispatch scratch1 fdcb
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85
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86 z80_check_cond
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87 arg cond 8
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88 local invert 8
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89 switch cond
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90 case 0
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91 meta istrue invert
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92 lnot zflag invert
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93
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94 case 1
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95 meta istrue zflag
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96
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97 case 2
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98 meta istrue invert
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99 not chflags invert
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100 and 0x80 invert invert
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101
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102 case 3
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103 meta istrue invert
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104 and 0x80 invert invert
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105
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106 case 4
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107 meta istrue invert
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108 lnot pvflag invert
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109
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110 case 5
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111 meta istrue pvflag
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112
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113 case 6
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114 meta istrue invert
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115 not last_flag_result invert
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116 and 0x80 invert invert
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117
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118 case 7
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119 meta istrue invert
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120 and 0x80 last_flag_result invert
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121
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122 end
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123
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124 z80_fetch_hl
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125 lsl h 8 scratch1
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126 or l scratch1 scratch1
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127 ocall read_8
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128
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129 z80_store_hl
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130 lsl h 8 scratch2
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131 or l scratch2 scratch2
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132 ocall write_8
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133
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134 z80_fetch_immed
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135 mov pc scratch1
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136 ocall read_8
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137 add 1 pc pc
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138
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139 z80_fetch_immed16
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140 mov pc scratch1
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141 ocall read_8
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142 mov scratch1 wz
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143 add 1 pc pc
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144 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148 or scratch1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
150 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
156 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
157 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
158 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
159
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 01RRR110 ld_from_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 01DDDSSS ld_from_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176 mov main.S main.D
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
178 z80_calc_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
179 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
180 mov index wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
181 z80_fetch_immed
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
182 sext 16 scratch1 scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
183 add scratch1 wz wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
184
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
185 z80_fetch_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
186 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
187 z80_calc_index index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
188 mov wz scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
189 cycles 5
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
190 ocall read_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
191
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
192 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
193 mov wz scratch2
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
194 ocall write_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
195
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196 dd 01RRR110 ld_from_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
197 z80_fetch_index ix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 fd 01RRR110 ld_from_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
201 z80_fetch_index iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204 00RRR110 ld_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 01110RRR ld_to_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212 dd 01110RRR ld_to_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
213 z80_calc_index ix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218 fd 01110RRR ld_to_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
219 z80_calc_index iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 00110110 ld_to_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 00001010 ld_a_from_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 or c scratch2 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 00011010 ld_a_from_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 lsl d 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 or e scratch2 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 00111010 ld_a_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 00000010 ld_a_to_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 00010010 ld_a_to_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253 lsl d 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 or e scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 00110010 ld_a_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 ed 01000111 ld_i_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 mov a i
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 ed 01001111 ld_r_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 mov a r
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 00000001 ld_bc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 00010001 ld_de_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 00100001 ld_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 00110001 ld_sp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 dd 00100001 ld_ix_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 fd 00100001 ld_iy_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309 00101010 ld_hl_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 ed 01001011 ld_bc_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 ed 01011011 ld_de_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 meta high c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 ed 01101011 ld_hl_from_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 ed 01111011 ld_sp_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 dd 00101010 ld_ix_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 fd 00101010 ld_iy_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 00100010 ld_hl_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 mov l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 mov h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 ed 01000011 ld_bc_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 ed 01010011 ld_de_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 ed 01100011 ld_hl_to_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 ed 01110011 ld_sp_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 meta low sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 local sph 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 lsr sp 8 sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 meta high sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 11111001 ld_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 lsl h 8 sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 or l sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 lsr sp 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 11000101 push_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 11010101 push_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 11100101 push_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 11110101 push_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 dd 11100101 push_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 local ixh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 lsr ix 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 fd 11100101 push_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 local iyh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 lsr iy 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 11000001 pop_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 11010001 pop_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 11100001 pop_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 11110001 pop_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481 dd 11100001 pop_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482 local ixh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 lsl ixh 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 or ixh ix ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 fd 11100001 pop_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 local iyh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 lsl iyh 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 or iyh iy iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 11101011 ex_de_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 xchg e l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 xchg d h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 00001000 ex_af_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 xchg a a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 xchg f f'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 11011001 exx
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 xchg b b'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 xchg c c'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 xchg d d'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 xchg e e'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 xchg h h'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 xchg l l'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 11100011 ex_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 xchg l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 add 1 sp wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 xchg h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 10000RRR add_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 add a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
532 dd 10000100 add_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
533 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
534 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
535 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
536
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
537 dd 10000101 add_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
538 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
539 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
540 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
541
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
542 fd 10000100 add_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
543 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
544 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
545 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
546
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
547 fd 10000101 add_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
548 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
549 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
550 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
551
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 10000110 add_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 update_flags SZYHVXN0C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
556
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
557 dd 10000110 add_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
558 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
559 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
560 update_flags SZYHVXN0C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
561
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
562 fd 10000110 add_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
563 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
564 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
565 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 11000110 add_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
572 z80_add16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
573 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
574 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
575 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
576 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
577 add src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
578 update_flags YHXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
579 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
580 lsr hlt 8 h
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
581
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
582 00001001 add_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
583 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
584 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
585 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
586 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
587 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
588 z80_add16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
589
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
590 00011001 add_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
591 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
592 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
593 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
594 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
595 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
596 z80_add16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
597
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
598 00101001 add_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
599 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
600 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
601 z80_add16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
602
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
603 00111001 add_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
604 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
605 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
606 z80_add16_hl sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
607
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
608 dd 00001001 add_ix_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
609 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
610 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
611 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
612 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
613
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
614 dd 00011001 add_ix_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
615 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
616 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
617 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
618 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
619
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
620 dd 00101001 add_ix_ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
621 add ix ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
622 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
623
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
624 dd 00111001 add_ix_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
625 add sp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
626 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
627
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
628 fd 00001001 add_iy_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
629 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
630 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
631 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
632 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
633
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
634 fd 00011001 add_iy_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
635 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
636 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
637 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
638 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
639
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
640 fd 00101001 add_iy_iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
641 add iy iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
642 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
643
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
644 fd 00111001 add_iy_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
645 add sp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
646 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
647
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 10001RRR adc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 adc a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
651
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
652 dd 10001100 adc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
653 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
654 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
655 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
656
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
657 dd 10001101 adc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
658 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
659 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
660 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
661
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
662 fd 10001100 adc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
663 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
664 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
665 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
666
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
667 fd 10001101 adc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
668 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
669 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
670 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672 10001110 adc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
676
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
677 dd 10001110 adc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
678 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
679 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
680 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
681
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
682 fd 10001110 adc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
683 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
684 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
685 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
687 11001110 adc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 update_flags SZYHVXN0C
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
691
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
692 z80_adc16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
693 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
694 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
695 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
696 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
697 adc src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
698 update_flags SZYHVXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
699 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
700 lsr hlt 8 h
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
701
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
702 ed 01001010 adc_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
703 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
704 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
705 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
706 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
707 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
708 z80_adc16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
709
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
710 ed 01011010 adc_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
711 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
712 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
713 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
714 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
715 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
716 z80_adc16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
717
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
718 ed 01101010 adc_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
719 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
720 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
721 z80_adc16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
722
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
723
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
724 ed 01111010 adc_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
725 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
726 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
727 z80_adc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
728
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
729 10010RRR sub_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
730 sub main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
731 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
732
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
733 dd 10010100 sub_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
734 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
735 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
736 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
737
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
738 dd 10010101 sub_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
739 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
740 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
741 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
742
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
743 fd 10010100 sub_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
744 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
745 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
746 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
747
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
748 fd 10010101 sub_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
749 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
750 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
751 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
752
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
753 10010110 sub_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
754 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
755 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
756 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
757
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
758 dd 10010110 sub_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
759 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
760 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
761 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
762
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
763 fd 10010110 sub_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
764 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
765 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
766 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
767
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
768 11010110 sub_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
769 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
770 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
771 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
772
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
773 10011RRR sbc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
774 sbc main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
775 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
776
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
777 dd 10011100 sbc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
778 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
779 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
780 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
781
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
782 dd 10011101 sbc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
783 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
784 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
785 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
786
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
787 fd 10011100 sbc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
788 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
789 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
790 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
791
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
792 fd 10011101 sbc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
793 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
794 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
795 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
796
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
797
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
798 10011110 sbc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
799 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
800 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
801 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
802
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
803 dd 10011110 sbc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
804 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
805 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
806 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
807
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
808 fd 10011110 sbc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
809 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
810 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
811 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
812
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
813 11011110 sbc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
814 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
815 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
816 update_flags SZYHVXN1C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
817
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
818 z80_sbc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
819 arg src 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
820 lsl h 8 hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
821 or l hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
822 add 1 hlt wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
823 sbc src hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
824 update_flags SZYHVXN1C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
825 mov hlt l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
826 lsr hlt 8 h
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
827
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
828 ed 01000010 sbc_hl_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
829 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
830 local bcw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
831 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
832 lsl b 8 bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
833 or c bcw bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
834 z80_sbc16_hl bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
835
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
836 ed 01010010 sbc_hl_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
837 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
838 local dew 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
839 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
840 lsl d 8 dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
841 or e dew dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
842 z80_sbc16_hl dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
843
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
844 ed 01100010 sbc_hl_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
845 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
846 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
847 z80_sbc16_hl hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
848
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
849
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
850 ed 01110010 sbc_hl_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
851 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
852 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
853 z80_sbc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
854
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
855 10100RRR and_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
856 and a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
857 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
858
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
859 dd 10100100 and_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
860 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
861 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
862 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
863
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
864 dd 10100101 and_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
865 and ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
866 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
867
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
868 fd 10100100 and_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
869 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
870 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
871 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
872
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
873 fd 10100101 and_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
874 and iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
875 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
876
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
877 10100110 and_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
878 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
879 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
880 update_flags SZYH1PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
881
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
882 dd 10100110 and_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
883 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
884 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
885 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
886
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
887 fd 10100110 and_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
888 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
889 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
890 update_flags SZYH1PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
891
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
892 11100110 and_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
893 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
894 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
895 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
896
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
897 10110RRR or_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
898 or a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
899 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
900
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
901 dd 10110100 or_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
902 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
903 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
904 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
905
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
906 dd 10110101 or_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
907 or ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
908 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
909
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
910 fd 10110100 or_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
911 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
912 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
913 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
914
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
915 fd 10110101 or_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
916 or iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
917 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
918
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
919 10110110 or_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
920 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
921 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
922 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
923
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
924 dd 10110110 or_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
925 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
926 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
927 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
928
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
929 fd 10110110 or_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
930 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
931 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
932 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
933
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
934 11110110 or_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
935 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
936 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
937 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
938
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
939 10101RRR xor_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
940 xor a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
941 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
942
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
943 dd 10101100 xor_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
944 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
945 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
946 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
947
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
948 dd 10101101 xor_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
949 xor ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
950 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
951
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
952 fd 10101100 xor_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
953 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
954 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
955 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
956
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
957 fd 10101101 xor_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
958 xor iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
959 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
960
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
961 10101110 xor_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
962 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
963 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
964 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
965
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
966 dd 10101110 xor_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
967 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
968 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
969 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
970
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
971 fd 10101110 xor_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
972 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
973 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
974 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
975
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
976 11101110 xor_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
977 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
978 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
979 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
980
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
981 10111RRR cp_reg
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
982 mov main.R last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
983 cmp main.R a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
984 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
985
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
986 dd 10111100 cp_ixh
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
987 lsr ix 8 last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
988 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
989 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
990
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
991 dd 10111101 cp_ixl
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
992 mov ix last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
993 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
994 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
995
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
996 fd 10111100 cp_iyh
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
997 lsr iy 8 last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
998 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
999 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1000
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1001 fd 10111101 cp_iyl
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1002 mov iy last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1003 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1004 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1005
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1006 10111110 cp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1007 z80_fetch_hl
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1008 mov scratch1 last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1009 cmp scratch1 a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1010 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1011
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1012 dd 10111110 cp_ixd
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1013 z80_fetch_index ix
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1014 mov scratch1 last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1015 cmp scratch1 a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1016 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1017
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1018 fd 10111110 cp_iyd
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1019 z80_fetch_index iy
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1020 mov scratch1 last_flag_result
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1021 cmp scratch1 a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1022 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1023
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1024 11111110 cp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1025 z80_fetch_immed
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1026 mov scratch1 last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1027 cmp scratch1 a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1028 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1029
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1030 00RRR100 inc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1031 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1032 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1033
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1034 dd 00100100 inc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1035 add 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1036 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1037
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1038 dd 00101100 inc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1039 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1040 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1041 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1042 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1043 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1044 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1045
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1046 fd 00100100 inc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1047 add 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1048 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1049
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1050 fd 00101100 inc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1051 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1052 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1053 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1054 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1055 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1056 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1057
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1058 00110100 inc_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1059 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1060 z80_fetch_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1061 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1062 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1063 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1064 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1065 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1066 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1067 z80_store_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1068
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1069 dd 00110100 inc_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1070 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1071 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1072 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1073 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1074 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1075 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1076 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1077 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1078 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1079 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1080
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1081 fd 00110100 inc_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1082 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1083 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1084 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1085 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1086 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1087 add 1 tmp tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1088 update_flags SZYHVXN0
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1089 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1090 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1091 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1092
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1093 z80_inc_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1094 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1095 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1096 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1097 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1098 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1099 add 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1100 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1101 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1102
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1103 00000011 inc_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1104 z80_inc_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1105
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1106 00010011 inc_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1107 z80_inc_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1108
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1109 00100011 inc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1110 z80_inc_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1111
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1112 00110011 inc_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1113 add 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1114
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1115 dd 00100011 inc_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1116 add 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1117
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1118 fd 00100011 inc_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1119 add 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1120
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1121 00RRR101 dec_reg
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1122 sub 1 main.R main.R
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1123 update_flags SZYHVXN1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1124
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1125 dd 00100101 dec_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1126 sub 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1127 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1128
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1129 dd 00101101 dec_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1130 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1131 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1132 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1133 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1134 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1135 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1136
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1137 fd 00100101 dec_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1138 sub 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1139 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1140
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1141 fd 00101101 dec_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1142 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1143 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1144 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1145 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1146 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1147 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1148
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1149 00110101 dec_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1150 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1151 #TODO: fix size
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1152 sub 1 scratch1 scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1153 update_flags SZYHVXN1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1154 z80_store_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1155
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1156 dd 00110101 dec_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1157 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1158 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1159 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1160 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1161 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1162 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1163 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1164 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1165 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1166 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1167
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1168 fd 00110101 dec_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1169 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1170 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1171 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1172 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1173 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1174 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1175 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1176 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1177 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1178 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1179
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1180 z80_dec_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1181 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1182 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1183 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1184 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1185 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1186 sub 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1187 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1188 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1189
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1190 00001011 dec_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1191 z80_dec_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1192
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1193 00011011 dec_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1194 z80_dec_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1195
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1196 00101011 dec16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1197 z80_dec_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1198
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1199 00111011 dec_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1200 sub 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1201
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1202 dd 00101011 dec_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1203 sub 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1204
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1205 fd 00101011 dec_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1206 sub 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1207
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1208 00101111 cpl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1209 not a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1210 update_flags YH1XN1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1211
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1212 11101101 neg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1213 neg a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1214 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1215
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1216 00111111 ccf
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1217 xor 0x80 chflags chflags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1218
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1219 00111111 scf
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1220 or 0x80 chflags chflags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1221
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1222 00000000 nop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1223
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1224 11110011 di
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1225 mov 0 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1226 mov 0 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1227 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1228
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1229 11111011 ei
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1230 mov 1 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1231 mov 1 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1232 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1233
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1234 ed 01000110 im0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1235 mov 0 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1236
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1237 ed 01010110 im1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1238 mov 1 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1239
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1240 ed 01011110 im2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1241 mov 2 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1242
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1243 11000011 jp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1244 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1245 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1246
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1247 11CCC010 jp_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1248 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1249 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1250 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1251
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1252 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1253
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1254 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1255
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1256 00011000 jr
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1257 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1258 #TODO: determine if this updates wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1259 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1260 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1261 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1262
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1263 001CC000 jr_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1264 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1265 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1266
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1267 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1268
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1269 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1270 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1271 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1272
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1273 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1274
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1275 00010000 djnz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1276 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1277 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1278 sub 1 b b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1279
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1280 if b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1281
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1282 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1283 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1284 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1285
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1286 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1287
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1288
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1289 11001101 call_uncond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1290 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1291 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1292 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1293 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1294 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1295 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1296 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1297
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1298 11TTT111 rst
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1299 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1300 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1301 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1302 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1303 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1304 lsl T 3 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1305 mov scratch1 pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1306
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1307 11001001 ret
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1308 #TODO: confirm this goes through wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1309 local wzh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1310 meta high wzh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1311 meta low wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1312 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1313 lsl wzh 8 wzh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1314 or wzh wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1315 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1316
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1317 11011011 in_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1318 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1319 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1320 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1321
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1322 ed 01RRR000 in_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1323 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1324 or c scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1325 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1326 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1327
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1328 11010011 out_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1329 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1330 mov scratch1 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1331 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1332 ocall io_write8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1333
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1334 ed 01RRR001 out_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1335 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1336 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1337 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1338 ocall io_write8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1339
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1340 00000111 rlca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1341 rol a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1342 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1343
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1344 00010111 rla
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1345 rlc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1346 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1347
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1348 00001111 rrca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1349 ror a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1350 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1351
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1352 00011111 rra
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1353 rrc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1354 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1355
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1356 cb 00000RRR rlc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1357 rol main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1358 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1359
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1360 cb 00000110 rlc_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1361 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1362 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1363 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1364 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1365 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1366 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1367 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1368
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1369 z80_rlc_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1370 arg tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1371 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1372 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1373 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1374 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1375 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1376 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1377 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1378 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1379
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1380 ddcb 00000110 rlc_ixd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1381 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1382 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1383
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1384 ddcb 00000RRR rlc_ixd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1385 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1386
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1387 fdcb 00000110 rlc_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1388 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1389 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1390
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1391 fdcb 00000RRR rlc_iyd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1392 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1393
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1394 cb 00010RRR rl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1395 rlc main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1396 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1397
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1398 cb 00010110 rl_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1399 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1400 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1401 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1402 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1403 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1404 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1405 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1406
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1407 ddcb 00010110 rl_ixd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1408 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1409 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1410 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1411 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1412 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1413 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1414 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1415 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1416 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1417
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1418 fdcb 00010110 rl_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1419 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1420 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1421 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1422 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1423 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1424 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1425 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1426 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1427 z80_store_index