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annotate gentests.py @ 354:15dd6418fe67

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Initial PSG support. Mostly works, noise channel is borked though.
author Mike Pavone <pavone@retrodev.com>
date Thu, 23 May 2013 23:42:42 -0700
parents 8db584faac4b
children bfbb8613efb4
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #!/usr/bin/env python
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2
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3 def split_fields(line):
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4 parts = []
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5 while line:
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6 field,_,line = line.partition('\t')
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7 parts.append(field.strip())
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8 while line.startswith('\t'):
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9 line = line[1:]
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10 return parts
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11
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12 class Program(object):
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13 def __init__(self, instruction):
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14 self.avail_dregs = {0,1,2,3,4,5,6,7}
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15 self.avail_aregs = {0,1,2,3,4,5,6,7}
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16 instruction.consume_regs(self)
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17 self.inst = instruction
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18
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19 def dirname(self):
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20 return self.inst.name + '_' + self.inst.size
214
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21 def name(self):
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22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
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23
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24 def write_rom_test(self, outfile):
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25 outfile.write('\tdc.l $0, start\n')
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26 needdivzero = self.inst.name.startswith('div')
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27 needchk = self.inst.name.startswith('chk')
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28 for i in xrange(0x8, 0x100, 0x4):
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29 if needdivzero and i == 0x14:
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30 outfile.write('\tdc.l div_zero_handler\n')
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31 elif needchk and i == 0x18:
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32 outfile.write('\tdc.l chk_handler\n')
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33 else:
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34 outfile.write('\tdc.l empty_handler\n')
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35 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n')
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36 if needdivzero:
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37 outfile.write('div_zero_handler:\n')
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38 div_zero_count = self.get_dreg()
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39 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n')
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40 outfile.write('\trte\n')
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41 if needchk:
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42 outfile.write('chk_handler:\n')
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43 chk_count = self.get_dreg()
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44 outfile.write('\taddq #1, ' + str(chk_count) + '\n')
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45 outfile.write('\trte\n')
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46 outfile.write('start:\n\tmove #0, CCR\n')
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47 if needdivzero:
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48 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n')
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49 already = {}
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50 self.inst.write_init(outfile, already)
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51 if 'label' in already:
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52 outfile.write('lbl_' + str(already['label']) + ':\n')
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53 outfile.write('\t'+str(self.inst)+'\n')
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54 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
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55 save_ccr = self.get_dreg()
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56 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
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57 outfile.write('\tmove #$1F, CCR\n')
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58 self.inst.invalidate_dest(already)
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59 self.inst.write_init(outfile, already)
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60 if 'label' in already:
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61 outfile.write('lbl_' + str(already['label']) + ':\n')
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62 outfile.write('\t'+str(self.inst)+'\n')
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63 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
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64 outfile.write('\treset\n')
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65
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66 def consume_dreg(self, num):
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67 self.avail_dregs.discard(num)
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68
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69 def consume_areg(self, num):
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70 self.avail_aregs.discard(num)
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71
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72 def get_dreg(self):
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73 return Register('d', self.avail_dregs.pop())
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74
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75 class Register(object):
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76 def __init__(self, kind, num):
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77 self.kind = kind
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78 self.num = num
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79
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80 def __str__(self):
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81 if self.kind == 'd' or self.kind == 'a':
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82 return self.kind + str(self.num)
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83 return self.kind
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84
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85 def write_init(self, outfile, size, already):
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86 if not str(self) in already:
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87 minv,maxv = get_size_range(size)
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88 val = randint(minv,maxv)
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89 already[str(self)] = val
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90 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
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91
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92 def consume_regs(self, program):
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93 if self.kind == 'd':
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94 program.consume_dreg(self.num)
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95 elif self.kind == 'a':
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96 program.consume_areg(self.num)
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97
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98 def valid_ram_address(address, size='b'):
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99 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
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100
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101 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
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102 return randint(mina, maxa) | 0xE00000
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103
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104 class Indexed(object):
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105 def __init__(self, base, index, index_size, disp):
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106 self.base = base
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107 self.index = index
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108 self.index_size = index_size
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109 self.disp = disp
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110
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111 def write_init(self, outfile, size, already):
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112 if self.base.kind == 'pc':
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113 if str(self.index) in already:
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114 index = already[str(self.index)]
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115 if self.index_size == 'w':
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116 index = index & 0xFFFF
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117 #sign extend index
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118 if index & 0x8000:
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119 index -= 65536
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120 if index > -1024:
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121 index = already[str(self.index)] = randint(-32768, -1024)
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122 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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123 else:
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124 index = already[str(self.index)] = randint(-32768, -1024)
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125 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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126 num = already.get('label', 0)+1
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127 already['label'] = num
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128 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
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129 else:
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130 if self.base == self.index:
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131 if str(self.base) in already:
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132 if not valid_ram_address(already[str(self.base)]*2):
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133 del already[str(self.base)]
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134 self.write_init(outfile, size, already)
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135 return
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136 else:
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137 base = index = already[str(self.base)]
214
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diff changeset
138 else:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
139 base = index = already[str(self.base)] = random_ram_address()/2
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diff changeset
140 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
214
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parents:
diff changeset
141 else:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
142 if str(self.base) in already:
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parents: 214
diff changeset
143 if not valid_ram_address(already[str(self.base)]):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
144 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
145 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
146 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
147 else:
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parents: 214
diff changeset
148 base = already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
149 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
150 base = already[str(self.base)] = random_ram_address()
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
151 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
152 if str(self.index) in already:
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parents: 214
diff changeset
153 index = already[str(self.index)]
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diff changeset
154 if self.index_size == 'w':
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
155 index = index & 0xFFFF
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
156 #sign extend index
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
157 if index & 0x8000:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
158 index -= 65536
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
159 if not valid_ram_address(base + index):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
160 index = already[str(self.index)] = randint(-64, 63)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
161 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
162 else:
214
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parents:
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163 index = already[str(self.index)] = randint(-64, 63)
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parents:
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164 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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parents:
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165 address = base + index + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
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166 if (address & 0xFFFFFF) < 0xE00000:
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Mike Pavone <pavone@retrodev.com>
parents:
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167 if (address & 0xFFFFFF) < 128:
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parents:
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168 self.disp -= (address & 0xFFFFFF)
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parents:
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169 else:
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170 self.disp += 0xE00000-(address & 0xFFFFFF)
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171 address = base + index + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
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172 elif (address & 0xFFFFFF) > 0xFFFFFC:
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parents:
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173 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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174 address = base + index + self.disp
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175 if size != 'b' and address & 1:
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parents:
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176 self.disp = self.disp ^ 1
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177 address = base + index + self.disp
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178 minv,maxv = get_size_range(size)
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179 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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180
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181 def __str__(self):
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parents:
diff changeset
182 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
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parents:
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183
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parents:
diff changeset
184 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
185 self.base.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
186 self.index.consume_regs(program)
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parents:
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187
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parents:
diff changeset
188 class Displacement(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
189 def __init__(self, base, disp):
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parents:
diff changeset
190 self.base = base
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
191 self.disp = disp
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parents:
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192
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
193 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 if self.base.kind == 'pc':
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parents:
diff changeset
195 num = already.get('label', 0)+1
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196 already['label'] = num
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parents:
diff changeset
197 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
198 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
199 if str(self.base) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
200 if not valid_ram_address(already[str(self.base)]):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
201 del already[str(self.base)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
203 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
205 base = already[str(self.base)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
206 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 base = already[str(self.base)] = random_ram_address()
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
208 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210 if (address & 0xFFFFFF) < 0xE00000:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 if (address & 0xFFFFFF) < 0x10000:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 self.disp -= (address & 0xFFFFFF)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 self.disp += 0xE00000-(address & 0xFFFFFF)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
215 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216 elif (address & 0xFFFFFF) > 0xFFFFFC:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
218 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219 if size != 'b' and address & 1:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
220 self.disp = self.disp ^ 1
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
222 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 def __str__(self):
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parents:
diff changeset
226 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
227
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
229 self.base.consume_regs(program)
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parents:
diff changeset
230
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
231 class Indirect(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
232 def __init__(self, reg):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 self.reg = reg
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
234
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 def __str__(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 return '(' + str(self.reg) + ')'
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 if str(self.reg) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
240 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
243 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
245 address = already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
246 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
247 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
248 if size != 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
249 address = address & 0xFFFFFFFE
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
251 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
252 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
253 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
254
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
255 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
256 self.reg.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
257
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
258 class Increment(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
259 def __init__(self, reg):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
260 self.reg = reg
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
261
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
262 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
263 return '(' + str(self.reg) + ')+'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
264
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
266 if str(self.reg) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 if not valid_ram_address(already[str(self.reg)], size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
268 del already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
269 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
270 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
271 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
272 address = already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
273 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
274 address = random_ram_address()
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275 if size != 'b':
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276 address = address & 0xFFFFFFFE
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277 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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278 already[str(self.reg)] = address
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279 minv,maxv = get_size_range(size)
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280 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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281
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282 def consume_regs(self, program):
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283 self.reg.consume_regs(program)
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284
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285 class Decrement(object):
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286 def __init__(self, reg):
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287 self.reg = reg
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parents:
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288
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parents:
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289 def __str__(self):
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parents:
diff changeset
290 return '-(' + str(self.reg) + ')'
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291
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diff changeset
292 def write_init(self, outfile, size, already):
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parents:
diff changeset
293 if str(self.reg) in already:
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294 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
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295 del already[str(self.reg)]
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diff changeset
296 self.write_init(outfile, size, already)
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297 return
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parents:
diff changeset
298 else:
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299 address = already[str(self.reg)]
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300 else:
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301 address = random_ram_address(mina=0xE00004)
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302 if size != 'b':
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303 address = address & 0xFFFFFFFE
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304 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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305 already[str(self.reg)] = address
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306 minv,maxv = get_size_range(size)
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307 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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308
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309 def consume_regs(self, program):
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310 self.reg.consume_regs(program)
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311
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312 class Absolute(object):
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313 def __init__(self, address, size):
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parents:
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314 self.address = address
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315 self.size = size
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parents:
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316
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parents:
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317 def __str__(self):
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parents:
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318 return '(' + str(self.address) + ').' + self.size
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parents:
diff changeset
319
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parents:
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320 def write_init(self, outfile, size, already):
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321 minv,maxv = get_size_range(size)
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parents:
diff changeset
322 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
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parents:
diff changeset
323
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parents:
diff changeset
324 def consume_regs(self, program):
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parents:
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325 pass
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parents:
diff changeset
326
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parents:
diff changeset
327 class Immediate(object):
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parents:
diff changeset
328 def __init__(self, value):
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parents:
diff changeset
329 self.value = value
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parents:
diff changeset
330
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parents:
diff changeset
331 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
332 return '#' + str(self.value)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
333
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parents:
diff changeset
334 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
335 pass
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
336
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parents:
diff changeset
337 def consume_regs(self, program):
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parents:
diff changeset
338 pass
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parents:
diff changeset
339
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parents:
diff changeset
340 all_dregs = [Register('d', i) for i in range(0, 8)]
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parents:
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341 all_aregs = [Register('a', i) for i in range(0, 8)]
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parents:
diff changeset
342 all_indirect = [Indirect(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343 all_predec = [Decrement(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
344 all_postinc = [Increment(reg) for reg in all_aregs]
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parents:
diff changeset
345 from random import randint
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346 def all_indexed():
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parents:
diff changeset
347 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
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parents:
diff changeset
348
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parents:
diff changeset
349 def all_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
350 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
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parents:
diff changeset
351
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parents:
diff changeset
352 def rand_pc_disp():
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parents:
diff changeset
353 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
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parents:
diff changeset
354
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parents:
diff changeset
355 def all_pc_indexed():
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parents:
diff changeset
356 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
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parents:
diff changeset
357
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parents:
diff changeset
358 def rand_abs_short():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
359 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)]
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parents:
diff changeset
360
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parents:
diff changeset
361 def rand_abs_long():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
362 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
363
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parents:
diff changeset
364 def get_size_range(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
365 if size == 'b':
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parents:
diff changeset
366 return (-128, 127)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
367 elif size == 'w':
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parents:
diff changeset
368 return (-32768, 32767)
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parents:
diff changeset
369 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
370 return (-2147483648, 2147483647)
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parents:
diff changeset
371
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
372 def rand_immediate(size):
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parents:
diff changeset
373 minv,maxv = get_size_range(size)
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parents:
diff changeset
374
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parents:
diff changeset
375 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
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parents:
diff changeset
376
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parents:
diff changeset
377 def get_variations(mode, size):
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parents:
diff changeset
378 mapping = {
9126c33cc33c Add test generator, builder and runner
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parents:
diff changeset
379 'd':all_dregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380 'a':all_aregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
381 '(a)':all_indirect,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
382 '-(a)':all_predec,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
383 '(a)+':all_postinc,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
384 '(n,a)':all_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
385 '(n,a,x)':all_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
386 '(n,pc)':rand_pc_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
387 '(n,pc,x)':all_pc_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
388 '(n).w':rand_abs_short,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 '(n).l':rand_abs_long
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
390 }
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
391 if mode in mapping:
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parents:
diff changeset
392 ret = mapping[mode]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
393 if type(ret) != list:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
394 ret = ret()
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
395 return ret
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
396 elif mode == '#n':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
397 return rand_immediate(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398 elif mode.startswith('#(') and mode.endswith(')'):
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parents:
diff changeset
399 inner = mode[2:-1]
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
400 start,sep,end = inner.rpartition('-')
220
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
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parents: 217
diff changeset
401 start,end = int(start),int(end)
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
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parents: 217
diff changeset
402 if end-start > 16:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
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parents: 217
diff changeset
403 return [Immediate(randint(start, end)) for x in range(0,8)]
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
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parents: 217
diff changeset
404 else:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
405 return [Immediate(num) for num in range(start, end+1)]
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
406 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
407 print "Don't know what to do with source type", mode
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
408 return None
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
410 class Inst2Op(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
411 def __init__(self, name, size, src, dst):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
412 self.name = name
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413 self.size = size
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
414 self.src = src
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
415 self.dst = dst
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
416
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
417 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
418 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
419
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
420 def write_init(self, outfile, already):
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parents:
diff changeset
421 self.src.write_init(outfile, self.size, already)
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422 self.dst.write_init(outfile, self.size, already)
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423
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424 def invalidate_dest(self, already):
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425 if type(self.dst) == Register:
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426 del already[str(self.dst)]
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427
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428 def save_result(self, reg, always):
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429 if always or type(self.dst) != Register:
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430 if type(self.dst) == Decrement:
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431 src = Increment(self.dst.reg)
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432 elif type(self.dst) == Increment:
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433 src = Decrement(self.dst.reg)
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434 else:
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435 src = self.dst
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436 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214
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437 else:
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438 return ''
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439
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440 def consume_regs(self, program):
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441 self.src.consume_regs(program)
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442 self.dst.consume_regs(program)
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443
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444 class Entry(object):
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445 def __init__(self, line):
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446 fields = split_fields(line)
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447 self.name = fields[0]
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448 sizes = fields[1]
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449 sources = fields[2].split(';')
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450 dests = fields[3].split(';')
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451 combos = []
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452 for size in sizes:
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453 for source in sources:
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454 if size != 'b' or source != 'a':
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455 for dest in dests:
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456 if size != 'b' or dest != 'a':
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457 combos.append((size, source, dest))
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458 self.cases = combos
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459
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460 def programs(self):
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461 res = []
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462 for (size, src, dst) in self.cases:
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463 sources = get_variations(src, size)
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464 dests = get_variations(dst, size)
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465 for source in sources:
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466 for dest in dests:
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467 res.append(Program(Inst2Op(self.name, size, source, dest)))
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468 return res
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469
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470 def process_entries(f):
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471 entries = []
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472 for line in f:
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473 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
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474 entries.append(Entry(line))
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475 return entries
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476
224
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477 from os import path, mkdir
214
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478 def main(args):
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479 entries = process_entries(open('testcases.txt'))
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480 for entry in entries:
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481 programs = entry.programs()
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482 for program in programs:
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483 dname = program.dirname()
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484 if not path.exists('generated_tests/' + dname):
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485 mkdir('generated_tests/' + dname)
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486 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w')
214
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487 program.write_rom_test(f)
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488 f.close()
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489
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490 if __name__ == '__main__':
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491 import sys
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492 main(sys.argv)
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493