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annotate gentests.py @ 227:42123feab62d

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Added test cases for divs/divu and added divide by zero handler to test generator
author Mike Pavone <pavone@retrodev.com>
date Sun, 21 Apr 2013 16:44:10 -0700
parents f7ff02eeec2f
children 8db584faac4b
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1 #!/usr/bin/env python
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2
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3 def split_fields(line):
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4 parts = []
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5 while line:
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6 field,_,line = line.partition('\t')
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7 parts.append(field.strip())
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8 while line.startswith('\t'):
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9 line = line[1:]
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10 return parts
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11
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12 class Program(object):
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13 def __init__(self, instruction):
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14 self.avail_dregs = {0,1,2,3,4,5,6,7}
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15 self.avail_aregs = {0,1,2,3,4,5,6,7}
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16 instruction.consume_regs(self)
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17 self.inst = instruction
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18
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19 def dirname(self):
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20 return self.inst.name + '_' + self.inst.size
214
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21 def name(self):
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22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
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23
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24 def write_rom_test(self, outfile):
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25 outfile.write('\tdc.l $0, start\n')
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26 needdivzero = self.inst.name.startswith('div')
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27 for i in xrange(0x8, 0x100, 0x4):
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28 if needdivzero and i == 0x14:
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29 outfile.write('\tdc.l div_zero_handler\n')
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30 else:
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31 outfile.write('\tdc.l empty_handler\n')
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32 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n')
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33 if needdivzero:
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34 outfile.write('div_zero_handler:\n')
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35 div_zero_count = self.get_dreg()
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36 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n')
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37 outfile.write('\trte\n')
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38 outfile.write('start:\n\tmove #0, CCR\n')
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39 if needdivzero:
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40 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n')
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41 already = {}
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42 self.inst.write_init(outfile, already)
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43 if 'label' in already:
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44 outfile.write('lbl_' + str(already['label']) + ':\n')
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45 outfile.write('\t'+str(self.inst)+'\n')
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46 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
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47 save_ccr = self.get_dreg()
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48 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
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49 outfile.write('\tmove #$1F, CCR\n')
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50 self.inst.invalidate_dest(already)
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51 self.inst.write_init(outfile, already)
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52 if 'label' in already:
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53 outfile.write('lbl_' + str(already['label']) + ':\n')
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54 outfile.write('\t'+str(self.inst)+'\n')
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55 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
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56 outfile.write('\treset\n')
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57
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58 def consume_dreg(self, num):
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59 self.avail_dregs.discard(num)
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60
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61 def consume_areg(self, num):
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62 self.avail_aregs.discard(num)
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63
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64 def get_dreg(self):
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65 return Register('d', self.avail_dregs.pop())
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66
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67 class Register(object):
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68 def __init__(self, kind, num):
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69 self.kind = kind
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70 self.num = num
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71
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72 def __str__(self):
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73 if self.kind == 'd' or self.kind == 'a':
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74 return self.kind + str(self.num)
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75 return self.kind
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76
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77 def write_init(self, outfile, size, already):
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78 if not str(self) in already:
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79 minv,maxv = get_size_range(size)
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80 val = randint(minv,maxv)
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81 already[str(self)] = val
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82 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
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83
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84 def consume_regs(self, program):
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85 if self.kind == 'd':
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86 program.consume_dreg(self.num)
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87 elif self.kind == 'a':
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88 program.consume_areg(self.num)
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89
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90 def valid_ram_address(address, size='b'):
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91 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
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92
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93 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
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94 return randint(mina, maxa) | 0xE00000
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95
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96 class Indexed(object):
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97 def __init__(self, base, index, index_size, disp):
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98 self.base = base
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99 self.index = index
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100 self.index_size = index_size
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101 self.disp = disp
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102
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103 def write_init(self, outfile, size, already):
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104 if self.base.kind == 'pc':
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105 if str(self.index) in already:
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106 index = already[str(self.index)]
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107 if self.index_size == 'w':
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108 index = index & 0xFFFF
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109 #sign extend index
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110 if index & 0x8000:
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111 index -= 65536
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112 if index > -1024:
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113 index = already[str(self.index)] = randint(-32768, -1024)
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114 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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115 else:
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116 index = already[str(self.index)] = randint(-32768, -1024)
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117 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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118 num = already.get('label', 0)+1
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119 already['label'] = num
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120 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
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121 else:
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122 if self.base == self.index:
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123 if str(self.base) in already:
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124 if not valid_ram_address(already[str(self.base)]*2):
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125 del already[str(self.base)]
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126 self.write_init(outfile, size, already)
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127 return
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128 else:
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129 base = index = already[str(self.base)]
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130 else:
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131 base = index = already[str(self.base)] = random_ram_address()/2
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132 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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133 else:
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134 if str(self.base) in already:
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135 if not valid_ram_address(already[str(self.base)]):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
136 del already[str(self.base)]
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parents: 214
diff changeset
137 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
138 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
139 else:
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
140 base = already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
141 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
142 base = already[str(self.base)] = random_ram_address()
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
143 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
144 if str(self.index) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
145 index = already[str(self.index)]
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parents: 214
diff changeset
146 if self.index_size == 'w':
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
147 index = index & 0xFFFF
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
148 #sign extend index
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
149 if index & 0x8000:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
150 index -= 65536
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
151 if not valid_ram_address(base + index):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
152 index = already[str(self.index)] = randint(-64, 63)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
153 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
154 else:
214
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155 index = already[str(self.index)] = randint(-64, 63)
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156 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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parents:
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157 address = base + index + self.disp
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parents:
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158 if (address & 0xFFFFFF) < 0xE00000:
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Mike Pavone <pavone@retrodev.com>
parents:
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159 if (address & 0xFFFFFF) < 128:
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parents:
diff changeset
160 self.disp -= (address & 0xFFFFFF)
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parents:
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161 else:
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162 self.disp += 0xE00000-(address & 0xFFFFFF)
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163 address = base + index + self.disp
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164 elif (address & 0xFFFFFF) > 0xFFFFFC:
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165 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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parents:
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166 address = base + index + self.disp
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167 if size != 'b' and address & 1:
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168 self.disp = self.disp ^ 1
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169 address = base + index + self.disp
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parents:
diff changeset
170 minv,maxv = get_size_range(size)
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diff changeset
171 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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172
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diff changeset
173 def __str__(self):
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diff changeset
174 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
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parents:
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175
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parents:
diff changeset
176 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 self.base.consume_regs(program)
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parents:
diff changeset
178 self.index.consume_regs(program)
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179
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parents:
diff changeset
180 class Displacement(object):
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parents:
diff changeset
181 def __init__(self, base, disp):
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182 self.base = base
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diff changeset
183 self.disp = disp
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parents:
diff changeset
184
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
185 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
186 if self.base.kind == 'pc':
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parents:
diff changeset
187 num = already.get('label', 0)+1
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188 already['label'] = num
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diff changeset
189 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
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parents:
diff changeset
190 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
191 if str(self.base) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 if not valid_ram_address(already[str(self.base)]):
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parents:
diff changeset
193 del already[str(self.base)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
195 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
197 base = already[str(self.base)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
198 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
199 base = already[str(self.base)] = random_ram_address()
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parents:
diff changeset
200 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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parents:
diff changeset
201 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 if (address & 0xFFFFFF) < 0xE00000:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
203 if (address & 0xFFFFFF) < 0x10000:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 self.disp -= (address & 0xFFFFFF)
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parents:
diff changeset
205 else:
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parents:
diff changeset
206 self.disp += 0xE00000-(address & 0xFFFFFF)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
208 elif (address & 0xFFFFFF) > 0xFFFFFC:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 if size != 'b' and address & 1:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 self.disp = self.disp ^ 1
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
215 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 def __str__(self):
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parents:
diff changeset
218 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219
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parents:
diff changeset
220 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 self.base.consume_regs(program)
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parents:
diff changeset
222
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 class Indirect(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224 def __init__(self, reg):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 self.reg = reg
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
227 def __str__(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 return '(' + str(self.reg) + ')'
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parents:
diff changeset
229
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
230 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
231 if str(self.reg) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
232 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 del already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
234 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237 address = already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
240 if size != 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 address = address & 0xFFFFFFFE
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
243 already[str(self.reg)] = address
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
245 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
246
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
247 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
248 self.reg.consume_regs(program)
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parents:
diff changeset
249
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parents:
diff changeset
250 class Increment(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
251 def __init__(self, reg):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
252 self.reg = reg
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
253
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
254 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
255 return '(' + str(self.reg) + ')+'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
256
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
257 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
258 if str(self.reg) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
259 if not valid_ram_address(already[str(self.reg)], size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
260 del already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
261 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
262 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
263 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
264 address = already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
266 address = random_ram_address()
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 if size != 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
268 address = address & 0xFFFFFFFE
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
269 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
270 already[str(self.reg)] = address
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
271 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
272 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
273
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
274 def consume_regs(self, program):
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275 self.reg.consume_regs(program)
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276
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diff changeset
277 class Decrement(object):
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parents:
diff changeset
278 def __init__(self, reg):
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parents:
diff changeset
279 self.reg = reg
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parents:
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280
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parents:
diff changeset
281 def __str__(self):
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parents:
diff changeset
282 return '-(' + str(self.reg) + ')'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
283
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parents:
diff changeset
284 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
285 if str(self.reg) in already:
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parents:
diff changeset
286 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
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parents:
diff changeset
287 del already[str(self.reg)]
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parents:
diff changeset
288 self.write_init(outfile, size, already)
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parents:
diff changeset
289 return
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parents:
diff changeset
290 else:
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parents:
diff changeset
291 address = already[str(self.reg)]
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parents:
diff changeset
292 else:
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diff changeset
293 address = random_ram_address(mina=0xE00004)
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parents:
diff changeset
294 if size != 'b':
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parents:
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295 address = address & 0xFFFFFFFE
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parents:
diff changeset
296 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
297 already[str(self.reg)] = address
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parents:
diff changeset
298 minv,maxv = get_size_range(size)
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parents:
diff changeset
299 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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300
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diff changeset
301 def consume_regs(self, program):
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parents:
diff changeset
302 self.reg.consume_regs(program)
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parents:
diff changeset
303
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parents:
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304 class Absolute(object):
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parents:
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305 def __init__(self, address, size):
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parents:
diff changeset
306 self.address = address
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parents:
diff changeset
307 self.size = size
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parents:
diff changeset
308
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 return '(' + str(self.address) + ').' + self.size
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
312 def write_init(self, outfile, size, already):
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parents:
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313 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
315
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
316 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
317 pass
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
318
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
319 class Immediate(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
320 def __init__(self, value):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
321 self.value = value
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324 return '#' + str(self.value)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
325
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
326 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
327 pass
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
328
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
329 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
330 pass
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
331
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
332 all_dregs = [Register('d', i) for i in range(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
333 all_aregs = [Register('a', i) for i in range(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
334 all_indirect = [Indirect(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
335 all_predec = [Decrement(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
336 all_postinc = [Increment(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
337 from random import randint
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
338 def all_indexed():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
339 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
340
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
341 def all_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
342 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
344 def rand_pc_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
346
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
347 def all_pc_indexed():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
348 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
349
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parents:
diff changeset
350 def rand_abs_short():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
351 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
352
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
353 def rand_abs_long():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
354 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
355
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
356 def get_size_range(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
357 if size == 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
358 return (-128, 127)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
359 elif size == 'w':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
360 return (-32768, 32767)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
361 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
362 return (-2147483648, 2147483647)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
363
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
364 def rand_immediate(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
365 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
366
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
367 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
368
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
369 def get_variations(mode, size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
370 mapping = {
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
371 'd':all_dregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
372 'a':all_aregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
373 '(a)':all_indirect,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
374 '-(a)':all_predec,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
375 '(a)+':all_postinc,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
376 '(n,a)':all_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
377 '(n,a,x)':all_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
378 '(n,pc)':rand_pc_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
379 '(n,pc,x)':all_pc_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380 '(n).w':rand_abs_short,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
381 '(n).l':rand_abs_long
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
382 }
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
383 if mode in mapping:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
384 ret = mapping[mode]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
385 if type(ret) != list:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
386 ret = ret()
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
387 return ret
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
388 elif mode == '#n':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 return rand_immediate(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
390 elif mode.startswith('#(') and mode.endswith(')'):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
391 inner = mode[2:-1]
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
392 start,sep,end = inner.rpartition('-')
220
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
393 start,end = int(start),int(end)
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
394 if end-start > 16:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
395 return [Immediate(randint(start, end)) for x in range(0,8)]
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
396 else:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
397 return [Immediate(num) for num in range(start, end+1)]
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
398 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
399 print "Don't know what to do with source type", mode
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
400 return None
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
401
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
402 class Inst2Op(object):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
403 def __init__(self, name, size, src, dst):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
404 self.name = name
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
405 self.size = size
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
406 self.src = src
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
407 self.dst = dst
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
408
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
410 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
411
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
412 def write_init(self, outfile, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413 self.src.write_init(outfile, self.size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
414 self.dst.write_init(outfile, self.size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
415
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
416 def invalidate_dest(self, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
417 if type(self.dst) == Register:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
418 del already[str(self.dst)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
419
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
420 def save_result(self, reg, always):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
421 if always or type(self.dst) != Register:
217
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422 if type(self.dst) == Decrement:
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423 src = Increment(self.dst.reg)
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424 elif type(self.dst) == Increment:
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425 src = Decrement(self.dst.reg)
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426 else:
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427 src = self.dst
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428 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214
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429 else:
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430 return ''
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431
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432 def consume_regs(self, program):
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433 self.src.consume_regs(program)
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434 self.dst.consume_regs(program)
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435
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436 class Entry(object):
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437 def __init__(self, line):
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438 fields = split_fields(line)
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439 self.name = fields[0]
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440 sizes = fields[1]
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441 sources = fields[2].split(';')
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442 dests = fields[3].split(';')
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443 combos = []
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444 for size in sizes:
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445 for source in sources:
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446 if size != 'b' or source != 'a':
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447 for dest in dests:
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448 if size != 'b' or dest != 'a':
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449 combos.append((size, source, dest))
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450 self.cases = combos
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451
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452 def programs(self):
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453 res = []
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454 for (size, src, dst) in self.cases:
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455 sources = get_variations(src, size)
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456 dests = get_variations(dst, size)
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457 for source in sources:
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458 for dest in dests:
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459 res.append(Program(Inst2Op(self.name, size, source, dest)))
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460 return res
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461
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462 def process_entries(f):
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463 entries = []
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464 for line in f:
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465 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
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466 entries.append(Entry(line))
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467 return entries
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468
224
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469 from os import path, mkdir
214
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470 def main(args):
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471 entries = process_entries(open('testcases.txt'))
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472 for entry in entries:
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473 programs = entry.programs()
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474 for program in programs:
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475 dname = program.dirname()
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476 if not path.exists('generated_tests/' + dname):
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477 mkdir('generated_tests/' + dname)
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478 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w')
214
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479 program.write_rom_test(f)
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480 f.close()
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481
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482 if __name__ == '__main__':
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483 import sys
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484 main(sys.argv)
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485