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annotate m68k_to_x86.c @ 76:187c65f40a64

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Implement JSR for some addressing modes
author Mike Pavone <pavone@retrodev.com>
date Fri, 21 Dec 2012 21:19:03 -0800
parents 6396dc91f61e
children 313a0e2228f1
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1 #include "gen_x86.h"
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2 #include "m68k_to_x86.h"
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3 #include <stdio.h>
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4 #include <stddef.h>
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5 #include <stdlib.h>
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6 #include <string.h>
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7
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8 #define BUS 4
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9 #define PREDEC_PENALTY 2
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10 #define CYCLES RAX
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11 #define LIMIT RBP
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12 #define SCRATCH1 RCX
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13 #define SCRATCH2 RDI
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14 #define CONTEXT RSI
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15
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16 #define FLAG_N RBX
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17 #define FLAG_V BH
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18 #define FLAG_Z RDX
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19 #define FLAG_C DH
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20
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21 typedef struct {
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22 int32_t disp;
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23 uint8_t mode;
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24 uint8_t base;
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25 uint8_t index;
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26 uint8_t cycles;
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27 } x86_ea;
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28
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29 void handle_cycle_limit();
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30 void m68k_read_word_scratch1();
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31 void m68k_read_long_scratch1();
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32 void m68k_read_byte_scratch1();
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33 void m68k_write_word();
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34 void m68k_write_long_lowfirst();
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35 void m68k_write_long_highfirst();
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36 void m68k_write_byte();
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37 void m68k_save_context();
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38 void m68k_modified_ret_addr();
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39 void m68k_native_addr();
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40 void m68k_start_context(uint8_t * addr, m68k_context * context);
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41
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42 uint8_t * cycles(uint8_t * dst, uint32_t num)
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43 {
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44 dst = add_ir(dst, num, CYCLES, SZ_D);
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45 }
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46
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47 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
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48 {
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49 if (op->addr_mode == MODE_REG) {
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50 return opts->dregs[op->params.regs.pri];
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51 }
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52 if (op->addr_mode == MODE_AREG) {
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53 return opts->aregs[op->params.regs.pri];
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54 }
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55 return -1;
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56 }
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57
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58 //must be called with an m68k_op_info that uses a register
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59 size_t reg_offset(m68k_op_info *op)
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60 {
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61 if (op->addr_mode == MODE_REG) {
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62 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
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63 }
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64 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
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65 }
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66
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67 void print_regs_exit(m68k_context * context)
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68 {
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69 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
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70 for (int i = 0; i < 8; i++) {
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71 printf("d%d: %X\n", i, context->dregs[i]);
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72 }
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73 for (int i = 0; i < 8; i++) {
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74 printf("a%d: %X\n", i, context->aregs[i]);
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75 }
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76 exit(0);
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77 }
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78
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79 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
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80 {
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81 int8_t reg = native_reg(&(inst->src), opts);
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82 int32_t dec_amount,inc_amount;
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83 if (reg >= 0) {
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84 ea->mode = MODE_REG_DIRECT;
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85 ea->base = reg;
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86 return out;
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87 }
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88 switch (inst->src.addr_mode)
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89 {
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90 case MODE_REG:
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91 case MODE_AREG:
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92 //We only get one memory parameter, so if the dst operand is a register in memory,
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93 //we need to copy this to a temp register first
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94 reg = native_reg(&(inst->dst), opts);
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95 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode == MODE_AREG)
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96 || inst->op == M68K_EXG) {
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97
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98 ea->mode = MODE_REG_DISPLACE8;
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99 ea->base = CONTEXT;
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100 ea->disp = reg_offset(&(inst->src));
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101 } else {
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102 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
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103 ea->mode = MODE_REG_DIRECT;
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104 ea->base = SCRATCH1;
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105 }
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106 break;
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107 case MODE_AREG_PREDEC:
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108 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
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109 out = cycles(out, PREDEC_PENALTY);
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110 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
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111 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
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112 } else {
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113 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
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114 }
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115 case MODE_AREG_INDIRECT:
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116 case MODE_AREG_POSTINC:
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117 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
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118 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
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119 } else {
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120 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
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121 }
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122 switch (inst->extra.size)
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123 {
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124 case OPSIZE_BYTE:
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125 out = call(out, (char *)m68k_read_byte_scratch1);
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parents: 14
diff changeset
126 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
127 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
128 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
129 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
130 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
131 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
132 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
133 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
134
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
135 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
136 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
137 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
138 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
139 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
140 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
141 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
142 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
143 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
144 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
145 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
146 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
147 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
148 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
149 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
150 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
151 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
152 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
153 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
154 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
155 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
156 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
157 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
158 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
159 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
160 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
161 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
162 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
163 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
164 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
165 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
166 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
167 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
168 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
169 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
170 out = cycles(out, BUS);
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
171 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
172 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
173 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
174 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
175 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
176 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
177 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
178 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
179 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
180 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
181 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
182 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
183 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
184 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
185 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
186 break;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
187 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
188 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
189 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
190 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
191 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
192 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
193 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
194 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
195 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
196 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
197 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
198 out = call(out, (char *)m68k_read_byte_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
199 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
200 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
201 out = call(out, (char *)m68k_read_word_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
202 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
203 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
204 out = call(out, (char *)m68k_read_long_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
205 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
206 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
207 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
208 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
209 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
210 case MODE_IMMEDIATE:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
211 case MODE_IMMEDIATE_WORD:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
212 if (inst->variant != VAR_QUICK) {
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
213 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
214 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
215 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
216 ea->disp = inst->src.params.immed;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
217 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
218 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
219 printf("address mode %d not implemented (src)\n", inst->src.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
220 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
221 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
222 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
223 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
224
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
225 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
226 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
227 int8_t reg = native_reg(&(inst->dst), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
228 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
229 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
230 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
231 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
232 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
233 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
234 switch (inst->dst.addr_mode)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237 case MODE_AREG:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
238 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
239 ea->base = CONTEXT;
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
240 ea->disp = reg_offset(&(inst->dst));
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
241 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
242 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
243 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
244 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
245 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
246 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
247 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
248 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
249 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
250 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
251 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
252 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
253 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
254 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
255 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
256 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
257 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
258 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
259 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
260 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
261 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
262 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
263 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
264 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
265 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
266 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
267 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
268 //save reg value in SCRATCH2 so we can use it to save the result in memory later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
269 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
270 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
271 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
272 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
273 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
274
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
275 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
276 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
277 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
278 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
279 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
280 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
281 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
282 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
283 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
284 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
285 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
286 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
287 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
288 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
289 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
290 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
291 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
292 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
293 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
294 out = push_r(out, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
295 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
296 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
297 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
298 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
299 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
300 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
301 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
302 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
303 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
304 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
305 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
306 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
307 out = pop_r(out, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
308 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
309 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
310 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
311 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
312 out = cycles(out, BUS);
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
313 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
314 out = push_r(out, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
315 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
316 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
317 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
318 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
319 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
320 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
321 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
322 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
323 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
324 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
325 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
326 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
327 out = pop_r(out, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
328 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
329 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
330 break;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
331 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
332 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
333 //Add cycles for reading address from instruction stream
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
334 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
335 out = cycles(out, BUS*2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
336 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
337 out = cycles(out, BUS);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
338 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
339 out = mov_ir(out, inst->dst.params.immed, SCRATCH1, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
340 out = push_r(out, SCRATCH1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
341 switch (inst->extra.size)
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
342 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
343 case OPSIZE_BYTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
344 out = call(out, (char *)m68k_read_byte_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
345 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
346 case OPSIZE_WORD:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
347 out = call(out, (char *)m68k_read_word_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
348 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
349 case OPSIZE_LONG:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
350 out = call(out, (char *)m68k_read_long_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
351 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
352 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
353 out = pop_r(out, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
354 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
355 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
356 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
357 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
358 printf("address mode %d not implemented (dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
359 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
360 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
361 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
362 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
363
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
364 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
365 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
366 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
367 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
368 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
369 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
370 out = call(out, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
371 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
372 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
373 out = call(out, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
374 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
375 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
376 out = call(out, (char *)m68k_write_long_lowfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
377 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
378 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
379 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
380 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
381 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
382
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
383 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
384 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
385 address &= 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
386 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
387 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
388 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
389 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
390 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
391 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
392 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
393 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
394 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
395 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
396
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
397 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
398 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
399 deferred_addr * new_head = malloc(sizeof(deferred_addr));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
400 new_head->next = old_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
401 new_head->address = address & 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
402 new_head->dest = dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
403 return new_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
404 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
405
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
406 void process_deferred(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
407 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
408 deferred_addr * cur = opts->deferred;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
409 deferred_addr **last_next = &(opts->deferred);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
410 while(cur)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
411 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
412 uint8_t * native = get_native_address(opts->native_code_map, cur->address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
413 if (native) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
414 int32_t disp = native - (cur->dest + 4);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
415 printf("Native dest: %p, Offset address: %p, displacement: %X\n", native, cur->dest, disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
416 uint8_t * out = cur->dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
417 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
418 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
419 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
420 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
421 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
422 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
423 *out = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
424 *last_next = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
425 free(cur);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
426 cur = *last_next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
427 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
428 last_next = &(cur->next);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
429 cur = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
430 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
431 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
432 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
433
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
434 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
435 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
436 //FIXME: This probably isn't going to work with real code in a lot of cases, no guarantee that
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
437 //all the code in 1KB block is going to be translated at the same time
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
438 address &= 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
439 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
440 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
441 native_code_map[chunk].base = native_addr;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
442 native_code_map[chunk].offsets = malloc(sizeof(uint16_t) * NATIVE_CHUNK_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
443 memset(native_code_map[chunk].offsets, 0xFF, sizeof(uint16_t) * NATIVE_CHUNK_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
444 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
445 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
446 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
447 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
448
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
449 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
450 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
451 int8_t reg, flags_reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
452 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
453 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
454 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
455 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
456 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
457 reg = native_reg(&(inst->dst), opts);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
458 //update statically set flags
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
459 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
460 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
461
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
462 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
463 flags_reg = src.base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
464 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
465 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
466 flags_reg = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
467 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
468 printf("moving %d to temp register %d\n", src.disp, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
469 dst = mov_ir(dst, src.disp, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
470 src.mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
471 flags_reg = src.base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
472 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
473 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
474 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
475 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
476 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
477 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
478 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
479 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
480 dst = mov_rr(dst, src.base, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
481 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
482 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
483 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
484 dst = mov_ir(dst, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
485 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
486 } else if(src.mode == MODE_REG_DIRECT) {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
487 printf("mov_rrdisp8 from reg %d to offset %d from reg %d (%d)\n", src.base, (int)reg_offset(&(inst->dst)), CONTEXT, inst->dst.params.regs.pri);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
488 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
489 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
490 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
491 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
492 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
493 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
494 dst = setcc_r(dst, CC_S, FLAG_N);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
495 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
496 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
497 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
498 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
499 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
500 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
501 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
502 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
503 case MODE_AREG_INDIRECT:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
504 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
505 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
506 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
507 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
508 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
509 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
510 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
511 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
512 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
513 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
514 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
515 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
516 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
517 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
518 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
519 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
520 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
521 dst = setcc_r(dst, CC_S, FLAG_N);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
522 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
523 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
524 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
525 dst = call(dst, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
526 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
527 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
528 dst = call(dst, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
529 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
530 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
531 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
532 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
533 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
534 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
535 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
536 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
537 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
538 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
539 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
540 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
541 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
542 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
543 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
544 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
545 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
546 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
547 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
548 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
549 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
550 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
551 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
552 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
553 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
554 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
555 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
556 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
557 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
558 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
559 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
560 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
561 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
562 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
563 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
564 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
565 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
566 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
567 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
568 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
569 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
570 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
571 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
572 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
573 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
574 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
575 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
576 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
577 dst = cycles(dst, BUS);
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
578 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
579 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
580 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
581 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
582 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
583 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
584 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
585 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
586 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
587 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
588 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
589 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
590 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
591 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
592 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
593 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
594 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
595 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
596 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
597 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
598 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
599 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
600 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
601 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
602 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
603 break;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
604 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
605 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
606 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
607 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
608 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
609 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
610 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
611 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
612 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
613 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
614 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
615 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
616 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
617 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
618 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
619 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
620 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
621 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
622 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
623 dst = setcc_r(dst, CC_S, FLAG_N);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
624 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
625 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
626 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
627 dst = call(dst, (char *)m68k_write_byte);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
628 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
629 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
630 dst = call(dst, (char *)m68k_write_word);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
631 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
632 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
633 dst = call(dst, (char *)m68k_write_long_highfirst);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
634 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
635 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
636 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
637 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
638 printf("address mode %d not implemented (move dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
639 exit(1);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
640 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
641
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
642 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
643 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
644 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
645 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
646
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
647 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
648 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
649 int8_t bit,reg;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
650 uint8_t early_cycles;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
651 if(inst->src.addr_mode == MODE_REG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
652 //reg to mem
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
653 early_cycles = 8;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
654 int8_t dir;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
655 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
656 reg = 15;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
657 dir = -1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
658 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
659 reg = 0;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
660 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
661 switch (inst->dst.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
662 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
663 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
664 case MODE_AREG_PREDEC:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
665 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
666 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
667 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
668 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
669 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
670 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
671 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
672 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
673 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
674 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
675 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
676 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
677 default:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
678 printf("address mode %d not implemented (movem dst)\n", inst->dst.addr_mode);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
679 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
680 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
681 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
682 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
683 if (inst->src.params.immed & (1 << bit)) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
684 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
685 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
686 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
687 dst = push_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
688 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
689 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
690 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
691 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
692 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
693 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
694 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
695 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
696 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
697 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
698 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
699 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
700 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
701 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
702 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
703 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
704 dst = call(dst, (uint8_t *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
705 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
706 dst = pop_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
707 if (inst->dst.addr_mode != MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
708 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
709 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
710 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
711 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
712 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
713 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
714 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
715 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
716 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
717 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
718 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
719 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
720 //mem to reg
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
721 early_cycles = 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
722 switch (inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
723 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
724 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
725 case MODE_AREG_POSTINC:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
726 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
727 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
728 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
729 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
730 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
731 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
732 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
733 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
734 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
735 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
736 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
737 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
738 default:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
739 printf("address mode %d not implemented (movem src)\n", inst->src.addr_mode);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
740 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
741 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
742 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
743 for(reg = 0; reg < 16; reg ++) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
744 if (inst->dst.params.immed & (1 << reg)) {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
745 dst = push_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
746 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
747 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
748 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
749 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
750 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
751 if (reg > 7) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
752 printf("movem.%c to a%d\n", (inst->extra.size == OPSIZE_WORD ? 'w' : 'l'), reg-8);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
753 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
754 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
755 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
756 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
757 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
758 } else {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
759 printf("movem.%c to d%d\n", (inst->extra.size == OPSIZE_WORD ? 'w' : 'l'), reg);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
760 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
761 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
762 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
763 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
764 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
765 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
766 dst = pop_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
767 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
768 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
769 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
770 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
771 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
772 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
773 } else {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
774 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
775 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
776 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
777 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
778 //prefetch
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
779 dst = cycles(dst, 4);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
780 return dst;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
781 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
782
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
783 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
784 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
785 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
786 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
787 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
788 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
789 uint8_t reg = native_reg(&(inst->dst), opts);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
790 if (reg >= 0) {
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
791 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
792 return xor_rr(dst, reg, reg, inst->extra.size);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
793 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
794 int32_t dec_amount,inc_amount;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
795 switch (inst->dst.addr_mode)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
796 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
797 case MODE_REG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
798 case MODE_AREG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
799 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
800 dst = mov_irdisp8(dst, 0, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
801 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
802 case MODE_AREG_PREDEC:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
803 dst = cycles(dst, PREDEC_PENALTY);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
804 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
805 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
806 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
807 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
808 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
809 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
810 case MODE_AREG_INDIRECT:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
811 case MODE_AREG_POSTINC:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
812 //add cycles for prefetch and wasted read
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
813 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 12 : 8));
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
814 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
815 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
816 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
817 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
818 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
819 dst = xor_rr(dst, SCRATCH1, SCRATCH1, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
820 switch (inst->extra.size)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
821 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
822 case OPSIZE_BYTE:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
823 dst = call(dst, (char *)m68k_write_byte);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
824 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
825 case OPSIZE_WORD:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
826 dst = call(dst, (char *)m68k_write_word);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
827 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
828 case OPSIZE_LONG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
829 dst = call(dst, (char *)m68k_write_long_highfirst);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
830 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
831 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
832 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
833 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
834 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
835 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
836 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
837 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
838 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
839 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
840 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
841 default:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
842 printf("address mode %d not implemented (clr dst)\n", inst->dst.addr_mode);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
843 exit(1);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
844 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
845 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
846 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
847
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
848 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
849 {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
850 int8_t dst_reg = native_reg(&(inst->dst), opts);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
851 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
852 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
853 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
854 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
855 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
856 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
857 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
858 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
859 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
860 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
861 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
862 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
863 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
864 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
865 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
866 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
867 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
868 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
869 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
870 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
871 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
872 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
873 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
874 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
875 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
876 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
877 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
878 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
879 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
880 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
881 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
882 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
883 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
884 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
885 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
886 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
887 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
888 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
889 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
890 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
891 if (dst_reg >= 0) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
892 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
893 } else {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
894 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
895 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
896 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
897 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
898 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
899 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
900 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
901 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
902 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
903 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
904 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
905 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
906 default:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
907 printf("address mode %d not implemented (lea src)\n", inst->src.addr_mode);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
908 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
909 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
910 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
911 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
912
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
913 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
914 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
915 int32_t disp = inst->src.params.immed;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
916 uint32_t after = inst->address + 2;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
917 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
918 dst = cycles(dst, 10);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
919 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
920 dst = push_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
921 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
922 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
923 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
924 printf("bsr@%X: after=%X, disp=%X, dest=%X\n", inst->address, after, disp, after+disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
925 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
926 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
927 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
928 //dummy address to be replaced later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
929 dest_addr = dst + 5;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
930 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
931 dst = call(dst, (char *)dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
932 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
933 dst = pop_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
934 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
935 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
936
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
937 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
938 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
939 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
940 int32_t disp = inst->src.params.immed;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
941 uint32_t after = inst->address + 2;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
942 printf("bcc@%X: after=%X, disp=%X, dest=%X\n", inst->address, after, disp, after+disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
943 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
944 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
945 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
946 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
947 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
948 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
949 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
950 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
951 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
952 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
953 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
954 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
955 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
956 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
957 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
958 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
959 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
960 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
961 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
962 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
963 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
964 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
965 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
966 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
967 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
968 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
969 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
970 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
971 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
972 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
973 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
974 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
975 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
976 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
977 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
978 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
979 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
980 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
981 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
982 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
983 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
984 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
985 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
986 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
987 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
988 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
989 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
990 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
991 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
992 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
993 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
994 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
995 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
996 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
997 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
998 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
999 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1000 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1001 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1002 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1003
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1004 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1005 {
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1006 uint8_t * dest_addr;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1007 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1008 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1009 case MODE_AREG_INDIRECT:
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1010 dst = cycles(dst, BUS*2);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1011 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1012 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1013 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1014 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1015 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1016 dst = call(dst, (uint8_t *)m68k_native_addr);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1017 //TODO: Finish me
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1018 printf("address mode %d not yet supported (jmp)\n", inst->src.addr_mode);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1019 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1020 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1021 dst = cycles(dst, 10);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1022 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1023 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1024 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1025 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1026 dest_addr = dst + 256;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1027 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1028 dst = jmp(dst, dest_addr);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1029 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1030 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1031 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1032 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1033 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1034 if (!dest_addr) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1035 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1036 //dummy address to be replaced later, make sure it generates a 4-byte displacement
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1037 dest_addr = dst + 256;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1038 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1039 dst = jmp(dst, dest_addr);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1040 break;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1041 default:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1042 printf("address mode %d not yet supported (jmp)\n", inst->src.addr_mode);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1043 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1044 return dst;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1045 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1046
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1047 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1048 {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1049 uint8_t * dest_addr;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1050 uint32_t after;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1051 switch(inst->src.addr_mode)
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1052 {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1053 case MODE_AREG_INDIRECT:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1054 dst = cycles(dst, BUS*2);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1055 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1056 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1057 } else {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1058 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1059 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1060 dst = call(dst, (uint8_t *)m68k_native_addr);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1061 //TODO: Finish me
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1062 printf("address mode %d not yet supported (jsr)\n", inst->src.addr_mode);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1063 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1064 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1065 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1066 dst = cycles(dst, 10);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1067 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1068 dst = push_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1069 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1070 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1071 dst = call(dst, (char *)m68k_write_long_highfirst);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1072 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1073 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1074 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1075 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1076 dest_addr = dst + 5;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1077 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1078 dst = call(dst, (char *)dest_addr);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1079 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1080 dst = pop_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1081 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1082 case MODE_ABSOLUTE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1083 case MODE_ABSOLUTE_SHORT:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1084 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1085 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1086 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1087 dst = push_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1088 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1089 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1090 dst = call(dst, (char *)m68k_write_long_highfirst);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1091 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1092 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1093 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1094 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1095 dest_addr = dst + 5;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1096 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1097 dst = call(dst, (char *)dest_addr);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1098 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1099 dst = pop_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1100 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1101 default:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1102 printf("address mode %d not yet supported (jsr)\n", inst->src.addr_mode);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1103 }
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1104 return dst;
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1105 }
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1106
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1107 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1108 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1109 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1110 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1111 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1112 dst = call(dst, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1113 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1114 dst = jcc(dst, CC_NZ, dst+3);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1115 dst = retn(dst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1116 dst = jmp(dst, (char *)m68k_modified_ret_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1117 return dst;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1118 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1119
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1120 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1121 {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1122 //best case duration
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1123 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1124 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1125 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1126 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1127 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1128 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1129 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1130 {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1131 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1132 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1133 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1134 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1135 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1136 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1137 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1138 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1139 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1140 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1141 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1142 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1143 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1144 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1145 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1146 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1147 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1148 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1149 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1150 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1151 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1152 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1153 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1154 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1155 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1156 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1157 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1158 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1159 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1160 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1161 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1162 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1163 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1164 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1165 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1166 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1167 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1168 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1169 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1170 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1171 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1172 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1173 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1174 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1175 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1176 } else {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1177 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1178 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1179 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1180 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1181 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1182 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1183 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1184 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1185 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1186 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1187 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1188 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1189 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1190 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1191 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1192 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1193 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1194 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1195 } else {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1196 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1197 }
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1198 return dst;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1199 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1200
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1201 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1202 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1203 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1204 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1205
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1206 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1207 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1208 uint8_t * end_off = NULL;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1209 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1210 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1211 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1212 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1213 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1214 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1215 if (src_op->mode == MODE_IMMED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1216 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1217 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1218 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1219 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1220 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1221 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1222 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1223 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1224 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1225 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1226 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1227 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1228 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1229 dst = and_ir(dst, 63, RCX, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1230 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1231 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1232 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1233 //x86 shifts modulo 32 for operand sizes less than 64-bits
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1234 //but M68K shifts modulo 64, so we need to check for large shifts here
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1235 dst = cmp_ir(dst, 32, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1236 uint8_t * norm_shift_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1237 dst = jcc(dst, CC_L, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1238 if (special) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1239 if (inst->extra.size == OPSIZE_LONG) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1240 uint8_t * neq_32_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1241 dst = jcc(dst, CC_NZ, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1242
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1243 //set the carry bit to the lsb
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1244 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1245 dst = special(dst, 1, dst_op->base, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1246 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1247 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1248 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1249 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1250 dst = jmp(dst, dst+4);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1251 *neq_32_off = dst - (neq_32_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1252 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1253 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1254 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1255 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1256 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1257 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1258 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1259 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1260 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1261 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1262 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1263 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1264 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1265 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1266 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1267 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1268 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1269
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1270 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1271 end_off = dst+1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1272 dst = jmp(dst, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1273 *norm_shift_off = dst - (norm_shift_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1274 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1275 dst = shift_clr(dst, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1276 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1277 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1278 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1279
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1280 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1281
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1282 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1283 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1284 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1285 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1286 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1287 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1288 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1289 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1290 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1291 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1292 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1293 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1294 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1295 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1296 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1297 }
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
1298 return dst;
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1299 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1300
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1301 #define BIT_SUPERVISOR 5
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1302
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1303 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1304 {
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1305 uint8_t * end_off;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1306 map_native_address(opts->native_code_map, inst->address, dst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1307 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1308 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1309 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1310 return translate_m68k_lea(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1311 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1312 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1313 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1314 return translate_m68k_bcc(dst, inst, opts);
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1315 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1316 return translate_m68k_jmp(dst, inst, opts);
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1317 } else if(inst->op == M68K_JSR) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1318 return translate_m68k_jsr(dst, inst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1319 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1320 return translate_m68k_rts(dst, inst, opts);
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1321 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1322 return translate_m68k_dbcc(dst, inst, opts);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1323 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1324 return translate_m68k_clr(dst, inst, opts);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1325 } else if(inst->op == M68K_MOVEM) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1326 return translate_m68k_movem(dst, inst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1327 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1328 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1329 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1330 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1331 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1332 if (inst->dst.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1333 dst = translate_m68k_dst(inst, &dst_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1334 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1335 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1336 {
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1337 //case M68K_ABCD:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1338 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1339 case M68K_ADD:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1340 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1341 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1342 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1343 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1344 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1345 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1346 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1347 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1348 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1349 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1350 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1351 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1352 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1353 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1354 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1355 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1356 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1357 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1358 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1359 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1360 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1361 dst = m68k_save_result(inst, dst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1362 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1363 //case M68K_ADDX:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1364 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1365 case M68K_AND:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1366 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1367 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1368 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1369 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1370 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1371 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1372 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1373 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1374 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1375 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1376 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1377 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1378 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1379 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1380 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1381 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1382 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1383 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1384 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1385 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1386 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1387 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1388 case M68K_ANDI_CCR:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1389 case M68K_ANDI_SR:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1390 dst = cycles(dst, 20);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1391 //TODO: If ANDI to SR, trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1392 if (!(inst->src.params.immed & 0x1)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1393 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1394 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1395 if (!(inst->src.params.immed & 0x2)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1396 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1397 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1398 if (!(inst->src.params.immed & 0x4)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1399 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1400 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1401 if (!(inst->src.params.immed & 0x8)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1402 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1403 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1404 if (!(inst->src.params.immed & 0x10)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1405 dst = mov_irind(dst, 0, CONTEXT, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1406 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1407 if (inst->op == M68K_ANDI_SR) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1408 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1409 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1410 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1411 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1412 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1413 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1414 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1415 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1416 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1417 case M68K_ASL:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1418 case M68K_LSL:
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1419 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1420 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1421 case M68K_ASR:
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1422 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1423 break;
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1424 case M68K_LSR:
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1425 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1426 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1427 /*case M68K_BCHG:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1428 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1429 case M68K_BSET:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1430 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1431 case M68K_BTST:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1432 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
67
534eb4976423 Fix BTST
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
1433 if (src_op.mode == MODE_IMMED) {
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1434 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1435 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1436 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1437 if (dst_op.mode == MODE_REG_DIRECT) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1438 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1439 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1440 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1441 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1442 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1443 if (src_op.mode == MODE_REG_DISPLACE8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1444 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1445 dst = push_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1446 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1447 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1448 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1449 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1450 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1451 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1452 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1453 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1454 dst = and_ir(dst, 0x7, src_op.base, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1455 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1456 if (dst_op.mode == MODE_REG_DIRECT) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1457 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1458 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1459 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1460 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1461 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1462 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1463 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1464 dst = setcc_r(dst, CC_NC, FLAG_Z);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1465 if (src_op.base == SCRATCH2) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1466 dst = pop_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1467 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1468 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1469 /*case M68K_CHK:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1470 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1471 case M68K_CMP:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1472 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1473 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1474 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1475 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1476 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1477 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1478 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1479 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1480 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1481 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1482 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1483 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1484 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1485 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1486 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1487 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1488 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1489 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1490 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1491 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1492 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1493 /*case M68K_DIVS:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1494 case M68K_DIVU:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1495 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1496 case M68K_EOR:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1497 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1498 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1499 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1500 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1501 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1502 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1503 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1504 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1505 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1506 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1507 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1508 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1509 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1510 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1511 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1512 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1513 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1514 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1515 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1516 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1517 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1518 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1519 /*case M68K_EORI_CCR:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1520 case M68K_EORI_SR:*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1521 case M68K_EXG:
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1522 dst = cycles(dst, 6);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1523 if (dst_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1524 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1525 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1526 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1527 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1528 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1529 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1530 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1531 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1532 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1533 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1534 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1535 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1536 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1537 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1538 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1539 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1540 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1541 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1542 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1543 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1544 //case M68K_EXT:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1545 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1546 case M68K_ILLEGAL:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1547 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1548 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1549 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1550 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1551 /*case M68K_JSR:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1552 case M68K_LEA:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1553 case M68K_LINK:
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1554 case M68K_MOVE_FROM_SR:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1555 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1556 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1557 case M68K_MOVE_SR:
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1558 //TODO: Privilege check for MOVE to SR
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1559 if (src_op.mode == MODE_IMMED) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1560 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1561 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1562 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1563 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1564 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1565 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1566 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1567 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1568 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1569 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1570 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1571 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1572 }
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1573 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1574 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1575 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1576 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1577 dst = mov_rr(dst, src_op.base, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1578 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1579 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1580 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1581 dst = mov_rr(dst, FLAG_C, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1582 dst = and_ir(dst, 1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1583 dst = shr_ir(dst, 1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1584 dst = mov_rr(dst, FLAG_V, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1585 dst = and_ir(dst, 1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1586 dst = shr_ir(dst, 1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1587 dst = mov_rr(dst, FLAG_Z, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1588 dst = and_ir(dst, 1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1589 dst = shr_ir(dst, 1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1590 dst = mov_rr(dst, 1, SCRATCH2, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1591 dst = shr_ir(dst, 1, SCRATCH2, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1592 dst = and_ir(dst, 1, SCRATCH2, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1593 dst = mov_rrind(dst, SCRATCH2, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1594 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1595 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1596 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1597 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_W);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1598 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1599 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1600 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1601 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1602 dst = shr_ir(dst, 8, SCRATCH2, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1603 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, status), SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1604 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1605 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1606 case M68K_MOVE_USP:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1607 dst = cycles(dst, BUS);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1608 //TODO: Trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1609 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1610 if (inst->src.addr_mode == MODE_UNUSED) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1611 if (dst_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1612 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1613 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1614 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1615 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1616 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1617 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1618 if (src_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1619 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1620 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1621 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1622 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1623 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1624 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1625 break;
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1626 /*case M68K_MOVEP:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1627 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1628 case M68K_MULU:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1629 case M68K_NBCD:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1630 case M68K_NEG:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1631 case M68K_NEGX:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1632 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1633 case M68K_NOP:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1634 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1635 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1636 //case M68K_NOT:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1637 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1638 case M68K_OR:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1639 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1640 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1641 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1642 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1643 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1644 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1645 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1646 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1647 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1648 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1649 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1650 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1651 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1652 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1653 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1654 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1655 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1656 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1657 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1658 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1659 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1660 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1661 /*case M68K_ORI_CCR:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1662 case M68K_ORI_SR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1663 case M68K_PEA:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1664 case M68K_RESET:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1665 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1666 case M68K_ROR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1667 case M68K_ROXL:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1668 case M68K_ROXR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1669 case M68K_RTE:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1670 case M68K_RTR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1671 case M68K_SBCD:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1672 case M68K_SCC:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1673 case M68K_STOP:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1674 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1675 case M68K_SUB:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1676 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1677 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1678 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1679 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1680 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1681 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1682 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1683 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1684 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1685 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1686 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1687 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1688 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1689 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1690 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1691 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1692 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1693 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1694 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1695 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1696 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1697 dst = m68k_save_result(inst, dst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1698 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1699 //case M68K_SUBX:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1700 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1701 case M68K_SWAP:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1702 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1703 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1704 dst = rol_ir(dst, 16, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1705 } else{
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1706 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1707 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1708 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1709 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1710 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1711 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1712 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1713 /*case M68K_TAS:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1714 case M68K_TRAP:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1715 case M68K_TRAPV:*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1716 case M68K_TST:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1717 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1718 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1719 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1720 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1721 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1722 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1723 dst = setcc_r(dst, CC_C, FLAG_C);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1724 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1725 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1726 dst = setcc_r(dst, CC_O, FLAG_V);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1727 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1728 /*case M68K_UNLK:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1729 case M68K_INVALID:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1730 break;*/
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1731 default:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1732 printf("instruction %d not yet implemented\n", inst->op);
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1733 exit(1);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1734 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1735 return dst;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1736 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1737
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1738 uint8_t * translate_m68k_stream(uint8_t * dst, uint8_t * dst_end, uint32_t address, m68k_context * context)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1739 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1740 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1741 x86_68k_options * opts = context->options;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1742 char disbuf[1024];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1743 uint16_t *encoded = context->mem_pointers[0] + address/2, *next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1744 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1745 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1746 if (dst_end-dst < 128) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1747 puts("out of code memory");
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1748 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1749 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1750 next = m68k_decode(encoded, &instbuf, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1751 address += (next-encoded)*2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1752 encoded = next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1753 m68k_disasm(&instbuf, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1754 printf("%X: %s\n", instbuf.address, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1755 dst = translate_m68k(dst, &instbuf, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1756 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1757 process_deferred(opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1758 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1759 address = opts->deferred->address;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1760 encoded = context->mem_pointers[0] + address/2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1761 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1762 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1763 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1764 } while(encoded != NULL);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1765 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1766 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1767
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1768 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1769 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1770 uint8_t * addr = get_native_address(context->native_code_map, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1771 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1772 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1773
19
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1774 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1775 {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1776 //TODO: Make this actually use the normal read functions
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1777 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1];
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1778 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3];
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1779 start_68k_context(context, address);
19
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1780 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1781
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1782 void init_x86_68k_opts(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1783 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1784 opts->flags = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1785 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1786 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1787 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1788 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1789 opts->dregs[2] = R12;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1790 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1791 opts->aregs[1] = R14;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1792 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1793 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1794 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1795 opts->deferred = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1796 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1797
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1798 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1799 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1800 memset(context, 0, sizeof(m68k_context));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1801 context->native_code_map = native_code_map;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1802 context->options = opts;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1803 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1804