Mercurial > repos > blastem
annotate runtime.S @ 243:2f069a0b487e
Implement EI, DI and IM in the Z80 core
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Sun, 28 Apr 2013 14:32:45 -0700 |
| parents | 28a6697e847b |
| children | 4a7ac10ac2d9 |
| rev | line source |
|---|---|
|
17
de0085d4ea40
Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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1 |
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18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
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2 .global handle_cycle_limit |
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150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
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3 .global do_sync |
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18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
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4 handle_cycle_limit: |
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82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
5 cmp 84(%rsi), %eax |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
6 jb skip_sync |
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150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
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7 do_sync: |
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54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
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8 call m68k_save_context |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
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9 mov %rsi, %rdi |
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198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
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10 xor %esi, %esi |
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54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
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11 call sync_components |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
12 mov %rax, %rsi |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
13 call m68k_load_context |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
14 skip_sync: |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
15 ret |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
16 |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
17 .global handle_cycle_limit_int |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
18 handle_cycle_limit_int: |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
19 cmp 88(%rsi), %eax |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
20 jb skip_int |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
21 /* swap USP and SSP if not already in supervisor mode */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
22 bt $5, 5(%rsi) |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
23 jc already_supervisor |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
24 mov 72(%rsi), %edi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
25 mov %r15d, 72(%rsi) |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
26 mov %edi, %r15d |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
27 already_supervisor: |
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175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
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28 /* save PC */ |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
29 sub $4, %r15d |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
30 mov %r15d, %edi |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
31 call m68k_write_long_lowfirst |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
32 /* save status register on stack */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
33 sub $2, %r15d |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
34 mov %r15d, %edi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
35 call get_sr |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
36 call m68k_write_word |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
37 /* update status register */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
38 andb $0xF8, 5(%rsi) |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
39 mov 92(%rsi), %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
40 or $0x20, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
41 or %cl, 5(%rsi) |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
42 /* calculate interrupt vector address */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
43 mov 92(%rsi), %ecx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
44 shl $2, %ecx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
45 add $0x60, %ecx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
46 call m68k_read_long_scratch1 |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
47 call m68k_native_addr_and_sync |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
48 add $24, %eax |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
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49 /* discard function return address */ |
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6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
50 pop %rdi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
51 jmp *%rcx |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
52 ret |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
53 skip_int: |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
54 cmp 84(%rsi), %eax |
|
198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
55 jb skip_sync_int |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
56 call m68k_save_context |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
57 mov %rsi, %rdi |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
58 mov %ecx, %esi |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
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59 call sync_components |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
60 mov %rax, %rsi |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
61 call m68k_load_context |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
62 skip_sync_int: |
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82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
63 ret |
|
87
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
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64 |
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152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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65 .global m68k_trap |
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79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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66 m68k_trap: |
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79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
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67 push %rdi |
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79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
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68 push %rcx |
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79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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69 /* swap USP and SSP if not already in supervisor mode */ |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
70 bt $5, 5(%rsi) |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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71 jc already_supervisor_trap |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
72 mov 72(%rsi), %edi |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
73 mov %r15d, 72(%rsi) |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
74 mov %edi, %r15d |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
75 already_supervisor_trap: |
|
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
76 /* save PC */ |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
77 sub $4, %r15d |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
78 mov %r15d, %edi |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
79 pop %rcx |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
80 call m68k_write_long_lowfirst |
|
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
81 /* save status register on stack */ |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
82 sub $2, %r15d |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
83 mov %r15d, %edi |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
84 call get_sr |
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79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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85 call m68k_write_word |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
86 /* update status register */ |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
87 andb $0xF8, 5(%rsi) |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
88 mov 92(%rsi), %cl |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
89 or $0x20, %cl |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
90 or %cl, 5(%rsi) |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
91 /* calculate interrupt vector address */ |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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92 pop %rcx |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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93 shl $2, %ecx |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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94 call m68k_read_long_scratch1 |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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95 call m68k_native_addr_and_sync |
|
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
209
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changeset
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96 add $18, %eax |
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152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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97 jmp *%rcx |
|
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
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98 |
|
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
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99 invalid_msg: |
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e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
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parents:
175
diff
changeset
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100 .asciz "Invalid instruction at %X\n" |
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e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
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101 |
|
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
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102 .global m68k_invalid |
|
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
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103 m68k_invalid: |
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104 lea invalid_msg(%rip), %rdi |
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105 mov %ecx, %esi |
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|
106 xor %rax, %rax |
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107 call printf |
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108 mov $1, %rdi |
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|
109 call exit |
|
194
811163790e6c
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|
110 |
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|
111 .global bcd_add |
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112 bcd_add: |
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|
113 xchg %rax, %rdi |
|
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114 |
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115 mov %cl, %ch |
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116 mov %al, %ah |
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117 and $0xF, %ch |
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|
118 and $0xF, %ah |
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119 and $0xF0, %cl |
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120 and $0xF0, %al |
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121 add %ah, %ch |
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122 cmp $10, %ch |
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123 jb no_adjust |
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124 add $6, %ch |
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125 no_adjust: |
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126 add %ch, %al |
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127 add %al, %cl |
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128 mov $0, %ch |
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129 jc def_adjust |
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130 cmp $0xA0, %cl |
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131 jb no_adjust_h |
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132 def_adjust: |
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133 add $0x60, %cl |
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134 mov $1, %ch |
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|
135 no_adjust_h: |
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136 |
|
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137 mov %rdi, %rax |
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138 ret |
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139 |
|
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140 .global bcd_sub |
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141 bcd_sub: |
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142 xchg %rax, %rdi |
|
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|
143 |
|
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144 mov %cl, %ch |
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145 mov %al, %ah |
|
811163790e6c
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parents:
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changeset
|
146 and $0xF, %ch |
|
811163790e6c
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Mike Pavone <pavone@retrodev.com>
parents:
193
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changeset
|
147 and $0xF, %ah |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
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|
148 and $0xF0, %cl |
|
811163790e6c
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Mike Pavone <pavone@retrodev.com>
parents:
193
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|
149 and $0xF0, %al |
|
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|
150 sub %ah, %ch |
|
811163790e6c
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|
151 cmp $10, %ch |
|
811163790e6c
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|
152 jb no_adjusts |
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811163790e6c
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|
153 sub $6, %ch |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
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changeset
|
154 no_adjusts: |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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changeset
|
155 add %ch, %cl |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
193
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changeset
|
156 sub %al, %cl |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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changeset
|
157 mov $0, %ch |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
193
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changeset
|
158 jc def_adjusts |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
193
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changeset
|
159 cmp $0xA0, %cl |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
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changeset
|
160 jb no_adjust_hs |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
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|
161 def_adjusts: |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
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changeset
|
162 sub $0x60, %cl |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
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|
163 mov $1, %ch |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
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changeset
|
164 no_adjust_hs: |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
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changeset
|
165 |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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193
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changeset
|
166 mov %rdi, %rax |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
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parents:
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changeset
|
167 ret |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
168 |
|
87
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
169 int_dbg_msg: |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
170 .asciz "Executing Interrupt!" |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
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86
diff
changeset
|
171 print_int_dbg: |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
172 call m68k_save_context |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
173 push %rsi |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
174 lea int_dbg_msg(%rip), %rdi |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
175 call puts |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
176 pop %rsi |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
177 call m68k_load_context |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
178 ret |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
179 |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
180 .global get_sr |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
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diff
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|
181 get_sr: |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
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diff
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|
182 mov 5(%rsi), %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
183 shl $8, %cx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
184 mov (%rsi), %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
185 shl $1, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
186 or %bl, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
187 shl $1, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
188 or %dl, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
189 shl $1, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
190 or %bh, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
191 shl $1, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
192 or %dh, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
193 ret |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
194 |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
195 .global set_sr |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
196 set_sr: |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
197 mov %cl, %dh |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
198 and $1, %dh |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
199 shr $1, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
200 mov %cl, %bh |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
201 and $1, %bh |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
202 shr $1, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
203 mov %cl, %dl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
204 and $1, %dl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
205 shr $1, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
206 mov %cl, %bl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
207 and $1, %bl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
208 shr $1, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
209 and $1, %cl |
|
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210 mov %cl, (%rsi) |
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211 shr $8, %cx |
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212 mov %cl, 5(%rsi) |
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213 ret |
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214 |
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215 .global set_ccr |
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216 set_ccr: |
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217 mov %cl, %dh |
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218 and $1, %dh |
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219 shr $1, %cl |
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220 mov %cl, %bh |
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221 and $1, %bh |
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222 shr $1, %cl |
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223 mov %cl, %dl |
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224 and $1, %dl |
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225 shr $1, %cl |
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226 mov %cl, %bl |
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227 and $1, %bl |
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228 shr $1, %cl |
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229 and $1, %cl |
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230 mov %cl, (%rsi) |
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231 ret |
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232 |
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233 do_vdp_port_write: |
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234 call m68k_save_context |
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235 mov %rcx, %rdx |
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236 call vdp_port_write |
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237 mov %rax, %rsi |
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238 call m68k_load_context |
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239 ret |
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240 |
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241 do_vdp_port_read: |
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242 mov %ecx, %edi |
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243 call m68k_save_context |
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244 call vdp_port_read |
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245 mov %rax, %rsi |
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246 call m68k_load_context |
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247 mov 136(%rsi), %cx |
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248 ret |
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249 |
| 66 | 250 do_io_write: |
| 251 call m68k_save_context | |
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252 and $0x1FFFF, %edi |
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253 mov %ecx, %edx |
| 66 | 254 call io_write |
| 255 mov %rax, %rsi | |
| 256 call m68k_load_context | |
| 257 ret | |
| 258 do_io_read: | |
| 259 mov %ecx, %edi | |
|
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260 and $0x1FFFF, %edi |
| 66 | 261 call m68k_save_context |
| 262 call io_read | |
| 263 mov %rax, %rsi | |
| 264 call m68k_load_context | |
|
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265 mov 136(%rsi), %cl |
| 66 | 266 ret |
|
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267 |
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268 do_io_write_w: |
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269 call m68k_save_context |
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270 and $0x1FFFF, %edi |
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83
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271 mov %ecx, %edx |
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272 call io_write_w |
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273 mov %rax, %rsi |
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274 call m68k_load_context |
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275 ret |
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276 do_io_read_w: |
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277 mov %ecx, %edi |
|
153
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278 and $0x1FFFF, %edi |
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279 call m68k_save_context |
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280 call io_read_w |
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281 mov %rax, %rsi |
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282 call m68k_load_context |
|
84
2d1ae596db7a
Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
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283 mov 136(%rsi), %cx |
|
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284 ret |
| 66 | 285 |
|
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286 bad_access_msg: |
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287 .asciz "Program tried to access illegal 68K address %X\n" |
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288 |
|
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289 .global m68k_write_word |
|
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bc3bc7a60c4e
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290 .global try_fifo_write |
|
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291 m68k_write_word: |
|
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2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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292 call inccycles |
|
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293 and $0xFFFFFF, %rdi |
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294 cmp $0x400000, %edi |
|
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295 jbe cart_w |
|
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296 cmp $0xE00000, %edi |
|
104
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297 jae workram_w |
|
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298 cmp $0xC00000, %edi |
|
104
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299 jae vdp_psg_w |
|
153
42c031184e8a
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300 cmp $0xA00000, %edi |
|
104
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|
301 jb not_io_w |
|
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
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302 cmp $0xA12000, %edi |
|
104
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|
303 jae not_io_w |
|
85
1db2a0b655d1
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|
304 jmp do_io_write_w |
|
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|
305 not_io_w: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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|
306 ret |
|
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|
307 workram_w: |
|
193
c66e4636f991
Implement support for self-modifying code
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|
308 and $0xFFFF, %edi |
|
18
3e7bfde7606e
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|
309 mov %cx, (%r9, %rdi) |
|
193
c66e4636f991
Implement support for self-modifying code
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|
310 mov %edi, %ecx |
|
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|
311 shr $10, %ecx |
|
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|
312 bt %ecx, 160(%rsi) |
|
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|
313 jnc not_code |
|
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|
314 call m68k_save_context |
|
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|
315 call m68k_handle_code_write |
|
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|
316 mov %rax, %rsi |
|
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|
317 call m68k_load_context |
|
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|
318 not_code: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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changeset
|
319 ret |
|
18
3e7bfde7606e
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320 cart_w: |
|
3e7bfde7606e
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|
321 mov %cx, (%r8, %rdi) |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
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changeset
|
322 ret |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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|
323 vdp_psg_w: |
|
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diff
changeset
|
324 test $0x2700E0, %edi |
|
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changeset
|
325 jnz crash |
|
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changeset
|
326 and $0x1F, %edi |
|
3b79cbcf6846
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changeset
|
327 cmp $4, %edi |
|
104
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328 jb try_fifo_write |
|
54
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|
329 jmp do_vdp_port_write |
|
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330 try_fifo_write: |
|
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331 push %rdx |
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332 push %rbx |
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|
333 /* fetch VDP context pointer from 68K context */ |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
334 mov 128(%rsi), %rdx |
|
149
139e5dcd6aa3
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|
335 /* check DMA flag */ |
|
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336 bt $6, 19(%rdx) |
|
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337 jc fifo_fallback |
|
54
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|
338 /* get fifo_cur and compare it to fifo_end */ |
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339 mov (%rdx), %rbx |
|
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340 cmp %rbx, 8(%rdx) |
|
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341 /* bail out if fifo is full */ |
|
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342 je fifo_fallback |
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|
343 /* populate FIFO entry */ |
| 138 | 344 mov %cx, 6(%rbx) /* value */ |
| 345 mov 16(%rdx), %cx | |
| 346 mov %cx, 4(%rbx) /* address */ | |
| 347 mov 18(%rdx), %cl | |
| 348 mov %cl, 8(%rbx) /* cd */ | |
| 349 movb $0, 9(%rbx) /* partial */ | |
|
54
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|
350 mov %eax, %ecx |
|
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351 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */ |
|
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352 sub %eax, %ecx |
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|
353 mov %ecx, (%rbx) /* cycle */ |
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|
354 /* update fifo_cur and store back in 68K context */ |
| 138 | 355 add $12, %rbx |
|
54
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356 mov %rbx, (%rdx) |
| 138 | 357 /* update address register */ |
| 358 movzbw 35(%rdx), %bx | |
| 359 add %bx, 16(%rdx) | |
|
54
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|
360 /* clear pending flag */ |
|
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|
361 andb $0xEF, 19(%rdx) |
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362 pop %rbx |
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363 pop %rdx |
|
64
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|
364 ret |
|
54
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365 fifo_fallback: |
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366 pop %rbx |
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367 pop %rdx |
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368 jmp do_vdp_port_write |
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369 crash: |
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|
370 mov %edi, %esi |
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|
371 lea bad_access_msg(%rip), %rdi |
|
160
69ac23d42897
Fix crash in printf from "crash" function due to lack of clearing rax
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372 xor %rax, %rax |
|
54
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373 call printf |
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374 mov $1, %rdi |
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375 call exit |
|
18
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376 |
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377 .global m68k_write_byte |
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378 m68k_write_byte: |
|
64
2b1a65f4b85d
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379 call inccycles |
|
18
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380 and $0xFFFFFF, %rdi |
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381 cmp $0x400000, %edi |
|
104
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382 jbe cart_wb |
|
18
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383 cmp $0xE00000, %edi |
|
104
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384 jae workram_wb |
| 66 | 385 cmp $0xC00000, %edi |
|
104
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386 jae vdp_psg_wb |
|
153
42c031184e8a
Implement access to Z80 RAM
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387 cmp $0xA00000, %edi |
|
104
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388 jb not_io_wb |
|
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
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389 cmp $0xA12000, %edi |
|
104
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390 jae not_io_wb |
| 66 | 391 jmp do_io_write |
| 392 not_io_wb: | |
|
64
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|
393 ret |
|
18
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394 workram_wb: |
|
83
2c7267617d71
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|
395 /* deal with byte swapping */ |
|
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|
396 xor $1, %edi |
|
18
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397 and $0xFFFF, %rdi |
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398 mov %cl, (%r9, %rdi) |
|
193
c66e4636f991
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|
399 mov %edi, %ecx |
|
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|
400 shr $10, %ecx |
|
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|
401 bt %ecx, 160(%rsi) |
|
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changeset
|
402 jnc not_code_b |
|
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changeset
|
403 xor $1, %edi |
|
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changeset
|
404 call m68k_save_context |
|
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|
405 call m68k_handle_code_write |
|
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|
406 mov %rax, %rsi |
|
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changeset
|
407 call m68k_load_context |
|
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changeset
|
408 not_code_b: |
|
64
2b1a65f4b85d
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59
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changeset
|
409 ret |
|
18
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changeset
|
410 cart_wb: |
|
83
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82
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changeset
|
411 /* deal with byte swapping */ |
|
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82
diff
changeset
|
412 xor $1, %edi |
|
18
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changeset
|
413 mov %cl, (%r8, %rdi) |
|
64
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changeset
|
414 ret |
| 66 | 415 vdp_psg_wb: |
| 416 push %rdx | |
| 417 mov %cl, %dl | |
| 418 and $0xFF, %cx | |
| 419 shl $8, %dx | |
| 420 or %dx, %cx | |
| 421 pop %rdx | |
| 422 jmp vdp_psg_w | |
|
18
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|
423 |
|
3e7bfde7606e
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changeset
|
424 .global m68k_write_long_lowfirst |
|
3e7bfde7606e
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changeset
|
425 m68k_write_long_lowfirst: |
|
3e7bfde7606e
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changeset
|
426 push %rdi |
|
86
3d3966c254b2
RTE doesn't crash the emulator anymore
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85
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changeset
|
427 push %rcx |
|
18
3e7bfde7606e
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changeset
|
428 add $2, %edi |
|
3e7bfde7606e
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17
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changeset
|
429 call m68k_write_word |
|
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
430 pop %rcx |
|
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
431 pop %rdi |
|
18
3e7bfde7606e
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17
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changeset
|
432 shr $16, %ecx |
|
3e7bfde7606e
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17
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changeset
|
433 jmp m68k_write_word |
|
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17
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changeset
|
434 |
|
3e7bfde7606e
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17
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changeset
|
435 .global m68k_write_long_highfirst |
|
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changeset
|
436 m68k_write_long_highfirst: |
|
3e7bfde7606e
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changeset
|
437 push %rdi |
|
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17
diff
changeset
|
438 push %rcx |
|
3e7bfde7606e
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17
diff
changeset
|
439 shr $16, %ecx |
|
3e7bfde7606e
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17
diff
changeset
|
440 call m68k_write_word |
|
3e7bfde7606e
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diff
changeset
|
441 pop %rcx |
|
3e7bfde7606e
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changeset
|
442 pop %rdi |
|
3e7bfde7606e
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17
diff
changeset
|
443 add $2, %rdi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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17
diff
changeset
|
444 jmp m68k_write_word |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
445 |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
446 inccycles: |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
447 cmp %rbp, %rax |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
448 jnb do_limit |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
449 add $4, %rax |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
450 ret |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
451 do_limit: |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
452 push %rcx |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
453 push %rdi |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
454 call handle_cycle_limit |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
455 pop %rdi |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
456 pop %rcx |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
457 add $4, %rax |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
458 ret |
|
17
de0085d4ea40
Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
460 .global m68k_read_word_scratch1 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
461 m68k_read_word_scratch1: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
462 call inccycles |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
463 and $0xFFFFFF, %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
464 cmp $0x400000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
465 jbe cart |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
466 cmp $0xE00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
467 jae workram |
|
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
468 cmp $0xC00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
469 jae vdp_psg |
|
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
470 cmp $0xA00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
471 jb not_io |
|
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
472 cmp $0xA12000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
473 jae not_io |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
474 call do_io_read_w |
|
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
475 ret |
|
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
476 not_io: |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
477 xor %cx, %cx |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
478 dec %cx |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
479 ret |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
480 workram: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
481 and $0xFFFF, %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
482 mov (%r9, %rcx), %cx |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
483 ret |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
484 vdp_psg: |
|
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
485 test $0x2700E0, %ecx |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
486 jnz crash |
|
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
487 and $0x1F, %ecx |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
488 jmp do_vdp_port_read |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
489 cart: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
490 mov (%r8, %rcx), %cx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
491 ret |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
492 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
493 .global m68k_read_long_scratch1 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
494 m68k_read_long_scratch1: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
495 push %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
496 call m68k_read_word_scratch1 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
497 mov %cx, %di |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
498 pop %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
499 add $2, %ecx |
|
84
2d1ae596db7a
Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents:
83
diff
changeset
|
500 push %rdi |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
501 call m68k_read_word_scratch1 |
|
84
2d1ae596db7a
Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents:
83
diff
changeset
|
502 pop %rdi |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
503 and $0xFFFF, %ecx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
504 shl $16, %edi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
505 or %edi, %ecx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
506 ret |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
507 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
508 .global m68k_read_byte_scratch1 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
509 m68k_read_byte_scratch1: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
510 call inccycles |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
511 and $0xFFFFFF, %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
512 cmp $0x400000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
513 jbe cart_b |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
514 cmp $0xE00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
515 jae workram_b |
| 137 | 516 cmp $0xC00000, %ecx |
| 517 jae vdp_psg_b | |
|
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
518 cmp $0xA00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
519 jb not_io_b |
|
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
520 cmp $0xA12000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
521 jae not_io_b |
| 66 | 522 jmp do_io_read |
| 523 not_io_b: | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
524 xor %cl, %cl |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
525 dec %cl |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
526 ret |
| 137 | 527 vdp_psg_b: |
| 528 test $0x2700E0, %ecx | |
| 529 jnz crash | |
| 530 and $0x1F, %ecx | |
| 531 bt $0, %ecx | |
| 532 jnc vdp_swap | |
| 533 jmp do_vdp_port_read | |
| 534 vdp_swap: | |
| 535 call do_vdp_port_read | |
| 536 shr $8, %cx | |
| 537 ret | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
538 workram_b: |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
539 /* deal with byte swapping */ |
|
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
540 xor $1, %ecx |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
541 and $0xFFFF, %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
542 mov (%r9, %rcx), %cl |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
543 ret |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
544 cart_b: |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
545 /* deal with byte swapping */ |
|
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
546 xor $1, %ecx |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
547 mov (%r8, %rcx), %cl |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
548 ret |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
549 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
550 .global m68k_modified_ret_addr |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
551 m68k_modified_ret_addr: |
|
145
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
552 add $16, %rsp |
|
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
553 call m68k_native_addr |
|
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
554 jmp *%rcx |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
555 |
|
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
556 dyn_addr_msg: |
|
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
557 .asciz "Program needs dynamically calculated native address\n" |
|
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
558 |
|
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
559 .global m68k_native_addr_and_sync |
|
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
560 m68k_native_addr_and_sync: |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
561 call m68k_save_context |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
562 push %rcx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
563 mov %rsi, %rdi |
|
198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
564 xor %esi, %esi |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
565 call sync_components |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
566 pop %rsi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
567 push %rax |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
568 mov %rax, %rdi |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
569 call get_native_address_trans |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
570 mov %rax, %rcx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
571 pop %rsi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
572 call m68k_load_context |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
573 ret |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
574 |
|
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
575 .global m68k_native_addr |
|
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
576 m68k_native_addr: |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
577 call m68k_save_context |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
578 push %rsi |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
579 mov %rsi, %rdi |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
580 mov %ecx, %esi |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
581 call get_native_address_trans |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
582 mov %rax, %rcx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
583 pop %rsi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
584 call m68k_load_context |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
585 ret |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
586 |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
587 .global m68k_retrans_stub |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
588 m68k_retrans_stub: |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
589 call m68k_save_context |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
590 push %rsi |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
591 call m68k_retranslate_inst |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
592 pop %rsi |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
593 mov %rax, %rcx |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
594 call m68k_load_context |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
595 jmp *%rcx |
|
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
596 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
597 .global m68k_save_context |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
598 m68k_save_context: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
599 mov %bl, 1(%rsi) /* N Flag */ |
| 207 | 600 mov %dl, 2(%rsi) /* Z flag */ |
| 601 mov %bh, 3(%rsi) /* V flag */ | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
602 mov %dh, 4(%rsi) /* C flag */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
603 mov %r10d, 8(%rsi) /* d0 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
604 mov %r11d, 12(%rsi) /* d1 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
605 mov %r12d, 16(%rsi) /* d2 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
606 mov %r13d, 40(%rsi) /* a0 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
607 mov %r14d, 44(%rsi) /* a1 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
608 mov %r15d, 68(%rsi) /* a7 */ |
|
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
609 mov %eax, 80(%rsi) /* current cycle count */ |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
610 ret |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
611 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
612 .global m68k_load_context |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
613 m68k_load_context: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
614 mov 1(%rsi), %bl /* N Flag */ |
| 207 | 615 mov 2(%rsi), %dl /* Z flag */ |
| 616 mov 3(%rsi), %bh /* V flag */ | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
617 mov 4(%rsi), %dh /* C flag */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
618 mov 8(%rsi), %r10d /* d0 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
619 mov 12(%rsi), %r11d /* d1 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
620 mov 16(%rsi), %r12d /* d2 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
621 mov 40(%rsi), %r13d /* a0 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
622 mov 44(%rsi), %r14d /* a1 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
623 mov 68(%rsi), %r15d /* a7 */ |
|
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
624 mov 76(%rsi), %ebp /* target cycle count */ |
|
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
625 mov 80(%rsi), %eax /* current cycle count */ |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
626 mov 96(%rsi), %r8d /* cartridge address */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
627 mov 104(%rsi), %r9d /* work ram address */ |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
628 ret |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
629 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
630 .global m68k_start_context |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
631 m68k_start_context: |
|
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
632 push %rbp |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
633 push %r12 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
634 push %r13 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
635 push %r14 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
636 push %r15 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
637 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
638 call m68k_load_context |
|
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
639 call *%rdi |
|
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
640 call m68k_save_context |
|
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
641 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
642 pop %r15 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
643 pop %r14 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
644 pop %r13 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
645 pop %r12 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
646 pop %rbp |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
647 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
648 ret |