repos/blastem: runtime.S annotate

annotate runtime.S @ 194:811163790e6c

Implement ABCD an SBCD. Fix BTEST with register source.

author	Mike Pavone <pavone@retrodev.com>
date	Wed, 16 Jan 2013 22:40:56 -0800
parents	c66e4636f991
children	209a37eed3e7

rev	line source
17 de0085d4ea40 Add asssembly runtime code stub Mike Pavone <pavone@retrodev.com> parents: diff changeset	1
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	2 .global handle_cycle_limit
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	3 .global do_sync
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	4 handle_cycle_limit:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	5 cmp 84(%rsi), %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	6 jb skip_sync
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	7 do_sync:
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	8 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	9 mov %rsi, %rdi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	10 call sync_components
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	11 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	12 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	13 skip_sync:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	14 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	15
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	16 .global handle_cycle_limit_int
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	17 handle_cycle_limit_int:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	18 cmp 88(%rsi), %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	19 jb skip_int
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	20 /* swap USP and SSP if not already in supervisor mode */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	21 bt $5, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	22 jc already_supervisor
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	23 mov 72(%rsi), %edi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	24 mov %r15d, 72(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	25 mov %edi, %r15d
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	26 already_supervisor:
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	27 /* save PC */
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	28 sub $4, %r15d
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	29 mov %r15d, %edi
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	30 call m68k_write_long_lowfirst
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	31 /* save status register on stack */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	32 sub $2, %r15d
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	33 mov %r15d, %edi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	34 call get_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	35 call m68k_write_word
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	36 /* update status register */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	37 andb $0xF8, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	38 mov 92(%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	39 or $0x20, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	40 or %cl, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	41 /* calculate interrupt vector address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	42 mov 92(%rsi), %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	43 shl $2, %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	44 add $0x60, %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	45 call m68k_read_long_scratch1
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	46 call m68k_native_addr_and_sync
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	47 add $24, %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	48 /* discard function return address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	49 pop %rdi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	50 jmp *%rcx
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	51 ret
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	52 skip_int:
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	53 cmp 84(%rsi), %eax
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	54 jnb do_sync
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	55 ret
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	56
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	57 .global m68k_trap
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	58 m68k_trap:
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	59 push %rdi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	60 push %rcx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	61 /* swap USP and SSP if not already in supervisor mode */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	62 bt $5, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	63 jc already_supervisor_trap
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	64 mov 72(%rsi), %edi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	65 mov %r15d, 72(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	66 mov %edi, %r15d
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	67 already_supervisor_trap:
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	68 /* save PC */
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	69 sub $4, %r15d
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	70 mov %r15d, %edi
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	71 pop %rcx
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	72 call m68k_write_long_lowfirst
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	73 /* save status register on stack */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	74 sub $2, %r15d
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	75 mov %r15d, %edi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	76 call get_sr
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	77 call m68k_write_word
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	78 /* update status register */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	79 andb $0xF8, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	80 mov 92(%rsi), %cl
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	81 or $0x20, %cl
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	82 or %cl, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	83 /* calculate interrupt vector address */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	84 pop %rcx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	85 shl $2, %ecx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	86 add $0x80, %ecx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	87 call m68k_read_long_scratch1
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	88 call m68k_native_addr_and_sync
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	89 add $24, %eax
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	90 jmp *%rcx
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	91
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	92 invalid_msg:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	93 .asciz "Invalid instruction at %X\n"
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	94
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	95 .global m68k_invalid
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	96 m68k_invalid:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	97 lea invalid_msg(%rip), %rdi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	98 mov %ecx, %esi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	99 xor %rax, %rax
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	100 call printf
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	101 mov $1, %rdi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	102 call exit
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	103
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	104 .global bcd_add
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	105 bcd_add:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	106 xchg %rax, %rdi
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	107
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	108 mov %cl, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	109 mov %al, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	110 and $0xF, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	111 and $0xF, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	112 and $0xF0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	113 and $0xF0, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	114 add %ah, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	115 cmp $10, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	116 jb no_adjust
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	117 add $6, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	118 no_adjust:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	119 add %ch, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	120 add %al, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	121 mov $0, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	122 jc def_adjust
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	123 cmp $0xA0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	124 jb no_adjust_h
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	125 def_adjust:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	126 add $0x60, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	127 mov $1, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	128 no_adjust_h:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	129
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	130 mov %rdi, %rax
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	131 ret
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	132
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	133 .global bcd_sub
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	134 bcd_sub:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	135 xchg %rax, %rdi
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	136
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	137 mov %cl, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	138 mov %al, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	139 and $0xF, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	140 and $0xF, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	141 and $0xF0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	142 and $0xF0, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	143 sub %ah, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	144 cmp $10, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	145 jb no_adjusts
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	146 sub $6, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	147 no_adjusts:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	148 add %ch, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	149 sub %al, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	150 mov $0, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	151 jc def_adjusts
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	152 cmp $0xA0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	153 jb no_adjust_hs
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	154 def_adjusts:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	155 sub $0x60, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	156 mov $1, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	157 no_adjust_hs:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	158
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	159 mov %rdi, %rax
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	160 ret
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	161
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	162 int_dbg_msg:
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	163 .asciz "Executing Interrupt!"
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	164 print_int_dbg:
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	165 call m68k_save_context
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	166 push %rsi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	167 lea int_dbg_msg(%rip), %rdi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	168 call puts
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	169 pop %rsi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	170 call m68k_load_context
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	171 ret
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	172
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	173 .global get_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	174 get_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	175 mov 5(%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	176 shl $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	177 mov (%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	178 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	179 or %bl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	180 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	181 or %dl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	182 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	183 or %bh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	184 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	185 or %dh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	186 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	187
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	188 .global set_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	189 set_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	190 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	191 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	192 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	193 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	194 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	195 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	196 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	197 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	198 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	199 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	200 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	201 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	202 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	203 mov %cl, (%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	204 shr $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	205 mov %cl, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	206 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	207
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	208 .global set_ccr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	209 set_ccr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	210 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	211 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	212 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	213 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	214 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	215 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	216 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	217 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	218 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	219 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	220 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	221 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	222 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	223 mov %cl, (%rsi)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	224 ret
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	225
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	226 do_vdp_port_write:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	227 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	228 mov %rcx, %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	229 call vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	230 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	231 call m68k_load_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	232 ret
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	233
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	234 do_vdp_port_read:
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	235 mov %ecx, %edi
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	236 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	237 call vdp_port_read
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	238 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	239 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	240 mov 136(%rsi), %cx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	241 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	242
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	243 do_io_write:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	244 call m68k_save_context
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	245 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	246 mov %ecx, %edx
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	247 call io_write
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	248 mov %rax, %rsi
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	249 call m68k_load_context
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	250 ret
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	251 do_io_read:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	252 mov %ecx, %edi
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	253 and $0x1FFFF, %edi
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	254 call m68k_save_context
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	255 call io_read
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	256 mov %rax, %rsi
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	257 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	258 mov 136(%rsi), %cl
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	259 ret
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	260
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	261 do_io_write_w:
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	262 call m68k_save_context
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	263 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	264 mov %ecx, %edx
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	265 call io_write_w
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	266 mov %rax, %rsi
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	267 call m68k_load_context
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	268 ret
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	269 do_io_read_w:
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	270 mov %ecx, %edi
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	271 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	272 call m68k_save_context
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	273 call io_read_w
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	274 mov %rax, %rsi
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	275 call m68k_load_context
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	276 mov 136(%rsi), %cx
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	277 ret
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	278
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	279 bad_access_msg:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	280 .asciz "Program tried to access illegal 68K address %X\n"
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	281
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	282 .global m68k_write_word
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	283 .global try_fifo_write
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	284 m68k_write_word:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	285 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	286 and $0xFFFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	287 cmp $0x400000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	288 jbe cart_w
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	289 cmp $0xE00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	290 jae workram_w
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	291 cmp $0xC00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	292 jae vdp_psg_w
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	293 cmp $0xA00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	294 jb not_io_w
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	295 cmp $0xA12000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	296 jae not_io_w
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	297 jmp do_io_write_w
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	298 not_io_w:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	299 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	300 workram_w:
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	301 and $0xFFFF, %edi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	302 mov %cx, (%r9, %rdi)
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	303 mov %edi, %ecx
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	304 shr $10, %ecx
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	305 bt %ecx, 160(%rsi)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	306 jnc not_code
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	307 call m68k_save_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	308 call m68k_handle_code_write
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	309 mov %rax, %rsi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	310 call m68k_load_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	311 not_code:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	312 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	313 cart_w:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	314 mov %cx, (%r8, %rdi)
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	315 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	316 vdp_psg_w:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	317 test $0x2700E0, %edi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	318 jnz crash
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	319 and $0x1F, %edi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	320 cmp $4, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	321 jb try_fifo_write
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	322 jmp do_vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	323 try_fifo_write:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	324 push %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	325 push %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	326 /* fetch VDP context pointer from 68K context */
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	327 mov 128(%rsi), %rdx
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	328 /* check DMA flag */
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	329 bt $6, 19(%rdx)
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	330 jc fifo_fallback
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	331 /* get fifo_cur and compare it to fifo_end */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	332 mov (%rdx), %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	333 cmp %rbx, 8(%rdx)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	334 /* bail out if fifo is full */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	335 je fifo_fallback
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	336 /* populate FIFO entry */
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	337 mov %cx, 6(%rbx) /* value */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	338 mov 16(%rdx), %cx
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	339 mov %cx, 4(%rbx) /* address */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	340 mov 18(%rdx), %cl
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	341 mov %cl, 8(%rbx) /* cd */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	342 movb $0, 9(%rbx) /* partial */
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	343 mov %eax, %ecx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	344 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	345 sub %eax, %ecx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	346 mov %ecx, (%rbx) /* cycle */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	347 /* update fifo_cur and store back in 68K context */
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	348 add $12, %rbx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	349 mov %rbx, (%rdx)
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	350 /* update address register */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	351 movzbw 35(%rdx), %bx
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	352 add %bx, 16(%rdx)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	353 /* clear pending flag */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	354 andb $0xEF, 19(%rdx)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	355 pop %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	356 pop %rdx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	357 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	358 fifo_fallback:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	359 pop %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	360 pop %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	361 jmp do_vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	362 crash:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	363 mov %edi, %esi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	364 lea bad_access_msg(%rip), %rdi
160 69ac23d42897 Fix crash in printf from "crash" function due to lack of clearing rax Mike Pavone <pavone@retrodev.com> parents: 153 diff changeset	365 xor %rax, %rax
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	366 call printf
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	367 mov $1, %rdi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	368 call exit
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	369
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	370 .global m68k_write_byte
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	371 m68k_write_byte:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	372 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	373 and $0xFFFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	374 cmp $0x400000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	375 jbe cart_wb
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	376 cmp $0xE00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	377 jae workram_wb
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	378 cmp $0xC00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	379 jae vdp_psg_wb
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	380 cmp $0xA00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	381 jb not_io_wb
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	382 cmp $0xA12000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	383 jae not_io_wb
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	384 jmp do_io_write
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	385 not_io_wb:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	386 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	387 workram_wb:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	388 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	389 xor $1, %edi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	390 and $0xFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	391 mov %cl, (%r9, %rdi)
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	392 mov %edi, %ecx
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	393 shr $10, %ecx
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	394 bt %ecx, 160(%rsi)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	395 jnc not_code_b
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	396 xor $1, %edi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	397 call m68k_save_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	398 call m68k_handle_code_write
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	399 mov %rax, %rsi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	400 call m68k_load_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	401 not_code_b:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	402 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	403 cart_wb:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	404 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	405 xor $1, %edi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	406 mov %cl, (%r8, %rdi)
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	407 ret
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	408 vdp_psg_wb:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	409 push %rdx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	410 mov %cl, %dl
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	411 and $0xFF, %cx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	412 shl $8, %dx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	413 or %dx, %cx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	414 pop %rdx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	415 jmp vdp_psg_w
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	416
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	417 .global m68k_write_long_lowfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	418 m68k_write_long_lowfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	419 push %rdi
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	420 push %rcx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	421 add $2, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	422 call m68k_write_word
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	423 pop %rcx
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	424 pop %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	425 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	426 jmp m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	427
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	428 .global m68k_write_long_highfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	429 m68k_write_long_highfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	430 push %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	431 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	432 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	433 call m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	434 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	435 pop %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	436 add $2, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	437 jmp m68k_write_word
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	438
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	439 inccycles:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	440 cmp %rbp, %rax
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	441 jnb do_limit
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	442 add $4, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	443 ret
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	444 do_limit:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	445 push %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	446 push %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	447 call handle_cycle_limit
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	448 pop %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	449 pop %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	450 add $4, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	451 ret
17 de0085d4ea40 Add asssembly runtime code stub Mike Pavone <pavone@retrodev.com> parents: diff changeset	452
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	453 .global m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	454 m68k_read_word_scratch1:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	455 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	456 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	457 cmp $0x400000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	458 jbe cart
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	459 cmp $0xE00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	460 jae workram
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	461 cmp $0xC00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	462 jae vdp_psg
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	463 cmp $0xA00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	464 jb not_io
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	465 cmp $0xA12000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	466 jae not_io
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	467 call do_io_read_w
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	468 ret
7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	469 not_io:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	470 xor %cx, %cx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	471 dec %cx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	472 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	473 workram:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	474 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	475 mov (%r9, %rcx), %cx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	476 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	477 vdp_psg:
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	478 test $0x2700E0, %ecx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	479 jnz crash
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	480 and $0x1F, %ecx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	481 jmp do_vdp_port_read
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	482 cart:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	483 mov (%r8, %rcx), %cx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	484 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	485
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	486 .global m68k_read_long_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	487 m68k_read_long_scratch1:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	488 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	489 call m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	490 mov %cx, %di
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	491 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	492 add $2, %ecx
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	493 push %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	494 call m68k_read_word_scratch1
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	495 pop %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	496 and $0xFFFF, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	497 shl $16, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	498 or %edi, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	499 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	500
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	501 .global m68k_read_byte_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	502 m68k_read_byte_scratch1:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	503 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	504 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	505 cmp $0x400000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	506 jbe cart_b
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	507 cmp $0xE00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	508 jae workram_b
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	509 cmp $0xC00000, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	510 jae vdp_psg_b
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	511 cmp $0xA00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	512 jb not_io_b
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	513 cmp $0xA12000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	514 jae not_io_b
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	515 jmp do_io_read
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	516 not_io_b:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	517 xor %cl, %cl
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	518 dec %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	519 ret
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	520 vdp_psg_b:
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	521 test $0x2700E0, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	522 jnz crash
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	523 and $0x1F, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	524 bt $0, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	525 jnc vdp_swap
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	526 jmp do_vdp_port_read
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	527 vdp_swap:
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	528 call do_vdp_port_read
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	529 shr $8, %cx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	530 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	531 workram_b:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	532 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	533 xor $1, %ecx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	534 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	535 mov (%r9, %rcx), %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	536 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	537 cart_b:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	538 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	539 xor $1, %ecx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	540 mov (%r8, %rcx), %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	541 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	542
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	543 .global m68k_modified_ret_addr
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	544 m68k_modified_ret_addr:
145 15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	545 add $16, %rsp
15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	546 call m68k_native_addr
15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	547 jmp *%rcx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	548
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	549 dyn_addr_msg:
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	550 .asciz "Program needs dynamically calculated native address\n"
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	551
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	552 .global m68k_native_addr_and_sync
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	553 m68k_native_addr_and_sync:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	554 call m68k_save_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	555 push %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	556 mov %rsi, %rdi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	557 call sync_components
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	558 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	559 push %rax
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	560 mov %rax, %rdi
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	561 call get_native_address_trans
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	562 mov %rax, %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	563 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	564 call m68k_load_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	565 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	566
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	567 .global m68k_native_addr
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	568 m68k_native_addr:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	569 call m68k_save_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	570 push %rsi
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	571 mov %rsi, %rdi
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	572 mov %ecx, %esi
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	573 call get_native_address_trans
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	574 mov %rax, %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	575 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	576 call m68k_load_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	577 ret
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	578
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	579 .global m68k_retrans_stub
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	580 m68k_retrans_stub:
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	581 call m68k_save_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	582 push %rsi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	583 call m68k_retranslate_inst
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	584 pop %rsi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	585 mov %rax, %rcx
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	586 call m68k_load_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	587 jmp *%rcx
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	588
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	589 .global m68k_save_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	590 m68k_save_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	591 mov %bl, 1(%rsi) /* N Flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	592 mov %bh, 2(%rsi) /* V flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	593 mov %dl, 3(%rsi) /* Z flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	594 mov %dh, 4(%rsi) /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	595 mov %r10d, 8(%rsi) /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	596 mov %r11d, 12(%rsi) /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	597 mov %r12d, 16(%rsi) /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	598 mov %r13d, 40(%rsi) /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	599 mov %r14d, 44(%rsi) /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	600 mov %r15d, 68(%rsi) /* a7 */
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	601 mov %eax, 80(%rsi) /* current cycle count */
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	602 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	603
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	604 .global m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	605 m68k_load_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	606 mov 1(%rsi), %bl /* N Flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	607 mov 2(%rsi), %bh /* V flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	608 mov 3(%rsi), %dl /* Z flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	609 mov 4(%rsi), %dh /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	610 mov 8(%rsi), %r10d /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	611 mov 12(%rsi), %r11d /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	612 mov 16(%rsi), %r12d /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	613 mov 40(%rsi), %r13d /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	614 mov 44(%rsi), %r14d /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	615 mov 68(%rsi), %r15d /* a7 */
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	616 mov 76(%rsi), %ebp /* target cycle count */
7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	617 mov 80(%rsi), %eax /* current cycle count */
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	618 mov 96(%rsi), %r8d /* cartridge address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	619 mov 104(%rsi), %r9d /* work ram address */
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	620 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	621
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	622 .global m68k_start_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	623 m68k_start_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	624 call m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	625 jmp *%rdi

Mercurial > repos > blastem

annotate runtime.S @ 194:811163790e6c