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annotate gentests.py @ 1889:377f110e4cea

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Report more accurate frame and sample rates to frontend in libretro target
author Michael Pavone <pavone@retrodev.com>
date Sat, 21 Sep 2019 20:26:12 -0700
parents f6ee0df6bb48
children ab577e2ed66a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #!/usr/bin/env python
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2
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3 def split_fields(line):
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4 parts = []
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5 while line:
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6 field,_,line = line.partition('\t')
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7 parts.append(field.strip())
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8 while line.startswith('\t'):
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9 line = line[1:]
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10 return parts
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11
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12 class Program(object):
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13 def __init__(self, instruction):
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14 self.avail_dregs = {0,1,2,3,4,5,6,7}
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15 self.avail_aregs = {0,1,2,3,4,5,6,7}
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16 instruction.consume_regs(self)
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17 self.inst = instruction
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18
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19 def dirname(self):
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20 return self.inst.name + '_' + self.inst.size
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21 def name(self):
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22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
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23
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24 def write_rom_test(self, outfile):
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25 outfile.write('\tdc.l $0, start\n')
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26 needdivzero = self.inst.name.startswith('div')
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27 needchk = self.inst.name.startswith('chk')
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28 for i in xrange(0x8, 0x100, 0x4):
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29 if needdivzero and i == 0x14:
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30 outfile.write('\tdc.l div_zero_handler\n')
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31 elif needchk and i == 0x18:
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32 outfile.write('\tdc.l chk_handler\n')
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33 else:
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34 outfile.write('\tdc.l empty_handler\n')
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35 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n')
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36 if needdivzero:
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37 outfile.write('div_zero_handler:\n')
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38 div_zero_count = self.get_dreg()
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39 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n')
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40 outfile.write('\trte\n')
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41 if needchk:
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42 outfile.write('chk_handler:\n')
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43 chk_count = self.get_dreg()
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44 outfile.write('\taddq #1, ' + str(chk_count) + '\n')
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45 outfile.write('\trte\n')
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46 outfile.write('start:\n\tmove #0, CCR\n')
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47 if needdivzero:
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48 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n')
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49 already = {}
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50 self.inst.write_init(outfile, already)
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51 if 'label' in already:
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52 outfile.write('lbl_' + str(already['label']) + ':\n')
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53 outfile.write('\t'+str(self.inst)+'\n')
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54 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
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55 save_ccr = self.get_dreg()
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56 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
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57 outfile.write('\tmove #$1F, CCR\n')
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58 self.inst.invalidate_dest(already)
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59 self.inst.write_init(outfile, already)
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60 if 'label' in already:
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61 outfile.write('lbl_' + str(already['label']) + ':\n')
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62 outfile.write('\t'+str(self.inst)+'\n')
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63 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
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64 outfile.write('\treset\nforever:\n\tbra.s forever\n')
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65
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66 def consume_dreg(self, num):
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67 self.avail_dregs.discard(num)
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68
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69 def consume_areg(self, num):
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70 self.avail_aregs.discard(num)
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71
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72 def get_dreg(self):
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73 return Register('d', self.avail_dregs.pop())
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74
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75 class Dummy(object):
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76 def __str__(self):
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77 return ''
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78 def write_init(self, outfile, size, already):
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79 pass
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80 def consume_regs(self, program):
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81 pass
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82
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83 dummy_op = Dummy()
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84
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85 class Register(object):
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86 def __init__(self, kind, num):
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87 self.kind = kind
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88 self.num = num
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89
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90 def __str__(self):
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91 if self.kind == 'd' or self.kind == 'a':
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92 return self.kind + str(self.num)
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93 return self.kind
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94
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95 def write_init(self, outfile, size, already):
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96 if not str(self) in already:
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97 minv,maxv = get_size_range(size)
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98 val = randint(minv,maxv)
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99 already[str(self)] = val
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100 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
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101
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102 def consume_regs(self, program):
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103 if self.kind == 'd':
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104 program.consume_dreg(self.num)
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105 elif self.kind == 'a':
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106 program.consume_areg(self.num)
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107
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108 def valid_ram_address(address, size='b'):
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109 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
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110
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111 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
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112 return randint(mina/2, maxa/2)*2 | 0xE00000
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113
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114 class Indexed(object):
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115 def __init__(self, base, index, index_size, disp):
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116 self.base = base
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117 self.index = index
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118 self.index_size = index_size
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119 self.disp = disp
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120
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121 def write_init(self, outfile, size, already):
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122 if self.base.kind == 'pc':
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123 if str(self.index) in already:
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124 index = already[str(self.index)]
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125 if self.index_size == 'w':
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126 index = index & 0xFFFF
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127 #sign extend index
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128 if index & 0x8000:
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129 index -= 65536
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130 if index > -1024:
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131 index = already[str(self.index)] = 2 * randint(-16384, -512)
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132 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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133 else:
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134 index = already[str(self.index)] = 2 * randint(-16384, -512)
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135 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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136 num = already.get('label', 0)+1
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137 already['label'] = num
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138 if (already[str(self.index)] + self.disp) & 1:
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139 if self.disp > 0:
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140 self.disp -= 1
f6ee0df6bb48 Minor fix to 68K test generator script
Michael Pavone <pavone@retrodev.com>
parents: 1283
diff changeset
141 else:
f6ee0df6bb48 Minor fix to 68K test generator script
Michael Pavone <pavone@retrodev.com>
parents: 1283
diff changeset
142 self.disp += 1
214
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diff changeset
143 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
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parents:
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144 else:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
145 if self.base == self.index:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
146 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
147 if not valid_ram_address(already[str(self.base)]*2):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
148 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
149 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
150 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
151 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
152 base = index = already[str(self.base)]
214
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parents:
diff changeset
153 else:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
154 base = index = already[str(self.base)] = random_ram_address()/2
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
155 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
156 else:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
157 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
158 if not valid_ram_address(already[str(self.base)]):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
159 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
160 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
161 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
162 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
163 base = already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
164 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
165 base = already[str(self.base)] = random_ram_address()
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
166 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
167 if str(self.index) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
168 index = already[str(self.index)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
169 if self.index_size == 'w':
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
170 index = index & 0xFFFF
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
171 #sign extend index
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
172 if index & 0x8000:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
173 index -= 65536
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
174 if not valid_ram_address(base + index):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
175 index = already[str(self.index)] = randint(-64, 63)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
176 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
177 else:
214
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178 index = already[str(self.index)] = randint(-64, 63)
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parents:
diff changeset
179 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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180 address = base + index + self.disp
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181 if (address & 0xFFFFFF) < 0xE00000:
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parents:
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182 if (address & 0xFFFFFF) < 128:
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parents:
diff changeset
183 self.disp -= (address & 0xFFFFFF)
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parents:
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184 else:
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diff changeset
185 self.disp += 0xE00000-(address & 0xFFFFFF)
608
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
186 if self.disp > 127:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
187 self.disp = 127
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
188 elif self.disp < -128:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
189 self.disp = -128
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
190 address = base + index + self.disp
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diff changeset
191 elif (address & 0xFFFFFF) > 0xFFFFFC:
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parents:
diff changeset
192 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
608
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
193 if self.disp > 127:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
194 self.disp = 127
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
195 elif self.disp < -128:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
196 self.disp = -128
214
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parents:
diff changeset
197 address = base + index + self.disp
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diff changeset
198 if size != 'b' and address & 1:
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199 self.disp = self.disp ^ 1
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200 address = base + index + self.disp
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parents:
diff changeset
201 minv,maxv = get_size_range(size)
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parents:
diff changeset
202 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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203
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parents:
diff changeset
204 def __str__(self):
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parents:
diff changeset
205 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
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parents:
diff changeset
206
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parents:
diff changeset
207 def consume_regs(self, program):
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parents:
diff changeset
208 self.base.consume_regs(program)
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parents:
diff changeset
209 self.index.consume_regs(program)
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parents:
diff changeset
210
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 class Displacement(object):
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parents:
diff changeset
212 def __init__(self, base, disp):
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parents:
diff changeset
213 self.base = base
1283
188a60def81f Fixed some deficiencies in the 68K test generator
Michael Pavone <pavone@retrodev.com>
parents: 608
diff changeset
214 if disp & 1:
188a60def81f Fixed some deficiencies in the 68K test generator
Michael Pavone <pavone@retrodev.com>
parents: 608
diff changeset
215 disp += 1
188a60def81f Fixed some deficiencies in the 68K test generator
Michael Pavone <pavone@retrodev.com>
parents: 608
diff changeset
216 self.disp = disp
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217
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parents:
diff changeset
218 def write_init(self, outfile, size, already):
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parents:
diff changeset
219 if self.base.kind == 'pc':
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parents:
diff changeset
220 num = already.get('label', 0)+1
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parents:
diff changeset
221 already['label'] = num
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parents:
diff changeset
222 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
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parents:
diff changeset
223 else:
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parents:
diff changeset
224 if str(self.base) in already:
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parents:
diff changeset
225 if not valid_ram_address(already[str(self.base)]):
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parents:
diff changeset
226 del already[str(self.base)]
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parents:
diff changeset
227 self.write_init(outfile, size, already)
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parents:
diff changeset
228 return
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parents:
diff changeset
229 else:
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parents:
diff changeset
230 base = already[str(self.base)]
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parents:
diff changeset
231 else:
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parents:
diff changeset
232 base = already[str(self.base)] = random_ram_address()
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parents:
diff changeset
233 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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parents:
diff changeset
234 address = base + self.disp
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parents:
diff changeset
235 if (address & 0xFFFFFF) < 0xE00000:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 if (address & 0xFFFFFF) < 0x10000:
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parents:
diff changeset
237 self.disp -= (address & 0xFFFFFF)
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parents:
diff changeset
238 else:
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parents:
diff changeset
239 self.disp += 0xE00000-(address & 0xFFFFFF)
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parents:
diff changeset
240 address = base + self.disp
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parents:
diff changeset
241 elif (address & 0xFFFFFF) > 0xFFFFFC:
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parents:
diff changeset
242 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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parents:
diff changeset
243 address = base + self.disp
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parents:
diff changeset
244 if size != 'b' and address & 1:
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parents:
diff changeset
245 self.disp = self.disp ^ 1
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parents:
diff changeset
246 address = base + self.disp
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parents:
diff changeset
247 minv,maxv = get_size_range(size)
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parents:
diff changeset
248 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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249
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parents:
diff changeset
250 def __str__(self):
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parents:
diff changeset
251 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
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parents:
diff changeset
252
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parents:
diff changeset
253 def consume_regs(self, program):
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parents:
diff changeset
254 self.base.consume_regs(program)
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parents:
diff changeset
255
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parents:
diff changeset
256 class Indirect(object):
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parents:
diff changeset
257 def __init__(self, reg):
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parents:
diff changeset
258 self.reg = reg
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parents:
diff changeset
259
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parents:
diff changeset
260 def __str__(self):
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parents:
diff changeset
261 return '(' + str(self.reg) + ')'
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parents:
diff changeset
262
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parents:
diff changeset
263 def write_init(self, outfile, size, already):
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parents:
diff changeset
264 if str(self.reg) in already:
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parents:
diff changeset
265 if not valid_ram_address(already[str(self.reg)], size):
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parents:
diff changeset
266 del already[str(self.reg)]
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parents:
diff changeset
267 self.write_init(outfile, size, already)
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parents:
diff changeset
268 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
269 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
270 address = already[str(self.reg)]
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parents:
diff changeset
271 else:
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parents:
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272 address = random_ram_address()
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parents:
diff changeset
273 if size != 'b':
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parents:
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274 address = address & 0xFFFFFFFE
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parents:
diff changeset
275 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
276 already[str(self.reg)] = address
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parents:
diff changeset
277 minv,maxv = get_size_range(size)
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parents:
diff changeset
278 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
diff changeset
279
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parents:
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280 def consume_regs(self, program):
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parents:
diff changeset
281 self.reg.consume_regs(program)
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parents:
diff changeset
282
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parents:
diff changeset
283 class Increment(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
284 def __init__(self, reg):
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parents:
diff changeset
285 self.reg = reg
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
286
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
287 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
288 return '(' + str(self.reg) + ')+'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
289
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
290 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
291 if str(self.reg) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
292 if not valid_ram_address(already[str(self.reg)], size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
293 del already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
294 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
295 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
296 else:
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parents:
diff changeset
297 address = already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
298 else:
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parents:
diff changeset
299 address = random_ram_address()
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parents:
diff changeset
300 if size != 'b':
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parents:
diff changeset
301 address = address & 0xFFFFFFFE
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parents:
diff changeset
302 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
303 already[str(self.reg)] = address
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
305 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
306
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
307 def consume_regs(self, program):
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parents:
diff changeset
308 self.reg.consume_regs(program)
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parents:
diff changeset
309
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 class Decrement(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311 def __init__(self, reg):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
312 self.reg = reg
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
313
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
315 return '-(' + str(self.reg) + ')'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
316
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
317 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
318 if str(self.reg) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
319 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
320 del already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
321 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
325 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
326 address = random_ram_address(mina=0xE00004)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
327 if size != 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
328 address = address & 0xFFFFFFFE
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
329 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
330 already[str(self.reg)] = address
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
331 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
332 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
333
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
334 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
335 self.reg.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
336
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
337 class Absolute(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
338 def __init__(self, address, size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
339 self.address = address
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
340 self.size = size
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
341
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
342 def __str__(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343 return '(' + str(self.address) + ').' + self.size
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
344
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
346 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
347 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
348
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
349 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
350 pass
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
351
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
352 class Immediate(object):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
353 def __init__(self, value):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
354 self.value = value
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
355
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
356 def __str__(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
357 return '#' + str(self.value)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
358
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
359 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
360 pass
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
361
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
362 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
363 pass
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
364
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
365 all_dregs = [Register('d', i) for i in range(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
366 all_aregs = [Register('a', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
367 all_indirect = [Indirect(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
368 all_predec = [Decrement(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
369 all_postinc = [Increment(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
370 from random import randint
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
371 def all_indexed():
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
372 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
373
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
374 def all_disp():
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
375 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
376
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
377 def rand_pc_disp():
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
378 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
379
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380 def all_pc_indexed():
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
381 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
382
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
383 def rand_abs_short():
1283
188a60def81f Fixed some deficiencies in the 68K test generator
Michael Pavone <pavone@retrodev.com>
parents: 608
diff changeset
384 return [Absolute(random_ram_address(0xFFFF8000), 'w') for x in xrange(0, 8)]
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
385
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
386 def rand_abs_long():
1283
188a60def81f Fixed some deficiencies in the 68K test generator
Michael Pavone <pavone@retrodev.com>
parents: 608
diff changeset
387 return [Absolute(random_ram_address(), 'l') for x in xrange(0, 8)]
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
388
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 def get_size_range(size):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
390 if size == 'b':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
391 return (-128, 127)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
392 elif size == 'w':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
393 return (-32768, 32767)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
394 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
395 return (-2147483648, 2147483647)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
396
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
397 def rand_immediate(size):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
399
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
400 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
401
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
402 def get_variations(mode, size):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
403 mapping = {
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
404 'd':all_dregs,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
405 'a':all_aregs,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
406 '(a)':all_indirect,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
407 '-(a)':all_predec,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
408 '(a)+':all_postinc,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409 '(n,a)':all_disp,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
410 '(n,a,x)':all_indexed,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
411 '(n,pc)':rand_pc_disp,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
412 '(n,pc,x)':all_pc_indexed,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413 '(n).w':rand_abs_short,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
414 '(n).l':rand_abs_long
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
415 }
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
416 if mode in mapping:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
417 ret = mapping[mode]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
418 if type(ret) != list:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
419 ret = ret()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
420 return ret
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
421 elif mode == '#n':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
422 return rand_immediate(size)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
423 elif mode.startswith('#(') and mode.endswith(')'):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
424 inner = mode[2:-1]
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
425 start,sep,end = inner.rpartition('-')
220
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
426 start,end = int(start),int(end)
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
427 if end-start > 16:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
428 return [Immediate(randint(start, end)) for x in range(0,8)]
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
429 else:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
430 return [Immediate(num) for num in range(start, end+1)]
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
431 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
432 print "Don't know what to do with source type", mode
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
433 return None
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
434
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
435 class Inst2Op(object):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
436 def __init__(self, name, size, src, dst):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
437 self.name = name
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
438 self.size = size
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
439 self.src = src
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
440 self.dst = dst
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
441
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
442 def __str__(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
443 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
444
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
445 def write_init(self, outfile, already):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
446 self.src.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
447 self.dst.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
448
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
449 def invalidate_dest(self, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
450 if type(self.dst) == Register:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
451 del already[str(self.dst)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
452
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
453 def save_result(self, reg, always):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
454 if always or type(self.dst) != Register:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
455 if type(self.dst) == Decrement:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
456 src = Increment(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
457 elif type(self.dst) == Increment:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
458 src = Decrement(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
459 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
460 src = self.dst
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
461 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
462 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
463 return ''
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
464
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
465 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
466 self.src.consume_regs(program)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
467 self.dst.consume_regs(program)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
468
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
469 class Inst1Op(Inst2Op):
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
470 def __init__(self, name, size, dst):
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
471 super(Inst1Op, self).__init__(name, size, dummy_op, dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
472
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
473 def __str__(self):
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
474 return self.name + '.' + self.size + ' ' + str(self.dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
475
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
476 class Entry(object):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
477 def __init__(self, line):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
478 fields = split_fields(line)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
479 self.name = fields[0]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
480 sizes = fields[1]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
481 sources = fields[2].split(';')
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
482 if len(fields) > 3:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
483 dests = fields[3].split(';')
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
484 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
485 dests = None
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
486 combos = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
487 for size in sizes:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
488 for source in sources:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
489 if size != 'b' or source != 'a':
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
490 if dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
491 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
492 if size != 'b' or dest != 'a':
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
493 combos.append((size, source, dest))
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
494 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
495 combos.append((size, None, source))
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
496 self.cases = combos
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
497
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
498 def programs(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
499 res = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
500 for (size, src, dst) in self.cases:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
501 dests = get_variations(dst, size)
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
502 if src:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
503 sources = get_variations(src, size)
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
504 for source in sources:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
505 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
506 res.append(Program(Inst2Op(self.name, size, source, dest)))
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
507 else:
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
508 for dest in dests:
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
509 res.append(Program(Inst1Op(self.name, size, dest)))
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
510 return res
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
511
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
512 def process_entries(f):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
513 entries = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
514 for line in f:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
515 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
516 entries.append(Entry(line))
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
517 return entries
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
518
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
519 from os import path, mkdir
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
520 def main(args):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
521 entries = process_entries(open('testcases.txt'))
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
522 for entry in entries:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
523 programs = entry.programs()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
524 for program in programs:
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
525 dname = program.dirname()
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
526 if not path.exists('generated_tests/' + dname):
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
527 mkdir('generated_tests/' + dname)
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
528 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w')
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
529 program.write_rom_test(f)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
530 f.close()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
531
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
532 if __name__ == '__main__':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
533 import sys
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
534 main(sys.argv)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
535