Mercurial > repos > blastem
annotate blastem.c @ 268:6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
author | Mike Pavone <pavone@retrodev.com> |
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date | Thu, 02 May 2013 21:54:04 -0700 |
parents | 376df762ddf5 |
children | 969ee17471c5 |
rev | line source |
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1 #include "68kinst.h" |
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2 #include "m68k_to_x86.h" |
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3 #include "z80_to_x86.h" |
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4 #include "mem.h" |
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5 #include "vdp.h" |
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6 #include "render.h" |
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7 #include "blastem.h" |
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8 #include <stdio.h> |
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9 #include <stdlib.h> |
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10 #include <string.h> |
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11 |
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12 #define CARTRIDGE_WORDS 0x200000 |
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13 #define RAM_WORDS 32 * 1024 |
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14 #define Z80_RAM_BYTES 8 * 1024 |
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15 #define MCLKS_PER_68K 7 |
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16 #define MCLKS_PER_Z80 15 |
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17 //TODO: Figure out the exact value for this |
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18 #define MCLKS_PER_FRAME (MCLKS_LINE*262) |
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19 #define CYCLE_NEVER 0xFFFFFFFF |
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20 |
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21 uint16_t cart[CARTRIDGE_WORDS]; |
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22 uint16_t ram[RAM_WORDS]; |
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23 uint8_t z80_ram[Z80_RAM_BYTES]; |
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24 |
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25 io_port gamepad_1; |
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26 io_port gamepad_2; |
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27 |
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28 int headless = 0; |
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29 int z80_enabled = 1; |
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30 |
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31 #ifndef MIN |
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32 #define MIN(a,b) ((a) < (b) ? (a) : (b)) |
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33 #endif |
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34 |
166 | 35 #define SMD_HEADER_SIZE 512 |
36 #define SMD_MAGIC1 0x03 | |
37 #define SMD_MAGIC2 0xAA | |
38 #define SMD_MAGIC3 0xBB | |
39 #define SMD_BLOCK_SIZE 0x4000 | |
40 | |
41 int load_smd_rom(long filesize, FILE * f) | |
42 { | |
43 uint8_t block[SMD_BLOCK_SIZE]; | |
44 filesize -= SMD_HEADER_SIZE; | |
45 fseek(f, SMD_HEADER_SIZE, SEEK_SET); | |
46 | |
47 uint16_t * dst = cart; | |
48 while (filesize > 0) { | |
49 fread(block, 1, SMD_BLOCK_SIZE, f); | |
50 for (uint8_t *low = block, *high = (block+SMD_BLOCK_SIZE/2), *end = block+SMD_BLOCK_SIZE; high < end; high++, low++) { | |
51 *(dst++) = *high << 8 | *low; | |
52 } | |
53 filesize -= SMD_BLOCK_SIZE; | |
54 } | |
55 return 1; | |
56 } | |
57 | |
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58 int load_rom(char * filename) |
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59 { |
166 | 60 uint8_t header[10]; |
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61 FILE * f = fopen(filename, "rb"); |
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62 if (!f) { |
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63 return 0; |
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64 } |
166 | 65 fread(header, 1, sizeof(header), f); |
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66 fseek(f, 0, SEEK_END); |
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67 long filesize = ftell(f); |
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68 if (filesize/2 > CARTRIDGE_WORDS) { |
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69 //carts bigger than 4MB not currently supported |
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70 filesize = CARTRIDGE_WORDS*2; |
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71 } |
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72 fseek(f, 0, SEEK_SET); |
166 | 73 if (header[1] == SMD_MAGIC1 && header[8] == SMD_MAGIC2 && header[9] == SMD_MAGIC3) { |
74 int i; | |
75 for (i = 3; i < 8; i++) { | |
76 if (header[i] != 0) { | |
77 break; | |
78 } | |
79 } | |
80 if (i == 8) { | |
81 if (header[2]) { | |
82 fprintf(stderr, "%s is a split SMD ROM which is not currently supported", filename); | |
83 exit(1); | |
84 } | |
85 return load_smd_rom(filesize, f); | |
86 } | |
87 } | |
88 fread(cart, 2, filesize/2, f); | |
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89 fclose(f); |
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90 for(unsigned short * cur = cart; cur - cart < (filesize/2); ++cur) |
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91 { |
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92 *cur = (*cur >> 8) | (*cur << 8); |
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93 } |
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94 //TODO: Mirror ROM |
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95 return 1; |
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96 } |
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97 |
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98 uint16_t read_dma_value(uint32_t address) |
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99 { |
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100 //addresses here are word addresses (i.e. bit 0 corresponds to A1), so no need to do div by 2 |
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101 if (address < 0x200000) { |
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102 return cart[address]; |
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103 } else if(address >= 0x700000) { |
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104 return ram[address & 0x7FFF]; |
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105 } |
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106 //TODO: Figure out what happens when you try to DMA from weird adresses like IO or banked Z80 area |
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107 return 0; |
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108 } |
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109 |
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110 #define VINT_CYCLE ((MCLKS_LINE * 226)/MCLKS_PER_68K) |
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111 #define ZVINT_CYCLE ((MCLKS_LINE * 226)/MCLKS_PER_Z80) |
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112 |
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113 void adjust_int_cycle(m68k_context * context, vdp_context * v_context) |
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114 { |
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115 if (!(v_context->regs[REG_MODE_2] & 0x20 && ((context->status & 0x7) < 6)) || context->current_cycle >= VINT_CYCLE) { |
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116 context->int_cycle = CYCLE_NEVER; |
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117 context->target_cycle = context->sync_cycle; |
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118 } else if (context->int_cycle > VINT_CYCLE) { |
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119 context->int_cycle = VINT_CYCLE; |
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120 context->int_num = 6; |
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121 if (context->int_cycle < context->sync_cycle) { |
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122 context->target_cycle = context->int_cycle; |
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123 } |
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124 } |
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125 } |
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126 |
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127 int break_on_sync = 0; |
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128 #define Z80_ACK_DELAY 3 //TODO: Calculate this on the fly based on how synced up the Z80 and 68K clocks are |
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129 |
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130 uint8_t reset = 1; |
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131 uint8_t need_reset = 0; |
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132 uint8_t busreq = 0; |
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133 uint8_t busack = 0; |
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134 uint32_t busack_cycle = CYCLE_NEVER; |
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135 uint8_t new_busack = 0; |
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136 |
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137 #ifdef DO_DEBUG_PRINT |
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138 #define dprintf printf |
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139 #else |
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140 #define dprintf |
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141 #endif |
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142 |
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143 void sync_z80(z80_context * z_context, uint32_t mclks) |
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144 { |
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145 if (z80_enabled && !reset && !busreq) { |
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146 if (need_reset) { |
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147 z80_reset(z_context); |
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148 need_reset = 0; |
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149 } |
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150 z_context->sync_cycle = mclks / MCLKS_PER_Z80; |
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151 while (z_context->current_cycle < z_context->sync_cycle) { |
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152 if (z_context->iff1 && z_context->current_cycle < ZVINT_CYCLE) { |
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153 z_context->int_cycle = ZVINT_CYCLE; |
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154 } |
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155 z_context->target_cycle = z_context->sync_cycle < z_context->int_cycle ? z_context->sync_cycle : z_context->int_cycle; |
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156 dprintf("Running Z80 from cycle %d to cycle %d. Native PC: %p\n", z_context->current_cycle, z_context->sync_cycle, z_context->native_pc); |
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157 z80_run(z_context); |
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158 dprintf("Z80 ran to cycle %d\n", z_context->current_cycle); |
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159 } |
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160 } |
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161 } |
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162 |
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163 m68k_context * sync_components(m68k_context * context, uint32_t address) |
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164 { |
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165 //TODO: Handle sync targets smaller than a single frame |
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166 vdp_context * v_context = context->video_context; |
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167 z80_context * z_context = context->next_cpu; |
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168 uint32_t mclks = context->current_cycle * MCLKS_PER_68K; |
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169 sync_z80(z_context, mclks); |
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170 if (mclks >= MCLKS_PER_FRAME) { |
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171 //printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, mclks); |
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172 vdp_run_context(v_context, MCLKS_PER_FRAME); |
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173 if (!headless) { |
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174 break_on_sync |= wait_render_frame(v_context); |
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175 } |
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176 mclks -= MCLKS_PER_FRAME; |
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177 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME); |
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178 io_adjust_cycles(&gamepad_1, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K); |
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179 io_adjust_cycles(&gamepad_2, context->current_cycle, MCLKS_PER_FRAME/MCLKS_PER_68K); |
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180 context->current_cycle -= MCLKS_PER_FRAME/MCLKS_PER_68K; |
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181 if (z_context->current_cycle >= MCLKS_PER_FRAME/MCLKS_PER_Z80) { |
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182 z_context->current_cycle -= MCLKS_PER_FRAME/MCLKS_PER_Z80; |
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183 } else { |
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184 z_context->current_cycle = 0; |
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185 } |
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186 if (mclks) { |
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187 vdp_run_context(v_context, mclks); |
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188 } |
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189 } else { |
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190 //printf("running VDP for %d cycles\n", mclks - v_context->cycles); |
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191 vdp_run_context(v_context, mclks); |
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192 } |
186
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193 adjust_int_cycle(context, v_context); |
198
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194 if (break_on_sync && address) { |
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195 break_on_sync = 0; |
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196 debugger(context, address); |
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197 } |
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198 return context; |
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199 } |
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200 |
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201 m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_t value) |
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202 { |
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203 //printf("vdp_port write: %X, value: %X, cycle: %d\n", vdp_port, value, context->current_cycle); |
198
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204 sync_components(context, 0); |
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205 vdp_context * v_context = context->video_context; |
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206 if (vdp_port < 0x10) { |
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207 int blocked; |
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208 if (vdp_port < 4) { |
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209 while (vdp_data_port_write(v_context, value) < 0) { |
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210 while(v_context->flags & FLAG_DMA_RUN) { |
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211 vdp_run_dma_done(v_context, MCLKS_PER_FRAME); |
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212 if (v_context->cycles >= MCLKS_PER_FRAME) { |
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213 if (!headless) { |
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214 wait_render_frame(v_context); |
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215 } |
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216 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME); |
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217 io_adjust_cycles(&gamepad_1, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K); |
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218 io_adjust_cycles(&gamepad_2, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K); |
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219 } |
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220 } |
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221 context->current_cycle = v_context->cycles / MCLKS_PER_68K; |
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222 } |
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223 } else if(vdp_port < 8) { |
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224 blocked = vdp_control_port_write(v_context, value); |
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225 if (blocked) { |
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226 while (blocked) { |
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227 while(v_context->flags & FLAG_DMA_RUN) { |
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228 vdp_run_dma_done(v_context, MCLKS_PER_FRAME); |
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229 if (v_context->cycles >= MCLKS_PER_FRAME) { |
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230 if (!headless) { |
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231 wait_render_frame(v_context); |
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232 } |
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233 vdp_adjust_cycles(v_context, MCLKS_PER_FRAME); |
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234 io_adjust_cycles(&gamepad_1, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K); |
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235 io_adjust_cycles(&gamepad_2, v_context->cycles/MCLKS_PER_68K, MCLKS_PER_FRAME/MCLKS_PER_68K); |
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236 } |
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237 } |
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238 if (blocked < 0) { |
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239 blocked = vdp_control_port_write(v_context, value); |
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240 } else { |
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241 blocked = 0; |
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242 } |
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243 } |
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244 context->current_cycle = v_context->cycles / MCLKS_PER_68K; |
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245 } else { |
186
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246 adjust_int_cycle(context, v_context); |
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247 } |
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248 } else { |
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249 printf("Illegal write to HV Counter port %X\n", vdp_port); |
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250 exit(1); |
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251 } |
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252 context->current_cycle = v_context->cycles/MCLKS_PER_68K; |
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253 } else if (vdp_port < 0x18) { |
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254 //TODO: Implement PSG |
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255 } else { |
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256 //TODO: Implement undocumented test register(s) |
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257 } |
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258 return context; |
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259 } |
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260 |
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261 m68k_context * vdp_port_read(uint32_t vdp_port, m68k_context * context) |
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262 { |
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263 sync_components(context, 0); |
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264 vdp_context * v_context = context->video_context; |
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265 if (vdp_port < 0x10) { |
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266 if (vdp_port < 4) { |
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267 context->value = vdp_data_port_read(v_context); |
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268 } else if(vdp_port < 8) { |
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269 context->value = vdp_control_port_read(v_context); |
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270 } else { |
137 | 271 context->value = vdp_hv_counter_read(v_context); |
272 //printf("HV Counter: %X at cycle %d\n", context->value, v_context->cycles); | |
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273 } |
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274 context->current_cycle = v_context->cycles/MCLKS_PER_68K; |
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275 } else { |
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276 printf("Illegal read from PSG or test register port %X\n", vdp_port); |
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277 exit(1); |
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278 } |
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279 return context; |
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280 } |
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281 |
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282 #define TH 0x40 |
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283 #define TH_TIMEOUT 8000 |
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284 |
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285 void io_adjust_cycles(io_port * pad, uint32_t current_cycle, uint32_t deduction) |
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286 { |
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287 /*uint8_t control = pad->control | 0x80; |
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288 uint8_t th = control & pad->output; |
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289 if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) { |
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290 printf("adjust_cycles | control: %X, TH: %X, GAMEPAD_TH0: %X, GAMEPAD_TH1: %X, TH Counter: %d, Timeout: %d, Cycle: %d\n", control, th, pad->input[GAMEPAD_TH0], pad->input[GAMEPAD_TH1], pad->th_counter,pad->timeout_cycle, current_cycle); |
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291 }*/ |
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292 if (current_cycle >= pad->timeout_cycle) { |
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293 pad->th_counter = 0; |
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294 } else { |
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295 pad->timeout_cycle -= deduction; |
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296 } |
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297 if (busack_cycle < CYCLE_NEVER && current_cycle < busack_cycle) { |
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298 busack_cycle -= deduction; |
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299 } |
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300 } |
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301 |
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302 void io_data_write(io_port * pad, m68k_context * context, uint8_t value) |
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303 { |
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304 if (pad->control & TH) { |
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305 //check if TH has changed |
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306 if ((pad->output & TH) ^ (value & TH)) { |
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307 if (context->current_cycle >= pad->timeout_cycle) { |
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308 pad->th_counter = 0; |
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309 } |
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310 if (!(value & TH)) { |
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311 pad->th_counter++; |
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312 } |
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313 pad->timeout_cycle = context->current_cycle + TH_TIMEOUT; |
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314 } |
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315 } |
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316 pad->output = value; |
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317 } |
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318 |
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319 void io_data_read(io_port * pad, m68k_context * context) |
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320 { |
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321 uint8_t control = pad->control | 0x80; |
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322 uint8_t th = control & pad->output; |
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323 uint8_t input; |
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324 if (context->current_cycle >= pad->timeout_cycle) { |
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325 pad->th_counter = 0; |
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326 } |
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327 /*if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) { |
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328 printf("io_data_read | control: %X, TH: %X, GAMEPAD_TH0: %X, GAMEPAD_TH1: %X, TH Counter: %d, Timeout: %d, Cycle: %d\n", control, th, pad->input[GAMEPAD_TH0], pad->input[GAMEPAD_TH1], pad->th_counter,pad->timeout_cycle, context->current_cycle); |
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329 }*/ |
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330 if (th) { |
195
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331 if (pad->th_counter == 3) { |
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332 input = pad->input[GAMEPAD_EXTRA]; |
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333 } else { |
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334 input = pad->input[GAMEPAD_TH1]; |
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335 } |
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336 } else { |
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337 if (pad->th_counter == 3) { |
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338 input = pad->input[GAMEPAD_TH0] | 0xF; |
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339 } else if(pad->th_counter == 4) { |
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340 input = pad->input[GAMEPAD_TH0] & 0x30; |
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341 } else { |
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342 input = pad->input[GAMEPAD_TH0] | 0xC; |
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343 } |
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344 } |
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345 context->value = ((~input) & (~control)) | (pad->output & control); |
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346 /*if (pad->input[GAMEPAD_TH0] || pad->input[GAMEPAD_TH1]) { |
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347 printf ("value: %X\n", context->value); |
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348 }*/ |
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349 } |
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350 |
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351 m68k_context * io_write(uint32_t location, m68k_context * context, uint8_t value) |
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352 { |
153
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353 if (location < 0x10000) { |
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354 if (busack_cycle > context->current_cycle) { |
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355 busack = new_busack; |
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356 busack_cycle = CYCLE_NEVER; |
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357 } |
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358 if (!(busack || reset)) { |
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359 location &= 0x7FFF; |
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360 if (location < 0x4000) { |
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361 z80_ram[location & 0x1FFF] = value; |
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362 z80_handle_code_write(location & 0x1FFF, context->next_cpu); |
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363 } |
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364 } |
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365 } else { |
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366 location &= 0x1FFF; |
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367 if (location < 0x100) { |
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368 switch(location/2) |
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369 { |
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370 case 0x1: |
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371 io_data_write(&gamepad_1, context, value); |
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372 break; |
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373 case 0x2: |
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374 io_data_write(&gamepad_2, context, value); |
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375 break; |
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376 case 0x3://PORT C Data |
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377 break; |
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378 case 0x4: |
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379 gamepad_1.control = value; |
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380 break; |
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381 case 0x5: |
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382 gamepad_2.control = value; |
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383 break; |
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384 } |
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385 } else { |
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386 if (location == 0x1100) { |
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387 sync_z80(context->next_cpu, context->current_cycle * MCLKS_PER_68K); |
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388 if (busack_cycle > context->current_cycle) { |
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389 busack = new_busack; |
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390 busack_cycle = CYCLE_NEVER; |
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391 } |
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392 if (value & 1) { |
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393 puts("bus requesting Z80"); |
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394 busreq = 1; |
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395 if(!reset) { |
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396 busack_cycle = context->current_cycle + Z80_ACK_DELAY; |
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397 new_busack = 0; |
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398 } |
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399 } else { |
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400 if (busreq) { |
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401 puts("releasing z80 bus"); |
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402 z80_context * z_context = context->next_cpu; |
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403 //TODO: Add necessary delay between release of busreq and resumption of execution |
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404 z_context->current_cycle = (context->current_cycle * MCLKS_PER_68K) / MCLKS_PER_Z80; |
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405 } |
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406 busreq = 0; |
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407 busack_cycle = CYCLE_NEVER; |
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408 busack = 1; |
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409 } |
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410 } else if (location == 0x1200) { |
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411 sync_z80(context->next_cpu, context->current_cycle * MCLKS_PER_68K); |
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412 if (value & 1) { |
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413 if (reset && busreq) { |
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414 new_busack = 0; |
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415 busack_cycle = context->current_cycle + Z80_ACK_DELAY; |
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416 } |
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417 //TODO: Deal with the scenario in which reset is not asserted long enough |
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418 if (reset) { |
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419 z80_context * z_context = context->next_cpu; |
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420 need_reset = 1; |
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421 //TODO: Add necessary delay between release of reset and start of execution |
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422 z_context->current_cycle = (context->current_cycle * MCLKS_PER_68K) / MCLKS_PER_Z80; |
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423 } |
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424 reset = 0; |
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425 } else { |
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426 reset = 1; |
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427 } |
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428 } |
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429 } |
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430 } |
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431 return context; |
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432 } |
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433 |
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434 m68k_context * io_write_w(uint32_t location, m68k_context * context, uint16_t value) |
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435 { |
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436 if (location < 0x10000) { |
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437 if (busack_cycle > context->current_cycle) { |
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438 busack = new_busack; |
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439 busack_cycle = CYCLE_NEVER; |
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440 } |
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441 if (!(busack || reset)) { |
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442 location &= 0x7FFF; |
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443 if (location < 0x4000) { |
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444 z80_ram[location & 0x1FFE] = value >> 8; |
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445 z80_handle_code_write(location & 0x1FFE, context->next_cpu); |
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446 } |
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447 } |
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448 } else { |
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449 location &= 0x1FFF; |
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450 if (location < 0x100) { |
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451 switch(location/2) |
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452 { |
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453 case 0x1: |
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454 io_data_write(&gamepad_1, context, value); |
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455 break; |
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456 case 0x2: |
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457 io_data_write(&gamepad_2, context, value); |
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458 break; |
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459 case 0x3://PORT C Data |
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460 break; |
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461 case 0x4: |
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462 gamepad_1.control = value; |
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463 break; |
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464 case 0x5: |
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465 gamepad_2.control = value; |
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466 break; |
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467 } |
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468 } else { |
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469 //printf("IO Write of %X to %X @ %d\n", value, location, context->current_cycle); |
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470 if (location == 0x1100) { |
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471 sync_z80(context->next_cpu, context->current_cycle * MCLKS_PER_68K); |
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472 if (busack_cycle > context->current_cycle) { |
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473 busack = new_busack; |
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474 busack_cycle = CYCLE_NEVER; |
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475 } |
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476 if (value & 0x100) { |
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477 printf("bus requesting Z80 @ %d\n", (context->current_cycle * MCLKS_PER_68K) / MCLKS_PER_Z80); |
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478 busreq = 1; |
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479 if(!reset) { |
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480 busack_cycle = context->current_cycle + Z80_ACK_DELAY; |
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481 new_busack = 0; |
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482 } |
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483 } else { |
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484 if (busreq) { |
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485 printf("releasing Z80 bus @ %d\n", (context->current_cycle * MCLKS_PER_68K) / MCLKS_PER_Z80); |
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486 z80_context * z_context = context->next_cpu; |
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487 //TODO: Add necessary delay between release of busreq and resumption of execution |
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488 z_context->current_cycle = (context->current_cycle * MCLKS_PER_68K) / MCLKS_PER_Z80; |
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489 } |
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490 busreq = 0; |
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491 busack_cycle = CYCLE_NEVER; |
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492 busack = 1; |
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493 } |
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494 } else if (location == 0x1200) { |
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495 sync_z80(context->next_cpu, context->current_cycle * MCLKS_PER_68K); |
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496 if (value & 0x100) { |
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497 if (reset && busreq) { |
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498 new_busack = 0; |
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499 busack_cycle = context->current_cycle + Z80_ACK_DELAY; |
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500 } |
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501 //TODO: Deal with the scenario in which reset is not asserted long enough |
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502 if (reset) { |
263
2989ed7b8608
Add a second context pointer to m68k_context so that try_fifo_write can still have easy access to the VDP. Handle writes to Z80 code addresses from the 68K.
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260
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503 z80_context * z_context = context->next_cpu; |
260
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504 need_reset = 1; |
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505 //TODO: Add necessary delay between release of reset and start of execution |
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506 z_context->current_cycle = (context->current_cycle * MCLKS_PER_68K) / MCLKS_PER_Z80; |
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507 } |
153
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508 reset = 0; |
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|
509 } else { |
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|
510 reset = 1; |
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|
511 } |
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|
512 } |
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|
513 } |
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diff
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|
514 } |
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|
515 return context; |
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parents:
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|
516 } |
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|
517 |
130
0bdbffa9fe90
Make version register return correct value for USA
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diff
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|
518 #define USA 0x80 |
0bdbffa9fe90
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diff
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519 #define JAP 0x00 |
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diff
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|
520 #define EUR 0xC0 |
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diff
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521 #define NO_DISK 0x20 |
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522 uint8_t version_reg = NO_DISK | USA; |
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|
523 |
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diff
changeset
|
524 m68k_context * io_read(uint32_t location, m68k_context * context) |
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diff
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|
525 { |
153
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diff
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|
526 if (location < 0x10000) { |
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527 if (busack_cycle > context->current_cycle) { |
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149
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528 busack = new_busack; |
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|
529 busack_cycle = CYCLE_NEVER; |
42c031184e8a
Implement access to Z80 RAM
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diff
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|
530 } |
42c031184e8a
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|
531 if (!(busack || reset)) { |
42c031184e8a
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|
532 location &= 0x7FFF; |
42c031184e8a
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|
533 if (location < 0x4000) { |
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534 context->value = z80_ram[location & 0x1FFF]; |
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diff
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|
535 } else { |
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diff
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|
536 context->value = 0xFF; |
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diff
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|
537 } |
42c031184e8a
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|
538 } else { |
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|
539 context->value = 0xFF; |
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diff
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|
540 } |
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|
541 } else { |
153
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diff
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|
542 location &= 0x1FFF; |
42c031184e8a
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diff
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|
543 if (location < 0x100) { |
42c031184e8a
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|
544 switch(location/2) |
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|
545 { |
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|
546 case 0x0: |
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|
547 //version bits should be 0 for now since we're not emulating TMSS |
42c031184e8a
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149
diff
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|
548 //Not sure about the other bits |
42c031184e8a
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149
diff
changeset
|
549 context->value = version_reg; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
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149
diff
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|
550 break; |
42c031184e8a
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149
diff
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|
551 case 0x1: |
42c031184e8a
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149
diff
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|
552 io_data_read(&gamepad_1, context); |
42c031184e8a
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parents:
149
diff
changeset
|
553 break; |
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parents:
149
diff
changeset
|
554 case 0x2: |
42c031184e8a
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149
diff
changeset
|
555 io_data_read(&gamepad_2, context); |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
556 break; |
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parents:
149
diff
changeset
|
557 case 0x3://PORT C Data |
42c031184e8a
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
558 break; |
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
559 case 0x4: |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
560 context->value = gamepad_1.control; |
42c031184e8a
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
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|
561 break; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
562 case 0x5: |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
563 context->value = gamepad_2.control; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
564 break; |
88
c339559f1d4f
Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
565 } |
c339559f1d4f
Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
566 } else { |
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
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|
567 if (location == 0x1100) { |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
568 if (busack_cycle > context->current_cycle) { |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
569 busack = new_busack; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
570 busack_cycle = CYCLE_NEVER; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
571 } |
42c031184e8a
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parents:
149
diff
changeset
|
572 context->value = reset || busack; |
42c031184e8a
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parents:
149
diff
changeset
|
573 //printf("Byte read of BUSREQ returned %d @ %d (reset: %d, busack: %d)\n", context->value, context->current_cycle, reset, busack); |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
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149
diff
changeset
|
574 } else if (location == 0x1200) { |
42c031184e8a
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parents:
149
diff
changeset
|
575 context->value = !reset; |
42c031184e8a
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
576 } else { |
42c031184e8a
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
577 printf("Byte read of unknown IO location: %X\n", location); |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
578 } |
88
c339559f1d4f
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
579 } |
c339559f1d4f
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
580 } |
c339559f1d4f
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
581 return context; |
c339559f1d4f
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
582 } |
c339559f1d4f
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
583 |
c339559f1d4f
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
584 m68k_context * io_read_w(uint32_t location, m68k_context * context) |
c339559f1d4f
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
585 { |
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
586 if (location < 0x10000) { |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
587 if (busack_cycle > context->current_cycle) { |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
588 busack = new_busack; |
42c031184e8a
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parents:
149
diff
changeset
|
589 busack_cycle = CYCLE_NEVER; |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
590 } |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
591 if (!(busack || reset)) { |
42c031184e8a
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
592 location &= 0x7FFF; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
593 if (location < 0x4000) { |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
594 context->value = z80_ram[location & 0x1FFE]; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
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149
diff
changeset
|
595 context->value |= context->value << 8; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
596 } else { |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
597 context->value = 0xFFFF; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
598 } |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
599 } else { |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
600 context->value = 0xFFFF; |
88
c339559f1d4f
Forgot to add blastem main file earlier
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parents:
diff
changeset
|
601 } |
c339559f1d4f
Forgot to add blastem main file earlier
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
602 } else { |
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
603 location &= 0x1FFF; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
604 if (location < 0x100) { |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
605 switch(location/2) |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
606 { |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
607 case 0x0: |
42c031184e8a
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parents:
149
diff
changeset
|
608 //version bits should be 0 for now since we're not emulating TMSS |
42c031184e8a
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
609 //Not sure about the other bits |
42c031184e8a
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
610 context->value = 0; |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
611 break; |
42c031184e8a
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Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
612 case 0x1: |
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parents:
149
diff
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|
613 io_data_read(&gamepad_1, context); |
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parents:
149
diff
changeset
|
614 break; |
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Mike Pavone <pavone@retrodev.com>
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149
diff
changeset
|
615 case 0x2: |
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parents:
149
diff
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|
616 io_data_read(&gamepad_2, context); |
42c031184e8a
Implement access to Z80 RAM
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149
diff
changeset
|
617 break; |
42c031184e8a
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parents:
149
diff
changeset
|
618 case 0x3://PORT C Data |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
619 break; |
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
620 case 0x4: |
42c031184e8a
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149
diff
changeset
|
621 context->value = gamepad_1.control; |
42c031184e8a
Implement access to Z80 RAM
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149
diff
changeset
|
622 break; |
42c031184e8a
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149
diff
changeset
|
623 case 0x5: |
42c031184e8a
Implement access to Z80 RAM
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149
diff
changeset
|
624 context->value = gamepad_2.control; |
42c031184e8a
Implement access to Z80 RAM
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parents:
149
diff
changeset
|
625 break; |
42c031184e8a
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parents:
149
diff
changeset
|
626 case 0x6: |
42c031184e8a
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parents:
149
diff
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|
627 //PORT C Control |
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628 context->value = 0; |
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629 break; |
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630 } |
153
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631 context->value = context->value | (context->value << 8); |
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632 //printf("Word read to %X returned %d\n", location, context->value); |
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633 } else { |
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634 if (location == 0x1100) { |
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635 if (busack_cycle > context->current_cycle) { |
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636 busack = new_busack; |
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637 busack_cycle = CYCLE_NEVER; |
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638 } |
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639 context->value = (reset || busack) << 8; |
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640 //printf("Word read of BUSREQ returned %d\n", context->value); |
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641 } else if (location == 0x1200) { |
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642 context->value = (!reset) << 8; |
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643 } else { |
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644 printf("Word read of unknown IO location: %X\n", location); |
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645 } |
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646 } |
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647 } |
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648 return context; |
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649 } |
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650 |
184
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651 typedef struct bp_def { |
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652 struct bp_def * next; |
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653 uint32_t address; |
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654 uint32_t index; |
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655 } bp_def; |
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656 |
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657 bp_def * breakpoints = NULL; |
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658 uint32_t bp_index = 0; |
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659 |
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660 bp_def ** find_breakpoint(bp_def ** cur, uint32_t address) |
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661 { |
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662 while (*cur) { |
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663 if ((*cur)->address == address) { |
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664 break; |
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665 } |
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666 cur = &((*cur)->next); |
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667 } |
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668 return cur; |
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669 } |
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670 |
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671 bp_def ** find_breakpoint_idx(bp_def ** cur, uint32_t index) |
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672 { |
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673 while (*cur) { |
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674 if ((*cur)->index == index) { |
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675 break; |
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676 } |
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677 cur = &((*cur)->next); |
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678 } |
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679 return cur; |
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680 } |
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681 |
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682 char * find_param(char * buf) |
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683 { |
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684 for (; *buf; buf++) { |
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685 if (*buf == ' ') { |
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686 if (*(buf+1)) { |
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687 return buf+1; |
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688 } |
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689 } |
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690 } |
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691 return NULL; |
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692 } |
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693 |
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694 void strip_nl(char * buf) |
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695 { |
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696 for(; *buf; buf++) { |
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697 if (*buf == '\n') { |
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698 *buf = 0; |
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699 return; |
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700 } |
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701 } |
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702 } |
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703 |
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704 m68k_context * debugger(m68k_context * context, uint32_t address) |
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705 { |
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706 static char last_cmd[1024]; |
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707 char input_buf[1024]; |
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708 static uint32_t branch_t; |
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709 static uint32_t branch_f; |
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710 m68kinst inst; |
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711 //probably not necessary, but let's play it safe |
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712 address &= 0xFFFFFF; |
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713 if (address == branch_t) { |
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714 bp_def ** f_bp = find_breakpoint(&breakpoints, branch_f); |
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715 if (!*f_bp) { |
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716 remove_breakpoint(context, branch_f); |
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717 } |
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718 branch_t = branch_f = 0; |
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719 } else if(address == branch_f) { |
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720 bp_def ** t_bp = find_breakpoint(&breakpoints, branch_t); |
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721 if (!*t_bp) { |
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722 remove_breakpoint(context, branch_t); |
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723 } |
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724 branch_t = branch_f = 0; |
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725 } |
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726 //Check if this is a user set breakpoint, or just a temporary one |
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727 bp_def ** this_bp = find_breakpoint(&breakpoints, address); |
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728 if (*this_bp) { |
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729 printf("Breakpoint %d hit\n", (*this_bp)->index); |
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730 } else { |
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731 remove_breakpoint(context, address); |
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732 } |
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733 uint16_t * pc; |
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734 if (address < 0x400000) { |
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735 pc = cart + address/2; |
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736 } else if(address > 0xE00000) { |
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737 pc = ram + (address & 0xFFFF)/2; |
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738 } else { |
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739 fprintf(stderr, "Entered debugger at address %X\n", address); |
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740 exit(1); |
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741 } |
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742 uint16_t * after_pc = m68k_decode(pc, &inst, address); |
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743 m68k_disasm(&inst, input_buf); |
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744 printf("%X: %s\n", address, input_buf); |
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745 uint32_t after = address + (after_pc-pc)*2; |
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746 int debugging = 1; |
ebcbdd1c4cc8
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747 while (debugging) { |
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748 fputs(">", stdout); |
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|
749 if (!fgets(input_buf, sizeof(input_buf), stdin)) { |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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750 fputs("fgets failed", stderr); |
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751 break; |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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752 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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|
753 strip_nl(input_buf); |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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754 //hitting enter repeats last command |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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|
755 if (input_buf[0]) { |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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756 strcpy(last_cmd, input_buf); |
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757 } else { |
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758 strcpy(input_buf, last_cmd); |
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759 } |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
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760 char * param; |
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761 char format[8]; |
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762 uint32_t value; |
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763 bp_def * new_bp; |
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764 switch(input_buf[0]) |
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765 { |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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766 case 'c': |
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767 puts("Continuing"); |
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768 debugging = 0; |
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769 break; |
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770 case 'b': |
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771 param = find_param(input_buf); |
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772 if (!param) { |
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773 fputs("b command requires a parameter\n", stderr); |
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774 break; |
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775 } |
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|
776 value = strtol(param, NULL, 16); |
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777 insert_breakpoint(context, value, (uint8_t *)debugger); |
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778 new_bp = malloc(sizeof(bp_def)); |
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779 new_bp->next = breakpoints; |
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780 new_bp->address = value; |
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781 new_bp->index = bp_index++; |
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782 breakpoints = new_bp; |
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783 printf("Breakpoint %d set at %X\n", new_bp->index, value); |
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784 break; |
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785 case 'a': |
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786 param = find_param(input_buf); |
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787 if (!param) { |
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|
788 fputs("a command requires a parameter\n", stderr); |
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789 break; |
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790 } |
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791 value = strtol(param, NULL, 16); |
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792 insert_breakpoint(context, value, (uint8_t *)debugger); |
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793 debugging = 0; |
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794 break; |
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Mike Pavone <pavone@retrodev.com>
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166
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795 case 'd': |
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796 param = find_param(input_buf); |
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797 if (!param) { |
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798 fputs("b command requires a parameter\n", stderr); |
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799 break; |
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800 } |
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801 value = atoi(param); |
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|
802 this_bp = find_breakpoint_idx(&breakpoints, value); |
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|
803 if (!*this_bp) { |
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|
804 fprintf(stderr, "Breakpoint %d does not exist\n", value); |
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805 break; |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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806 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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|
807 new_bp = *this_bp; |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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|
808 *this_bp = (*this_bp)->next; |
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809 free(new_bp); |
ebcbdd1c4cc8
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|
810 break; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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811 case 'p': |
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|
812 strcpy(format, "%s: %d\n"); |
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|
813 if (input_buf[1] == '/') { |
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Mike Pavone <pavone@retrodev.com>
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814 switch (input_buf[2]) |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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|
815 { |
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816 case 'x': |
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|
817 case 'X': |
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|
818 case 'd': |
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819 case 'c': |
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|
820 format[5] = input_buf[2]; |
ebcbdd1c4cc8
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|
821 break; |
ebcbdd1c4cc8
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|
822 default: |
ebcbdd1c4cc8
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|
823 fprintf(stderr, "Unrecognized format character: %c\n", input_buf[2]); |
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824 } |
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|
825 } |
ebcbdd1c4cc8
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|
826 param = find_param(input_buf); |
ebcbdd1c4cc8
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|
827 if (!param) { |
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changeset
|
828 fputs("p command requires a parameter\n", stderr); |
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|
829 break; |
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|
830 } |
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|
831 if (param[0] == 'd' && param[1] >= '0' && param[1] <= '7') { |
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|
832 value = context->dregs[param[1]-'0']; |
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|
833 } else if (param[0] == 'a' && param[1] >= '0' && param[1] <= '7') { |
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|
834 value = context->aregs[param[1]-'0']; |
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835 } else if (param[0] == 'S' && param[1] == 'R') { |
ebcbdd1c4cc8
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|
836 value = (context->status << 8); |
ebcbdd1c4cc8
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|
837 for (int flag = 0; flag < 5; flag++) { |
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|
838 value |= context->flags[flag] << (4-flag); |
ebcbdd1c4cc8
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166
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|
839 } |
185
b204fbed4efe
Add ability to print out current 68K cycle in debugger
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parents:
184
diff
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|
840 } else if(param[0] == 'c') { |
b204fbed4efe
Add ability to print out current 68K cycle in debugger
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184
diff
changeset
|
841 value = context->current_cycle; |
184
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166
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|
842 } else if (param[0] == '0' && param[1] == 'x') { |
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|
843 uint32_t p_addr = strtol(param+2, NULL, 16); |
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Fix a bunch of bugs in the CPU core, add a 68K debugger
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166
diff
changeset
|
844 value = read_dma_value(p_addr/2); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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166
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|
845 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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166
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changeset
|
846 fprintf(stderr, "Unrecognized parameter to p: %s\n", param); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
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166
diff
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|
847 break; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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166
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|
848 } |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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166
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changeset
|
849 printf(format, param, value); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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166
diff
changeset
|
850 break; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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changeset
|
851 case 'n': |
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166
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|
852 //TODO: Deal with jmp, dbcc, rtr and rte |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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166
diff
changeset
|
853 if (inst.op == M68K_RTS) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
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166
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|
854 after = (read_dma_value(context->aregs[7]/2) << 16) | read_dma_value(context->aregs[7]/2 + 1); |
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855 } else if(inst.op == M68K_BCC && inst.extra.cond != COND_FALSE) { |
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856 if (inst.extra.cond = COND_TRUE) { |
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857 after = inst.address + 2 + inst.src.params.immed; |
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858 } else { |
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859 branch_f = after; |
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860 branch_t = inst.address + 2 + inst.src.params.immed; |
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861 insert_breakpoint(context, branch_t, (uint8_t *)debugger); |
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862 } |
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863 } |
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864 insert_breakpoint(context, after, (uint8_t *)debugger); |
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865 debugging = 0; |
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866 break; |
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867 case 'q': |
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868 puts("Quitting"); |
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869 exit(0); |
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870 break; |
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871 default: |
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872 fprintf(stderr, "Unrecognized debugger command %s\n", input_buf); |
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873 break; |
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874 } |
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875 } |
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876 return context; |
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877 } |
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878 |
263
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879 void init_run_cpu(vdp_context * vcontext, z80_context * zcontext, int debug, FILE * address_log) |
211 | 880 { |
881 m68k_context context; | |
882 x86_68k_options opts; | |
883 init_x86_68k_opts(&opts); | |
884 opts.address_log = address_log; | |
885 init_68k_context(&context, opts.native_code_map, &opts); | |
886 | |
263
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887 context.video_context = vcontext; |
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888 context.next_cpu = zcontext; |
211 | 889 //cartridge ROM |
890 context.mem_pointers[0] = cart; | |
891 context.target_cycle = context.sync_cycle = MCLKS_PER_FRAME/MCLKS_PER_68K; | |
892 //work RAM | |
893 context.mem_pointers[1] = ram; | |
894 uint32_t address; | |
895 /*address = cart[0x68/2] << 16 | cart[0x6A/2]; | |
896 translate_m68k_stream(address, &context); | |
897 address = cart[0x70/2] << 16 | cart[0x72/2]; | |
898 translate_m68k_stream(address, &context); | |
899 address = cart[0x78/2] << 16 | cart[0x7A/2]; | |
900 translate_m68k_stream(address, &context);*/ | |
901 address = cart[2] << 16 | cart[3]; | |
902 translate_m68k_stream(address, &context); | |
903 if (debug) { | |
904 insert_breakpoint(&context, address, (uint8_t *)debugger); | |
905 } | |
906 m68k_reset(&context); | |
907 } | |
908 | |
88
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909 int main(int argc, char ** argv) |
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910 { |
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911 if (argc < 2) { |
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912 fputs("Usage: blastem FILENAME\n", stderr); |
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913 return 1; |
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914 } |
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915 if(!load_rom(argv[1])) { |
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916 fprintf(stderr, "Failed to open %s for reading\n", argv[1]); |
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917 return 1; |
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918 } |
184
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919 int width = -1; |
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920 int height = -1; |
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921 int debug = 0; |
197
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922 FILE *address_log = NULL; |
184
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923 for (int i = 2; i < argc; i++) { |
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924 if (argv[i][0] == '-') { |
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925 switch(argv[i][1]) { |
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926 case 'd': |
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927 debug = 1; |
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928 break; |
197
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929 case 'l': |
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930 address_log = fopen("address.log", "w"); |
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931 break; |
215
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|
932 case 'v': |
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933 headless = 1; |
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|
934 break; |
265
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264
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|
935 case 'n': |
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936 z80_enabled = 0; |
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|
937 break; |
184
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938 default: |
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939 fprintf(stderr, "Unrecognized switch %s\n", argv[i]); |
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940 return 1; |
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941 } |
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942 } else if (width < 0) { |
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943 width = atoi(argv[i]); |
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944 } else if (height < 0) { |
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|
945 height = atoi(argv[i]); |
88
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|
946 } |
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947 } |
184
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|
948 width = width < 320 ? 320 : width; |
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|
949 height = height < 240 ? (width/320) * 240 : height; |
215
2b1c2c28b261
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211
diff
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|
950 if (!headless) { |
2b1c2c28b261
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211
diff
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|
951 render_init(width, height); |
2b1c2c28b261
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211
diff
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|
952 } |
88
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|
953 vdp_context v_context; |
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changeset
|
954 |
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changeset
|
955 init_vdp_context(&v_context); |
260
625f8e4d5fd2
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215
diff
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|
956 |
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|
957 z80_context z_context; |
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|
958 x86_z80_options z_opts; |
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|
959 init_x86_z80_opts(&z_opts); |
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215
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|
960 init_z80_context(&z_context, &z_opts); |
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|
961 z_context.next_context = &v_context; |
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|
962 z_context.mem_pointers[0] = z80_ram; |
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|
963 z_context.sync_cycle = z_context.target_cycle = MCLKS_PER_FRAME/MCLKS_PER_Z80; |
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|
964 z_context.int_cycle = CYCLE_NEVER; |
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215
diff
changeset
|
965 z_context.mem_pointers[1] = z_context.mem_pointers[2] = (uint8_t *)cart; |
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Initial stab at integartiong Z80 core
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|
966 |
263
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260
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|
967 init_run_cpu(&v_context, &z_context, debug, address_log); |
88
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changeset
|
968 return 0; |
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|
969 } |