repos/blastem: gentests.py annotate

annotate gentests.py @ 445:80a9527c812c

Add config values for audio sample rate and buffer size

author	Mike Pavone <pavone@retrodev.com>
date	Thu, 18 Jul 2013 09:59:39 -0700
parents	bfbb8613efb4
children	097c172839d4

rev	line source
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #!/usr/bin/env python
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	2
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 def split_fields(line):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	4 parts = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	5 while line:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 field,_,line = line.partition('\t')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 parts.append(field.strip())
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 while line.startswith('\t'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 line = line[1:]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 return parts
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	11
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 class Program(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 def __init__(self, instruction):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 self.avail_dregs = {0,1,2,3,4,5,6,7}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 self.avail_aregs = {0,1,2,3,4,5,6,7}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 instruction.consume_regs(self)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 self.inst = instruction
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	18
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	19 def dirname(self):
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	20 return self.inst.name + '_' + self.inst.size
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 def name(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	23
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 def write_rom_test(self, outfile):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 outfile.write('\tdc.l $0, start\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	26 needdivzero = self.inst.name.startswith('div')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	27 needchk = self.inst.name.startswith('chk')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 for i in xrange(0x8, 0x100, 0x4):
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	29 if needdivzero and i == 0x14:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	30 outfile.write('\tdc.l div_zero_handler\n')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	31 elif needchk and i == 0x18:
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	32 outfile.write('\tdc.l chk_handler\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	33 else:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	34 outfile.write('\tdc.l empty_handler\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	35 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	36 if needdivzero:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	37 outfile.write('div_zero_handler:\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	38 div_zero_count = self.get_dreg()
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	39 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	40 outfile.write('\trte\n')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	41 if needchk:
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	42 outfile.write('chk_handler:\n')
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	43 chk_count = self.get_dreg()
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	44 outfile.write('\taddq #1, ' + str(chk_count) + '\n')
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	45 outfile.write('\trte\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	46 outfile.write('start:\n\tmove #0, CCR\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	47 if needdivzero:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	48 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 already = {}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 self.inst.write_init(outfile, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 if 'label' in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 outfile.write('lbl_' + str(already['label']) + ':\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 outfile.write('\t'+str(self.inst)+'\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 save_ccr = self.get_dreg()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	57 outfile.write('\tmove #$1F, CCR\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	58 self.inst.invalidate_dest(already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	59 self.inst.write_init(outfile, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 if 'label' in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 outfile.write('lbl_' + str(already['label']) + ':\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 outfile.write('\t'+str(self.inst)+'\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 outfile.write('\treset\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	65
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 def consume_dreg(self, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 self.avail_dregs.discard(num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	68
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 def consume_areg(self, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 self.avail_aregs.discard(num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	71
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 def get_dreg(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 return Register('d', self.avail_dregs.pop())
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	74
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	75 class Dummy(object):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	76 def __str__(self):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	77 return ''
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	78 def write_init(self, outfile, size, already):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	79 pass
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	80 def consume_regs(self, program):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	81 pass
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	82
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	83 dummy_op = Dummy()
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	84
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 class Register(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 def __init__(self, kind, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 self.kind = kind
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 self.num = num
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	89
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 if self.kind == 'd' or self.kind == 'a':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 return self.kind + str(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	93 return self.kind
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	94
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 if not str(self) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 val = randint(minv,maxv)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	99 already[str(self)] = val
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	101
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	102 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 if self.kind == 'd':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 program.consume_dreg(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 elif self.kind == 'a':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 program.consume_areg(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	107
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 def valid_ram_address(address, size='b'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	110
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 return randint(mina, maxa) \| 0xE00000
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	113
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 class Indexed(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	115 def __init__(self, base, index, index_size, disp):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	116 self.base = base
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 self.index = index
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 self.index_size = index_size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 self.disp = disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	120
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	121 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	122 if self.base.kind == 'pc':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 if str(self.index) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 index = already[str(self.index)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 if self.index_size == 'w':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 index = index & 0xFFFF
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	127 #sign extend index
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 if index & 0x8000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	129 index -= 65536
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	130 if index > -1024:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	131 index = already[str(self.index)] = randint(-32768, -1024)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	132 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	133 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	134 index = already[str(self.index)] = randint(-32768, -1024)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	135 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	136 num = already.get('label', 0)+1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 already['label'] = num
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	139 else:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	140 if self.base == self.index:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	141 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	142 if not valid_ram_address(already[str(self.base)]*2):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	143 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	144 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	145 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	146 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	147 base = index = already[str(self.base)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 else:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	149 base = index = already[str(self.base)] = random_ram_address()/2
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	150 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	151 else:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	152 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	153 if not valid_ram_address(already[str(self.base)]):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	154 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	155 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	156 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	157 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	158 base = already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	159 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	160 base = already[str(self.base)] = random_ram_address()
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	161 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	162 if str(self.index) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	163 index = already[str(self.index)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	164 if self.index_size == 'w':
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	165 index = index & 0xFFFF
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	166 #sign extend index
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	167 if index & 0x8000:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	168 index -= 65536
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	169 if not valid_ram_address(base + index):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	170 index = already[str(self.index)] = randint(-64, 63)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	171 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	172 else:
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 index = already[str(self.index)] = randint(-64, 63)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	174 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 if (address & 0xFFFFFF) < 0xE00000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 if (address & 0xFFFFFF) < 128:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 self.disp -= (address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	180 self.disp += 0xE00000-(address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 elif (address & 0xFFFFFF) > 0xFFFFFC:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	184 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	185 if size != 'b' and address & 1:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 self.disp = self.disp ^ 1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	190
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	193
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 self.base.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 self.index.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	197
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 class Displacement(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 def __init__(self, base, disp):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 self.base = base
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 self.disp = disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	202
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 if self.base.kind == 'pc':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 num = already.get('label', 0)+1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 already['label'] = num
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 if str(self.base) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 if not valid_ram_address(already[str(self.base)]):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 del already[str(self.base)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	214 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 base = already[str(self.base)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	217 base = already[str(self.base)] = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	219 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	220 if (address & 0xFFFFFF) < 0xE00000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 if (address & 0xFFFFFF) < 0x10000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	222 self.disp -= (address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 self.disp += 0xE00000-(address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 elif (address & 0xFFFFFF) > 0xFFFFFC:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	229 if size != 'b' and address & 1:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	230 self.disp = self.disp ^ 1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	234
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	235 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	237
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 self.base.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	240
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 class Indirect(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 self.reg = reg
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	244
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	246 return '(' + str(self.reg) + ')'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	247
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	250 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	252 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	255 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	264
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	265 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	267
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 class Increment(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	269 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	270 self.reg = reg
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	271
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 return '(' + str(self.reg) + ')+'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	274
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	275 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	276 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	279 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	280 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	284 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	285 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	287 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	288 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	289 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	291
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	294
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 class Decrement(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 self.reg = reg
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	298
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	299 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 return '-(' + str(self.reg) + ')'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	301
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	303 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	305 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	306 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	307 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	309 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	310 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	311 address = random_ram_address(mina=0xE00004)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	312 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	313 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	314 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	318
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	319 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	320 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	321
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	322 class Absolute(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	323 def __init__(self, address, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	324 self.address = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	325 self.size = size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	326
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	327 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	328 return '(' + str(self.address) + ').' + self.size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	329
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	330 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	331 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	332 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	333
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	334 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	335 pass
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	336
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 class Immediate(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 def __init__(self, value):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	339 self.value = value
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	340
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	341 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	342 return '#' + str(self.value)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	343
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	344 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	345 pass
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	346
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	347 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	348 pass
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	349
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	350 all_dregs = [Register('d', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	351 all_aregs = [Register('a', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 all_indirect = [Indirect(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	353 all_predec = [Decrement(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	354 all_postinc = [Increment(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	355 from random import randint
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	356 def all_indexed():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	358
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 def all_disp():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	360 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	361
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	362 def rand_pc_disp():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	364
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	365 def all_pc_indexed():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	367
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 def rand_abs_short():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	369 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	370
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 def rand_abs_long():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	373
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 def get_size_range(size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	375 if size == 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 return (-128, 127)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 elif size == 'w':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 return (-32768, 32767)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	379 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	380 return (-2147483648, 2147483647)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	381
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	382 def rand_immediate(size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	383 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	384
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	385 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	386
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	387 def get_variations(mode, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	388 mapping = {
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	389 'd':all_dregs,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	390 'a':all_aregs,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	391 '(a)':all_indirect,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	392 '-(a)':all_predec,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	393 '(a)+':all_postinc,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	394 '(n,a)':all_disp,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	395 '(n,a,x)':all_indexed,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	396 '(n,pc)':rand_pc_disp,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	397 '(n,pc,x)':all_pc_indexed,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	398 '(n).w':rand_abs_short,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	399 '(n).l':rand_abs_long
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	400 }
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	401 if mode in mapping:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	402 ret = mapping[mode]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	403 if type(ret) != list:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	404 ret = ret()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	405 return ret
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	406 elif mode == '#n':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	407 return rand_immediate(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	408 elif mode.startswith('#(') and mode.endswith(')'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	409 inner = mode[2:-1]
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	410 start,sep,end = inner.rpartition('-')
220 cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	411 start,end = int(start),int(end)
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	412 if end-start > 16:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	413 return [Immediate(randint(start, end)) for x in range(0,8)]
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	414 else:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	415 return [Immediate(num) for num in range(start, end+1)]
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	416 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	417 print "Don't know what to do with source type", mode
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	418 return None
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	419
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	420 class Inst2Op(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 def __init__(self, name, size, src, dst):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	422 self.name = name
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	423 self.size = size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	424 self.src = src
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	425 self.dst = dst
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	426
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	427 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	428 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	429
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	430 def write_init(self, outfile, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	431 self.src.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	432 self.dst.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	433
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	434 def invalidate_dest(self, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	435 if type(self.dst) == Register:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	436 del already[str(self.dst)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	437
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	438 def save_result(self, reg, always):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	439 if always or type(self.dst) != Register:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	440 if type(self.dst) == Decrement:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	441 src = Increment(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	442 elif type(self.dst) == Increment:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	443 src = Decrement(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	444 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	445 src = self.dst
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	446 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	448 return ''
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	449
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	450 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	451 self.src.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	452 self.dst.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	453
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	454 class Inst1Op(Inst2Op):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	455 def __init__(self, name, size, dst):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	456 super(Inst1Op, self).__init__(name, size, dummy_op, dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	457
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	458 def __str__(self):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	459 return self.name + '.' + self.size + ' ' + str(self.dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	460
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	461 class Entry(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	462 def __init__(self, line):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	463 fields = split_fields(line)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	464 self.name = fields[0]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	465 sizes = fields[1]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	466 sources = fields[2].split(';')
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	467 if len(fields) > 3:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	468 dests = fields[3].split(';')
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	469 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	470 dests = None
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	471 combos = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	472 for size in sizes:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	473 for source in sources:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	474 if size != 'b' or source != 'a':
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	475 if dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	476 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	477 if size != 'b' or dest != 'a':
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	478 combos.append((size, source, dest))
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	479 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	480 combos.append((size, None, source))
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	481 self.cases = combos
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	482
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	483 def programs(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	484 res = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	485 for (size, src, dst) in self.cases:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	486 dests = get_variations(dst, size)
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	487 if src:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	488 sources = get_variations(src, size)
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	489 for source in sources:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	490 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	491 res.append(Program(Inst2Op(self.name, size, source, dest)))
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	492 else:
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	493 for dest in dests:
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	494 res.append(Program(Inst1Op(self.name, size, dest)))
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	495 return res
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	496
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	497 def process_entries(f):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	498 entries = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	499 for line in f:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	500 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	501 entries.append(Entry(line))
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	502 return entries
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	503
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	504 from os import path, mkdir
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	505 def main(args):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	506 entries = process_entries(open('testcases.txt'))
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	507 for entry in entries:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	508 programs = entry.programs()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	509 for program in programs:
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	510 dname = program.dirname()
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	511 if not path.exists('generated_tests/' + dname):
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	512 mkdir('generated_tests/' + dname)
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	513 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	514 program.write_rom_test(f)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	515 f.close()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	516
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	517 if __name__ == '__main__':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	518 import sys
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	519 main(sys.argv)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	520

Mercurial > repos > blastem

annotate gentests.py @ 445:80a9527c812c