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annotate runtime.S @ 544:8a26567852b7

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Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
author Michael Pavone <pavone@retrodev.com>
date Sun, 16 Feb 2014 19:21:39 -0800
parents 915a1cb98bac
children 67cf0ce57d8d
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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17
de0085d4ea40 Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
2 .global handle_cycle_limit
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
3 .global do_sync
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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diff changeset
4 handle_cycle_limit:
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
5 cmp 84(%rsi), %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
6 jb skip_sync
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
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parents: 149
diff changeset
7 do_sync:
343
467bfa17004a Mostly working runtime generation of memory map read/write functions
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8 push %rcx
467bfa17004a Mostly working runtime generation of memory map read/write functions
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9 push %rdi
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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10 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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parents: 53
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11 mov %rsi, %rdi
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209a37eed3e7 Add support for breaking into the debugger while game is running
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12 xor %esi, %esi
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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parents: 423
diff changeset
13 test $8, %esp
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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parents: 423
diff changeset
14 jnz adjust_rsp
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
15 call sync_components
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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16 jmp done_adjust
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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parents: 423
diff changeset
17 adjust_rsp:
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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parents: 423
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18 sub $8, %rsp
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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19 call sync_components
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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20 add $8, %rsp
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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parents: 423
diff changeset
21 done_adjust:
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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parents: 53
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22 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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parents: 53
diff changeset
23 call m68k_load_context
343
467bfa17004a Mostly working runtime generation of memory map read/write functions
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24 pop %rdi
467bfa17004a Mostly working runtime generation of memory map read/write functions
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25 pop %rcx
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
26 skip_sync:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
27 ret
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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28
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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diff changeset
29 invalid_msg:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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30 .asciz "Invalid instruction at %X\n"
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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31
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e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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32 .global m68k_invalid
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33 m68k_invalid:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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34 lea invalid_msg(%rip), %rdi
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35 mov %ecx, %esi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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36 xor %rax, %rax
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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37 call printf
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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38 mov $1, %rdi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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39 call exit
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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40
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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41 .global bcd_add
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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42 bcd_add:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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43 xchg %rax, %rdi
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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44
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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45 mov %cl, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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46 mov %al, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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47 and $0xF, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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48 and $0xF, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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49 and $0xF0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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50 and $0xF0, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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51 add %ah, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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52 cmp $10, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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53 jb no_adjust
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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54 add $6, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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55 no_adjust:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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56 add %ch, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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57 add %al, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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58 mov $0, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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59 jc def_adjust
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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60 cmp $0xA0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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61 jb no_adjust_h
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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62 def_adjust:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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63 add $0x60, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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64 mov $1, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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65 no_adjust_h:
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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parents: 423
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66
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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67 mov %rdi, %rax
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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68 ret
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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69
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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70 .global bcd_sub
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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71 bcd_sub:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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72 xchg %rax, %rdi
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
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parents: 423
diff changeset
73
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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74 mov %cl, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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75 mov %al, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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76 and $0xF, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
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77 and $0xF, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
78 and $0xF0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
79 and $0xF0, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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80 sub %ah, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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81 cmp $10, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
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82 jb no_adjusts
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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83 sub $6, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
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84 no_adjusts:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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85 add %ch, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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86 sub %al, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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87 mov $0, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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88 jc def_adjusts
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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89 cmp $0xA0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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90 jb no_adjust_hs
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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91 def_adjusts:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
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92 sub $0x60, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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93 mov $1, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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parents: 193
diff changeset
94 no_adjust_hs:
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents: 423
diff changeset
95
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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96 mov %rdi, %rax
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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97 ret
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
98
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
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99 .global get_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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diff changeset
100 get_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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101 mov 5(%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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diff changeset
102 shl $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
103 mov (%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
104 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
105 or %bl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
106 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
107 or %dl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
108 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
109 or %bh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
110 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
111 or %dh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
112 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
113
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
114 .global set_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
115 set_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
116 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
117 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
118 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
119 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
120 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
121 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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parents: 72
diff changeset
122 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
123 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
124 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
125 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
126 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
127 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
128 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
129 mov %cl, (%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
130 shr $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
131 mov %cl, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
132 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
133
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
134 .global set_ccr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
135 set_ccr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
136 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
137 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
138 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
139 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
140 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
141 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
142 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
143 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
144 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
145 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
146 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
147 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
148 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
149 mov %cl, (%rsi)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
150 ret
485
b449af228c63 Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents: 423
diff changeset
151
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
152 .global m68k_save_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
153 m68k_save_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
154 mov %bl, 1(%rsi) /* N Flag */
207
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 198
diff changeset
155 mov %dl, 2(%rsi) /* Z flag */
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 198
diff changeset
156 mov %bh, 3(%rsi) /* V flag */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
157 mov %dh, 4(%rsi) /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
158 mov %r10d, 8(%rsi) /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
159 mov %r11d, 12(%rsi) /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
160 mov %r12d, 16(%rsi) /* d2 */
423
8e136187c0e0 Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents: 348
diff changeset
161 mov %r8d, 20(%rsi) /* d3 */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
162 mov %r13d, 40(%rsi) /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
163 mov %r14d, 44(%rsi) /* a1 */
423
8e136187c0e0 Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents: 348
diff changeset
164 mov %r9d, 48(%rsi) /* a2 */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
165 mov %r15d, 68(%rsi) /* a7 */
72
7935cd64d5c8 Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
166 mov %eax, 80(%rsi) /* current cycle count */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
167 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
168
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
169 .global m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
170 m68k_load_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
171 mov 1(%rsi), %bl /* N Flag */
207
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 198
diff changeset
172 mov 2(%rsi), %dl /* Z flag */
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 198
diff changeset
173 mov 3(%rsi), %bh /* V flag */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
174 mov 4(%rsi), %dh /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
175 mov 8(%rsi), %r10d /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
176 mov 12(%rsi), %r11d /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
177 mov 16(%rsi), %r12d /* d2 */
423
8e136187c0e0 Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents: 348
diff changeset
178 mov 20(%rsi), %r8d /* d3 */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
179 mov 40(%rsi), %r13d /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
180 mov 44(%rsi), %r14d /* a1 */
423
8e136187c0e0 Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents: 348
diff changeset
181 mov 48(%rsi), %r9d /* a2 */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
182 mov 68(%rsi), %r15d /* a7 */
72
7935cd64d5c8 Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
183 mov 76(%rsi), %ebp /* target cycle count */
7935cd64d5c8 Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
184 mov 80(%rsi), %eax /* current cycle count */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
185 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
186