Mercurial > repos > blastem
annotate runtime.S @ 343:467bfa17004a
Mostly working runtime generation of memory map read/write functions
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Sat, 18 May 2013 11:44:42 -0700 |
| parents | 146c87616b05 |
| children | b46771135442 |
| rev | line source |
|---|---|
|
17
de0085d4ea40
Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1 |
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18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
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2 .global handle_cycle_limit |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
3 .global do_sync |
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18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
4 handle_cycle_limit: |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
5 cmp 84(%rsi), %eax |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
6 jb skip_sync |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
7 do_sync: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
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8 push %rcx |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
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9 push %rdi |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
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10 call m68k_save_context |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
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11 mov %rsi, %rdi |
|
198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
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12 xor %esi, %esi |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
13 call sync_components |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
14 mov %rax, %rsi |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
15 call m68k_load_context |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
16 pop %rdi |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
17 pop %rcx |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
18 skip_sync: |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
19 ret |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
20 |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
21 .global handle_cycle_limit_int |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
22 handle_cycle_limit_int: |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
23 cmp 88(%rsi), %eax |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
24 jb skip_int |
|
251
4a7ac10ac2d9
Fix target cycle count after 68K interrupt
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
25 mov 84(%rsi), %ebp |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
26 /* swap USP and SSP if not already in supervisor mode */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
27 bt $5, 5(%rsi) |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
28 jc already_supervisor |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
29 mov 72(%rsi), %edi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
30 mov %r15d, 72(%rsi) |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
31 mov %edi, %r15d |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
32 already_supervisor: |
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175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
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33 /* save PC */ |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
34 sub $4, %r15d |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
35 mov %r15d, %edi |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
160
diff
changeset
|
36 call m68k_write_long_lowfirst |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
37 /* save status register on stack */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
38 sub $2, %r15d |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
39 mov %r15d, %edi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
40 call get_sr |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
41 call m68k_write_word |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
42 /* update status register */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
43 andb $0xF8, 5(%rsi) |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
44 mov 92(%rsi), %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
45 or $0x20, %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
46 or %cl, 5(%rsi) |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
47 /* calculate interrupt vector address */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
48 mov 92(%rsi), %ecx |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
251
diff
changeset
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49 mov %cx, 6(%rsi) /* interrupt acknowlege */ |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
50 shl $2, %ecx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
51 add $0x60, %ecx |
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321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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52 /* push %rcx |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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53 call debug_print_sr_int |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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54 pop %rcx */ |
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82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
55 call m68k_read_long_scratch1 |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
56 call m68k_native_addr_and_sync |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
57 add $24, %eax |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
58 /* discard function return address */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
59 pop %rdi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
60 jmp *%rcx |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
61 ret |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
62 skip_int: |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
63 cmp 84(%rsi), %eax |
|
198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
64 jb skip_sync_int |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
65 call m68k_save_context |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
66 mov %rsi, %rdi |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
67 mov %ecx, %esi |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
68 call sync_components |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
69 mov %rax, %rsi |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
70 call m68k_load_context |
|
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
71 skip_sync_int: |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
72 ret |
|
87
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents:
86
diff
changeset
|
73 |
|
321
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
74 sr_msg_int: |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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75 .asciz "SR set to $%X due to interrupt\n" |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
76 debug_print_sr_int: |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
77 call m68k_save_context |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
78 push %rsi |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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79 lea sr_msg_int(%rip), %rdi |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
80 movzxb 5(%rsi), %rsi |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
81 xor %rax, %rax |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
82 call printf |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
83 pop %rsi |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
84 call m68k_load_context |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
85 ret |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
86 |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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87 sr_msg: |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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88 .asciz "SR set to $%X\n" |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
89 .global debug_print_sr |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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90 debug_print_sr: |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
91 call m68k_save_context |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
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92 push %rsi |
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146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
93 lea sr_msg(%rip), %rdi |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
94 movzxb 5(%rsi), %rsi |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
95 xor %rax, %rax |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
96 call printf |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
97 pop %rsi |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
98 call m68k_load_context |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
99 ret |
|
146c87616b05
Don't update interrupt mask on non-interrupt exceptions
Mike Pavone <pavone@retrodev.com>
parents:
320
diff
changeset
|
100 |
|
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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101 .global m68k_trap |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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102 m68k_trap: |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
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103 push %rdi |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
150
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104 push %rcx |
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105 /* swap USP and SSP if not already in supervisor mode */ |
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106 bt $5, 5(%rsi) |
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107 jc already_supervisor_trap |
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108 mov 72(%rsi), %edi |
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109 mov %r15d, 72(%rsi) |
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110 mov %edi, %r15d |
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111 already_supervisor_trap: |
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175
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112 /* save PC */ |
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113 sub $4, %r15d |
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114 mov %r15d, %edi |
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115 pop %rcx |
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116 call m68k_write_long_lowfirst |
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117 /* save status register on stack */ |
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118 sub $2, %r15d |
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119 mov %r15d, %edi |
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120 call get_sr |
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121 call m68k_write_word |
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321
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122 /* set supervisor bit */ |
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123 or $0x20, 5(%rsi) |
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152
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124 /* calculate interrupt vector address */ |
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125 pop %rcx |
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126 shl $2, %ecx |
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127 call m68k_read_long_scratch1 |
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128 call m68k_native_addr_and_sync |
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226
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129 add $18, %eax |
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130 jmp *%rcx |
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176
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131 |
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132 invalid_msg: |
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133 .asciz "Invalid instruction at %X\n" |
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134 |
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135 .global m68k_invalid |
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136 m68k_invalid: |
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137 lea invalid_msg(%rip), %rdi |
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138 mov %ecx, %esi |
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139 xor %rax, %rax |
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140 call printf |
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141 mov $1, %rdi |
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142 call exit |
|
194
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143 |
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144 .global bcd_add |
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145 bcd_add: |
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146 xchg %rax, %rdi |
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147 |
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148 mov %cl, %ch |
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149 mov %al, %ah |
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150 and $0xF, %ch |
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151 and $0xF, %ah |
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152 and $0xF0, %cl |
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153 and $0xF0, %al |
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154 add %ah, %ch |
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155 cmp $10, %ch |
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156 jb no_adjust |
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157 add $6, %ch |
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158 no_adjust: |
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159 add %ch, %al |
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160 add %al, %cl |
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161 mov $0, %ch |
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162 jc def_adjust |
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163 cmp $0xA0, %cl |
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164 jb no_adjust_h |
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165 def_adjust: |
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166 add $0x60, %cl |
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167 mov $1, %ch |
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168 no_adjust_h: |
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169 |
|
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170 mov %rdi, %rax |
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|
171 ret |
|
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|
172 |
|
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173 .global bcd_sub |
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174 bcd_sub: |
|
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175 xchg %rax, %rdi |
|
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|
176 |
|
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|
177 mov %cl, %ch |
|
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|
178 mov %al, %ah |
|
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|
179 and $0xF, %ch |
|
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193
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|
180 and $0xF, %ah |
|
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193
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|
181 and $0xF0, %cl |
|
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193
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|
182 and $0xF0, %al |
|
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|
183 sub %ah, %ch |
|
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|
184 cmp $10, %ch |
|
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|
185 jb no_adjusts |
|
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|
186 sub $6, %ch |
|
811163790e6c
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193
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|
187 no_adjusts: |
|
811163790e6c
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193
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|
188 add %ch, %cl |
|
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|
189 sub %al, %cl |
|
811163790e6c
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|
190 mov $0, %ch |
|
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|
191 jc def_adjusts |
|
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|
192 cmp $0xA0, %cl |
|
811163790e6c
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193
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|
193 jb no_adjust_hs |
|
811163790e6c
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193
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|
194 def_adjusts: |
|
811163790e6c
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193
diff
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|
195 sub $0x60, %cl |
|
811163790e6c
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193
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|
196 mov $1, %ch |
|
811163790e6c
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193
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|
197 no_adjust_hs: |
|
811163790e6c
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|
198 |
|
811163790e6c
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|
199 mov %rdi, %rax |
|
811163790e6c
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|
200 ret |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
201 |
|
87
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
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86
diff
changeset
|
202 int_dbg_msg: |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
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86
diff
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|
203 .asciz "Executing Interrupt!" |
|
60b5c9e2f4e0
vertical interrupts now work
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86
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|
204 print_int_dbg: |
|
60b5c9e2f4e0
vertical interrupts now work
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86
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|
205 call m68k_save_context |
|
60b5c9e2f4e0
vertical interrupts now work
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86
diff
changeset
|
206 push %rsi |
|
60b5c9e2f4e0
vertical interrupts now work
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86
diff
changeset
|
207 lea int_dbg_msg(%rip), %rdi |
|
60b5c9e2f4e0
vertical interrupts now work
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86
diff
changeset
|
208 call puts |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
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86
diff
changeset
|
209 pop %rsi |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
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86
diff
changeset
|
210 call m68k_load_context |
|
60b5c9e2f4e0
vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
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86
diff
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|
211 ret |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
212 |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
213 .global get_sr |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
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|
214 get_sr: |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
215 mov 5(%rsi), %cl |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
216 shl $8, %cx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
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217 mov (%rsi), %cl |
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218 shl $1, %cl |
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219 or %bl, %cl |
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220 shl $1, %cl |
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221 or %dl, %cl |
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222 shl $1, %cl |
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223 or %bh, %cl |
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224 shl $1, %cl |
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225 or %dh, %cl |
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226 ret |
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227 |
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228 .global set_sr |
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229 set_sr: |
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230 mov %cl, %dh |
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231 and $1, %dh |
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232 shr $1, %cl |
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233 mov %cl, %bh |
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234 and $1, %bh |
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235 shr $1, %cl |
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236 mov %cl, %dl |
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237 and $1, %dl |
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238 shr $1, %cl |
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239 mov %cl, %bl |
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240 and $1, %bl |
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241 shr $1, %cl |
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242 and $1, %cl |
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243 mov %cl, (%rsi) |
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244 shr $8, %cx |
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245 mov %cl, 5(%rsi) |
|
321
146c87616b05
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246 /* call debug_print_sr */ |
|
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247 ret |
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248 |
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249 .global set_ccr |
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250 set_ccr: |
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251 mov %cl, %dh |
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252 and $1, %dh |
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253 shr $1, %cl |
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254 mov %cl, %bh |
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255 and $1, %bh |
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256 shr $1, %cl |
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257 mov %cl, %dl |
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258 and $1, %dl |
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259 shr $1, %cl |
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260 mov %cl, %bl |
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261 and $1, %bl |
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262 shr $1, %cl |
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263 and $1, %cl |
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264 mov %cl, (%rsi) |
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265 ret |
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266 |
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267 do_vdp_port_write: |
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268 call m68k_save_context |
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269 mov %rcx, %rdx |
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270 call vdp_port_write |
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271 mov %rax, %rsi |
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272 call m68k_load_context |
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273 ret |
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274 |
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275 do_vdp_port_read: |
|
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Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
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276 mov %ecx, %edi |
|
54
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277 call m68k_save_context |
|
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278 push %rsi |
|
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279 call vdp_port_read |
|
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280 pop %rsi |
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281 mov %ax, %cx |
|
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282 call m68k_load_context |
|
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3e7bfde7606e
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283 ret |
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284 |
| 66 | 285 do_io_write: |
| 286 call m68k_save_context | |
|
153
42c031184e8a
Implement access to Z80 RAM
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287 and $0x1FFFF, %edi |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
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288 mov %ecx, %edx |
| 66 | 289 call io_write |
| 290 mov %rax, %rsi | |
| 291 call m68k_load_context | |
| 292 ret | |
| 293 do_io_read: | |
| 294 mov %ecx, %edi | |
|
153
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Implement access to Z80 RAM
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295 and $0x1FFFF, %edi |
| 66 | 296 call m68k_save_context |
|
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297 push %rsi |
| 66 | 298 call io_read |
|
343
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299 pop %rsi |
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300 mov %al, %cl |
| 66 | 301 call m68k_load_context |
| 302 ret | |
|
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303 |
|
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|
304 do_io_write_w: |
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305 call m68k_save_context |
|
153
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306 and $0x1FFFF, %edi |
|
83
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|
307 mov %ecx, %edx |
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|
308 call io_write_w |
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|
309 mov %rax, %rsi |
|
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|
310 call m68k_load_context |
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|
311 ret |
|
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|
312 do_io_read_w: |
|
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|
313 mov %ecx, %edi |
|
153
42c031184e8a
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|
314 and $0x1FFFF, %edi |
|
83
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|
315 call m68k_save_context |
|
343
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|
316 push %rsi |
|
83
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|
317 call io_read_w |
|
343
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|
318 pop %rsi |
|
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|
319 mov %ax, %cx |
|
83
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|
320 call m68k_load_context |
|
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|
321 ret |
| 66 | 322 |
|
54
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|
323 bad_access_msg: |
|
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|
324 .asciz "Program tried to access illegal 68K address %X\n" |
|
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changeset
|
325 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
326 .global m68k_write_word |
|
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
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changeset
|
327 .global try_fifo_write |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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changeset
|
328 m68k_write_word: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
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59
diff
changeset
|
329 call inccycles |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
330 and $0xFFFFFF, %rdi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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|
331 cmp $0x400000, %edi |
|
104
a0fdaa134964
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95
diff
changeset
|
332 jbe cart_w |
|
18
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17
diff
changeset
|
333 cmp $0xE00000, %edi |
|
104
a0fdaa134964
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95
diff
changeset
|
334 jae workram_w |
|
54
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diff
changeset
|
335 cmp $0xC00000, %edi |
|
104
a0fdaa134964
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diff
changeset
|
336 jae vdp_psg_w |
|
153
42c031184e8a
Implement access to Z80 RAM
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152
diff
changeset
|
337 cmp $0xA00000, %edi |
|
104
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diff
changeset
|
338 jb not_io_w |
|
85
1db2a0b655d1
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84
diff
changeset
|
339 cmp $0xA12000, %edi |
|
104
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95
diff
changeset
|
340 jae not_io_w |
|
85
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84
diff
changeset
|
341 jmp do_io_write_w |
|
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84
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changeset
|
342 not_io_w: |
|
64
2b1a65f4b85d
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|
343 ret |
|
18
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344 workram_w: |
|
193
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|
345 and $0xFFFF, %edi |
|
18
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|
346 mov %cx, (%r9, %rdi) |
|
193
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|
347 mov %edi, %ecx |
|
320
67b6d351df0e
Fix check for code writes
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317
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|
348 shr $11, %ecx |
|
193
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|
349 bt %ecx, 160(%rsi) |
|
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|
350 jnc not_code |
|
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|
351 call m68k_save_context |
|
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|
352 call m68k_handle_code_write |
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353 mov %rax, %rsi |
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|
354 call m68k_load_context |
|
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|
355 not_code: |
|
64
2b1a65f4b85d
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diff
changeset
|
356 ret |
|
18
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357 cart_w: |
|
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|
358 mov %cx, (%r8, %rdi) |
|
64
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|
359 ret |
|
54
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changeset
|
360 vdp_psg_w: |
|
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diff
changeset
|
361 test $0x2700E0, %edi |
|
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|
362 jnz crash |
|
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|
363 and $0x1F, %edi |
|
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changeset
|
364 cmp $4, %edi |
|
104
a0fdaa134964
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
365 jb try_fifo_write |
|
54
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|
366 jmp do_vdp_port_write |
|
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|
367 try_fifo_write: |
|
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|
368 push %rdx |
|
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|
369 push %rbx |
|
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changeset
|
370 /* fetch VDP context pointer from 68K context */ |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
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72
diff
changeset
|
371 mov 128(%rsi), %rdx |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
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changeset
|
372 /* check DMA flag */ |
|
139e5dcd6aa3
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changeset
|
373 bt $6, 19(%rdx) |
|
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changeset
|
374 jc fifo_fallback |
|
54
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changeset
|
375 /* get fifo_cur and compare it to fifo_end */ |
|
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diff
changeset
|
376 mov (%rdx), %rbx |
|
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changeset
|
377 cmp %rbx, 8(%rdx) |
|
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changeset
|
378 /* bail out if fifo is full */ |
|
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diff
changeset
|
379 je fifo_fallback |
|
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diff
changeset
|
380 /* populate FIFO entry */ |
| 138 | 381 mov %cx, 6(%rbx) /* value */ |
| 382 mov 16(%rdx), %cx | |
| 383 mov %cx, 4(%rbx) /* address */ | |
| 384 mov 18(%rdx), %cl | |
| 385 mov %cl, 8(%rbx) /* cd */ | |
| 386 movb $0, 9(%rbx) /* partial */ | |
|
54
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diff
changeset
|
387 mov %eax, %ecx |
|
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diff
changeset
|
388 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */ |
|
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changeset
|
389 sub %eax, %ecx |
|
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changeset
|
390 mov %ecx, (%rbx) /* cycle */ |
|
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diff
changeset
|
391 /* update fifo_cur and store back in 68K context */ |
| 138 | 392 add $12, %rbx |
|
54
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diff
changeset
|
393 mov %rbx, (%rdx) |
| 138 | 394 /* update address register */ |
| 395 movzbw 35(%rdx), %bx | |
| 396 add %bx, 16(%rdx) | |
|
54
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diff
changeset
|
397 /* clear pending flag */ |
|
3b79cbcf6846
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diff
changeset
|
398 andb $0xEF, 19(%rdx) |
|
3b79cbcf6846
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diff
changeset
|
399 pop %rbx |
|
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diff
changeset
|
400 pop %rdx |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
401 ret |
|
54
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
402 fifo_fallback: |
|
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diff
changeset
|
403 pop %rbx |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
404 pop %rdx |
|
3b79cbcf6846
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diff
changeset
|
405 jmp do_vdp_port_write |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
406 crash: |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
407 mov %edi, %esi |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
408 lea bad_access_msg(%rip), %rdi |
|
160
69ac23d42897
Fix crash in printf from "crash" function due to lack of clearing rax
Mike Pavone <pavone@retrodev.com>
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153
diff
changeset
|
409 xor %rax, %rax |
|
54
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
410 call printf |
|
3b79cbcf6846
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53
diff
changeset
|
411 mov $1, %rdi |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
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53
diff
changeset
|
412 call exit |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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17
diff
changeset
|
413 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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17
diff
changeset
|
414 .global m68k_write_byte |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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17
diff
changeset
|
415 m68k_write_byte: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
416 call inccycles |
|
18
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
417 and $0xFFFFFF, %rdi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
418 cmp $0x400000, %edi |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
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95
diff
changeset
|
419 jbe cart_wb |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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17
diff
changeset
|
420 cmp $0xE00000, %edi |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
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95
diff
changeset
|
421 jae workram_wb |
| 66 | 422 cmp $0xC00000, %edi |
|
104
a0fdaa134964
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Mike Pavone <pavone@retrodev.com>
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95
diff
changeset
|
423 jae vdp_psg_wb |
|
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
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152
diff
changeset
|
424 cmp $0xA00000, %edi |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
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95
diff
changeset
|
425 jb not_io_wb |
|
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
426 cmp $0xA12000, %edi |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
427 jae not_io_wb |
| 66 | 428 jmp do_io_write |
| 429 not_io_wb: | |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
430 ret |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
431 workram_wb: |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
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82
diff
changeset
|
432 /* deal with byte swapping */ |
|
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
433 xor $1, %edi |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
434 and $0xFFFF, %rdi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
435 mov %cl, (%r9, %rdi) |
|
193
c66e4636f991
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Mike Pavone <pavone@retrodev.com>
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176
diff
changeset
|
436 mov %edi, %ecx |
|
320
67b6d351df0e
Fix check for code writes
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
437 shr $11, %ecx |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
438 bt %ecx, 160(%rsi) |
|
c66e4636f991
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176
diff
changeset
|
439 jnc not_code_b |
|
c66e4636f991
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176
diff
changeset
|
440 xor $1, %edi |
|
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diff
changeset
|
441 call m68k_save_context |
|
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changeset
|
442 call m68k_handle_code_write |
|
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diff
changeset
|
443 mov %rax, %rsi |
|
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176
diff
changeset
|
444 call m68k_load_context |
|
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176
diff
changeset
|
445 not_code_b: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
446 ret |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
447 cart_wb: |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
448 /* deal with byte swapping */ |
|
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
449 xor $1, %edi |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
450 mov %cl, (%r8, %rdi) |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
451 ret |
| 66 | 452 vdp_psg_wb: |
| 453 push %rdx | |
| 454 mov %cl, %dl | |
| 455 and $0xFF, %cx | |
| 456 shl $8, %dx | |
| 457 or %dx, %cx | |
| 458 pop %rdx | |
| 459 jmp vdp_psg_w | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
460 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
461 .global m68k_write_long_lowfirst |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
462 m68k_write_long_lowfirst: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
463 push %rdi |
|
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
464 push %rcx |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
465 add $2, %edi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
466 call m68k_write_word |
|
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
467 pop %rcx |
|
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
468 pop %rdi |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
469 shr $16, %ecx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
470 jmp m68k_write_word |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
471 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
472 .global m68k_write_long_highfirst |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
473 m68k_write_long_highfirst: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
474 push %rdi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
475 push %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
476 shr $16, %ecx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
477 call m68k_write_word |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
478 pop %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
479 pop %rdi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
480 add $2, %rdi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
481 jmp m68k_write_word |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
482 |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
483 inccycles: |
|
251
4a7ac10ac2d9
Fix target cycle count after 68K interrupt
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
484 cmp %ebp, %eax |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
485 jnb do_limit |
|
251
4a7ac10ac2d9
Fix target cycle count after 68K interrupt
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
486 add $4, %eax |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
487 ret |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
488 do_limit: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
489 |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
490 call handle_cycle_limit |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
491 pop %rdi |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
492 pop %rcx |
|
251
4a7ac10ac2d9
Fix target cycle count after 68K interrupt
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
493 add $4, %eax |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
494 ret |
|
17
de0085d4ea40
Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
496 .global m68k_read_word_scratch1 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
497 m68k_read_word_scratch1: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
498 call inccycles |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
499 and $0xFFFFFF, %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
500 cmp $0x400000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
501 jbe cart |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
502 cmp $0xE00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
503 jae workram |
|
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
504 cmp $0xC00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
505 jae vdp_psg |
|
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
506 cmp $0xA00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
507 jb not_io |
|
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
508 cmp $0xA12000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
509 jae not_io |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
510 call do_io_read_w |
|
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
511 ret |
|
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
512 not_io: |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
513 xor %cx, %cx |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
514 dec %cx |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
515 ret |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
516 workram: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
517 and $0xFFFF, %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
518 mov (%r9, %rcx), %cx |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
519 ret |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
520 vdp_psg: |
|
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
521 test $0x2700E0, %ecx |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
522 jnz crash |
|
57
bc3bc7a60c4e
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
523 and $0x1F, %ecx |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
524 jmp do_vdp_port_read |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
525 cart: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
526 mov (%r8, %rcx), %cx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
527 ret |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
528 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
529 .global m68k_read_long_scratch1 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
530 m68k_read_long_scratch1: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
531 push %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
532 call m68k_read_word_scratch1 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
533 mov %cx, %di |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
534 pop %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
535 add $2, %ecx |
|
84
2d1ae596db7a
Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents:
83
diff
changeset
|
536 push %rdi |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
537 call m68k_read_word_scratch1 |
|
84
2d1ae596db7a
Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents:
83
diff
changeset
|
538 pop %rdi |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
539 and $0xFFFF, %ecx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
540 shl $16, %edi |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
541 or %edi, %ecx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
542 ret |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
543 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
544 .global m68k_read_byte_scratch1 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
545 m68k_read_byte_scratch1: |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
546 call inccycles |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
547 and $0xFFFFFF, %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
548 cmp $0x400000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
549 jbe cart_b |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
550 cmp $0xE00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
551 jae workram_b |
| 137 | 552 cmp $0xC00000, %ecx |
| 553 jae vdp_psg_b | |
|
153
42c031184e8a
Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
554 cmp $0xA00000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
555 jb not_io_b |
|
85
1db2a0b655d1
Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents:
84
diff
changeset
|
556 cmp $0xA12000, %ecx |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
557 jae not_io_b |
| 66 | 558 jmp do_io_read |
| 559 not_io_b: | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
560 xor %cl, %cl |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
561 dec %cl |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
562 ret |
| 137 | 563 vdp_psg_b: |
| 564 test $0x2700E0, %ecx | |
| 565 jnz crash | |
| 566 and $0x1F, %ecx | |
| 567 bt $0, %ecx | |
| 568 jnc vdp_swap | |
| 569 jmp do_vdp_port_read | |
| 570 vdp_swap: | |
| 571 call do_vdp_port_read | |
| 572 shr $8, %cx | |
| 573 ret | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
574 workram_b: |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
575 /* deal with byte swapping */ |
|
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
576 xor $1, %ecx |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
577 and $0xFFFF, %rcx |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
578 mov (%r9, %rcx), %cl |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
579 ret |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
580 cart_b: |
|
83
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
581 /* deal with byte swapping */ |
|
2c7267617d71
Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
582 xor $1, %ecx |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
583 mov (%r8, %rcx), %cl |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
584 ret |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
585 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
586 .global m68k_modified_ret_addr |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
587 m68k_modified_ret_addr: |
|
145
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
588 add $16, %rsp |
|
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
589 call m68k_native_addr |
|
15b8dce19cf4
Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
590 jmp *%rcx |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
591 |
|
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
592 dyn_addr_msg: |
|
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
593 .asciz "Program needs dynamically calculated native address\n" |
|
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
594 |
|
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
595 .global m68k_native_addr_and_sync |
|
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
596 m68k_native_addr_and_sync: |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
597 call m68k_save_context |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
598 push %rcx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
599 mov %rsi, %rdi |
|
198
209a37eed3e7
Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
600 xor %esi, %esi |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
601 call sync_components |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
602 pop %rsi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
603 push %rax |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
604 mov %rax, %rdi |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
605 call get_native_address_trans |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
606 mov %rax, %rcx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
607 pop %rsi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
608 call m68k_load_context |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
609 ret |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
610 |
|
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
611 .global m68k_native_addr |
|
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
85
diff
changeset
|
612 m68k_native_addr: |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
613 call m68k_save_context |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
614 push %rsi |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
615 mov %rsi, %rdi |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
616 mov %ecx, %esi |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
617 call get_native_address_trans |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
618 mov %rax, %rcx |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
619 pop %rsi |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
620 call m68k_load_context |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
621 ret |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
622 |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
623 .global m68k_retrans_stub |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
624 m68k_retrans_stub: |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
625 call m68k_save_context |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
626 push %rsi |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
627 call m68k_retranslate_inst |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
628 pop %rsi |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
629 mov %rax, %rcx |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
630 call m68k_load_context |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
631 jmp *%rcx |
|
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
632 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
633 .global m68k_save_context |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
634 m68k_save_context: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
635 mov %bl, 1(%rsi) /* N Flag */ |
| 207 | 636 mov %dl, 2(%rsi) /* Z flag */ |
| 637 mov %bh, 3(%rsi) /* V flag */ | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
638 mov %dh, 4(%rsi) /* C flag */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
639 mov %r10d, 8(%rsi) /* d0 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
640 mov %r11d, 12(%rsi) /* d1 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
641 mov %r12d, 16(%rsi) /* d2 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
642 mov %r13d, 40(%rsi) /* a0 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
643 mov %r14d, 44(%rsi) /* a1 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
644 mov %r15d, 68(%rsi) /* a7 */ |
|
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
645 mov %eax, 80(%rsi) /* current cycle count */ |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
646 ret |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
647 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
648 .global m68k_load_context |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
649 m68k_load_context: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
650 mov 1(%rsi), %bl /* N Flag */ |
| 207 | 651 mov 2(%rsi), %dl /* Z flag */ |
| 652 mov 3(%rsi), %bh /* V flag */ | |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
653 mov 4(%rsi), %dh /* C flag */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
654 mov 8(%rsi), %r10d /* d0 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
655 mov 12(%rsi), %r11d /* d1 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
656 mov 16(%rsi), %r12d /* d2 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
657 mov 40(%rsi), %r13d /* a0 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
658 mov 44(%rsi), %r14d /* a1 */ |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
659 mov 68(%rsi), %r15d /* a7 */ |
|
72
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
660 mov 76(%rsi), %ebp /* target cycle count */ |
|
7935cd64d5c8
Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents:
66
diff
changeset
|
661 mov 80(%rsi), %eax /* current cycle count */ |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
662 mov 96(%rsi), %r8d /* cartridge address */ |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
72
diff
changeset
|
663 mov 104(%rsi), %r9d /* work ram address */ |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
664 ret |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
665 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
666 .global m68k_start_context |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
667 m68k_start_context: |
|
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
668 push %rbp |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
669 push %r12 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
670 push %r13 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
671 push %r14 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
672 push %r15 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
673 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
17
diff
changeset
|
674 call m68k_load_context |
|
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
675 call *%rdi |
|
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
676 call m68k_save_context |
|
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
677 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
678 pop %r15 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
679 pop %r14 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
680 pop %r13 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
681 pop %r12 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
682 pop %rbp |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
683 |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
684 ret |