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annotate m68k.cpu @ 2578:9b01541cbd60

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Fix rol and ror in new CPU core
author Michael Pavone <pavone@retrodev.com>
date Fri, 07 Feb 2025 19:58:20 -0800
parents 5f725429d08f
children 939b818df589
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1 info
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2 prefix m68k_
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3 opcode_size 16
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4 body m68k_run_op
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5 header m68k.h
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6 interrupt m68k_interrupt
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7 include m68k_util.c
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8 sync_cycle m68k_sync_cycle
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9
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10 declare
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11 typedef m68k_context *(sync_fun)(m68k_context * context, uint32_t address);
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12 typedef m68k_context *(*int_ack_fun)(m68k_context * context);
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13 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context);
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14 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun *sync_components, int_ack_fun int_ack);
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15 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler *reset_handler);
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16 void m68k_reset(m68k_context *context);
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17 void m68k_print_regs(m68k_context *context);
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18 void m68k_serialize(m68k_context *context, uint32_t pc, serialize_buffer *buf);
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19 void m68k_deserialize(deserialize_buffer *buf, void *vcontext);
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20 void start_68k_context(m68k_context *context, uint32_t pc);
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21 define NUM_MEM_AREAS 10
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22 define M68K_OPT_BROKEN_READ_MODIFY 1
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23 define INT_PENDING_SR_CHANGE 254
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24 define INT_PENDING_NONE 255
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25 define M68K_STATUS_TRACE 0x80
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26 define m68k_invalidate_code_range(context, start, end)
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27 define m68k_options_free free
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28 define m68k_handle_code_write(address, context)
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29 define resume_68k(context) m68k_execute(context, context->target_cycle)
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30 define insert_breakpoint(context, address, handler)
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31 define remove_breakpoint(context, address)
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32 define m68k_add_watchpoint(context, address, size)
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33 define m68k_remove_watchpoint(context, address, size)
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34
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35 regs
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36 dregs 32 d0 d1 d2 d3 d4 d5 d6 d7
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37 aregs 32 a0 a1 a2 a3 a4 a5 a6 a7
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38 pc 32
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39 other_sp 32
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40 scratch1 32
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41 scratch2 32
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42 int_cycle 32
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43 target_cycle 32
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44 wp_hit_address 32
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45 prefetch 16
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46 wp_hit_value 16
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47 wp_old_value 16
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48 int_priority 8
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49 int_num 8
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50 int_pending 8
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51 int_pending_num 8
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52 int_ack 8
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53 status 8
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54 ccr 8
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55 xflag 8
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56 nflag 8
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57 zflag 8
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58 vflag 8
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59 cflag 8
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60 wp_hit 8
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61 trace_pending 8
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62 should_return 8
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63 system ptrvoid
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64 reset_handler ptrvoid
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65 int_ack_handler ptrvoid
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66 sync_components ptrsync_fun
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67 mem_pointers ptr16 10
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68
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69 flags
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70 register ccr
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71 X 4 carry xflag
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72 N 3 sign nflag
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73 Z 2 zero zflag
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74 V 1 overflow vflag
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75 C 0 carry cflag
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76
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77 m68k_prefetch
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78 if dynarec
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79
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80 ccall m68k_read16_noinc context pc
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81 mov result prefetch
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82
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83 end
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84
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85 if interp
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86
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87 mov pc scratch1
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88 ocall read_16
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89 mov scratch1 prefetch
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90
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91 end
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92
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93 add 2 pc pc
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94
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95 check_user_mode_swap_ssp_usp
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96 local tmp 8
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97 and 0x20 status tmp
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98 if tmp
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99 else
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100 xchg other_sp a7
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101 end
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102
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103 m68k_get_sr
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104 lsl status 8 scratch1
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105 or ccr scratch1 scratch1
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106
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107 m68k_write32_lowfirst
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108 arg value 32
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109 add 2 scratch2 scratch2
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110 mov value scratch1
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111 ocall write_16
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112
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113 sub 2 scratch2 scratch2
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114 lsr value 16 scratch1
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115 ocall write_16
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116
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117 m68k_write32
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118 arg value 32
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119 local tmp 32
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120 mov value tmp
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121 lsr value 16 scratch1
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122 ocall write_16
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123
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124 add 2 scratch2 scratch2
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125 mov tmp scratch1
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126 ocall write_16
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127
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128 m68k_read32
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129 local tmp 32
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130 add 2 scratch1 tmp
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131 ocall read_16
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132 xchg scratch1 tmp
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133 ocall read_16
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134 lsl tmp 16 tmp
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135 or tmp scratch1 scratch1
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136
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137 m68k_trap
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138 arg vector 32
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139 check_user_mode_swap_ssp_usp
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140 #save PC
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141 a7 -= 4
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142 scratch2 = a7
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143 m68k_write32_lowfirst pc
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parents: 2502
diff changeset
144 #save SR
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
145 a7 -= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
146 scratch2 = a7
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Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
147 m68k_get_sr
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Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
148 ocall write_16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
149 #set supervisor bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
150 status |= 0x20
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
151 #clear trace bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
152 status &= 0x7F
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
153 trace_pending = 0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
154 scratch1 = vector << 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
155 m68k_read32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
156 pc = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
157 cycles 10
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
158 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
159
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
160
1838
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 m68k_interrupt
2577
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
163 if cycles >=U int_cycle
1838
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parents:
diff changeset
164
2577
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
165 #INT_PENDING_NONE
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
166 if 255 = int_pending
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
167 int_pending = int_priority
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
168 int_pending_num = int_num
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
169 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
170
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
171 #INT_PENDING_SR_CHANGE
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
172 if 254 = int_pending
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
173 int_pending = int_priority
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
174 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
175
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
176 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
177
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
178 check_user_mode_swap_ssp_usp
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
179
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
180 cycles 6
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
181 #save status reg
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
182 sub 6 a7 a7
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
183 m68k_get_sr
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
184 mov a7 scratch2
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
185 ocall write_16
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
186
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
187 #update status register
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
188 and 0x78 status status
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
189 or int_priority status status
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
190 or 0x20 status status
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
191
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
192 #Interrupt ack cycle
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
193 mov int_pending int_ack
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
194 cycles 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
195 if int_ack_handler
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
196 pcall int_ack_handler int_ack_fun context
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
197 end
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
198 if int_pending_num
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
199 else
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
200 int_pending_num = int_pending + 24
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
201 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
202
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
203 #save pc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
204 add 2 a7 scratch2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
205 m68k_write32_lowfirst pc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
206
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
207 lsl int_pending_num 2 scratch1
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
208 m68k_read32
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
209 mov scratch1 pc
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
210 update_sync
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
211 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
212 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 dispatch prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218 m68k_mem_src
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 arg address 32
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 arg size 16
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 arg isdst 8
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 mov address scratch1
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 mov address scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 meta ismem 1
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 case 0
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 ocall read_8
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 case 1
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 case 2
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 m68k_write_size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 arg lowfirst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 ocall write_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 if lowfirst
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253 m68k_write32_lowfirst scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 m68k_write32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 local disp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 and prefetch 255 disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 sext 16 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 sext 32 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 local index 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266 lsr prefetch 12 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 local isareg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 and index 8 isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 and index 7 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 local islong 16
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 and prefetch 2048 islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 switch isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 sext 32 dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 mov dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281 case 8
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 sext 32 aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286 mov aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 add disp scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 m68k_fetch_op_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299 #data reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300 meta op dregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 #address reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 meta op aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 #address reg indirect
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 #postincrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 addsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331 #predecrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 decsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 cycles 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 #displacement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 add scratch1 aregs.reg scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 #indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
355 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 add aregs.reg scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 #pc-relative and absolute modes
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 #absolute short
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 #absolute long
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 local address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 lsl prefetch 16 address
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 or prefetch address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 #pc displaceent
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 add scratch1 pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 #pc indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
389 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 add pc scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 #immediate
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 local tmp32 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 lsl prefetch 16 tmp32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 or prefetch tmp32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 mov prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 m68k_fetch_src_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 m68k_fetch_op_ea mode reg Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 meta src op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 meta src_is_mem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 m68k_fetch_dst_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 m68k_fetch_op_ea mode reg Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 meta dst op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 m68k_save_dst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 if ismem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 1101DDD0ZZMMMRRR add_ea_dn
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 m68k_fetch_src_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 add src dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 1101DDD1ZZMMMRRR add_dn_ea
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
454 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
455 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 add dregs.D dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 1101AAAZ11MMMRRR adda
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 local size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 local ext_src 32
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
476 #TODO: ensure "penalty" cycles are in the right place
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
478 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
479 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
480 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
481 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
482 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
483 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
484 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
485 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
486 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
487 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
488 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
489 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
490 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
491 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
492 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
493 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
494 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
495 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
497 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
498 cycles 4
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 m68k_fetch_src_ea M R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 sext 32 src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 meta src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 add src aregs.A aregs.A
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 00000110ZZMMMRRR addi
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 local immed 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 invalid Z 3
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
513 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 #fetch immediate operand
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 lsl prefetch 16 immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
527 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
528 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
529 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 mov prefetch immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 #fetch dst EA
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 add immed dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 0101III0ZZMMMRRR addq
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 local src 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 switch I
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 mov 8 src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 mov I src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559 case 1
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
560 cycles 4
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 1101DDD1ZZ000SSS addx_dy_dx
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 adc dregs.S dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 case 0
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
575 local tmp8 8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
576 mov dregs.D tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
577 if tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
578 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
579 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 case 1
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
581 local tmp16 16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
582 mov dregs.D tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
583 if tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
584 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
585 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
586 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
587 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
588 if dregs.D
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
589 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
590 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
591 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
592 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
593
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
594 1101DDD1ZZ001SSS addx_ay_ax
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
595 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
596 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
597 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
598 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
599 switch S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
601 sub 2 aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
606 #predec penalty on src only
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
607 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 mov aregs.S scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 mov scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 switch D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 sub 2 aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 mov aregs.D scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 adc scratch2 scratch1 scratch1 Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 local tmp8 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642 mov dregs.D tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 if tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647 local tmp16 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 mov dregs.D tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 if tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 if dregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 mov aregs.D scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
660
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
661 1100DDD0ZZMMMRRR and_ea_dn
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
662 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
663 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
664 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
665 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
666 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
667 m68k_fetch_src_ea M R Z
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
669 and src dregs.D dregs.D Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
670 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
671 m68k_prefetch
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
672
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
673 1100XXX101000YYY exg_dn_dn
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
674 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
675 dregs.X = dregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
676 dregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
677 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
678 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
679
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
680 1100XXX101001YYY exg_an_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
681 scratch1 = aregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
682 aregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
683 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
684 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
685 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
686
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
687 1100XXX110001YYY exg_dn_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
688 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
689 dregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
690 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
691 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
692 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
693
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
694 1100DDD011MMMRRR mulu
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
695 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
696 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
697 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
698 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
699 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
700 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
701
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
702 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
703 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
704 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
705 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
706 a = src & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
707 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
708 b = src & 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
709 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
710 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
711 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
712 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
713 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
714 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
715 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
716 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
717 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
718 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
719 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
720 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
721 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
722 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
723 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
724 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
725 dregs.D = src * dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
726 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
727 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
728
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
729 1100DDD111MMMRRR muls
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
730 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
731 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
732 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
733 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
734 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
735 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
736
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
737 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
738 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
739 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
740 #muls timing is essentially the same as muls, but it's based on the number of 0/1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
741 #transitions rather than the number of 1 bits. xoring the value with itself shifted
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
742 #by one effectively sets one bit for every transition
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
743 b = src << 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
744 b ^= src
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
745 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
746 a = b & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
747 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
748 b &= 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
749 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
750 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
751 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
752 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
753 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
754 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
755 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
756 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
757 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
758 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
759 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
760 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
761 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
762 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
763 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
764 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
765 dregs.D = src *S dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
766 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
767 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
768
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
769 1100DDD1ZZMMMRRR and_dn_ea
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
770 invalid M 0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
771 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
772 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
773 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
774 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
775 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
776 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
777 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
778 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
779 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
780
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
781 and dregs.D dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
782 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
783 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
784 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
785
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
786 00000010ZZMMMRRR andi
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
787 local immed 32
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
788 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
789 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
790 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
791 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
792 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
793 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
794 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
795 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
796 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
797 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
798 switch Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
799 case 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
800 lsl prefetch 16 immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
801 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
802 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
803 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
804 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
805 end
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
806 default
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
807 mov prefetch immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
808 end
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
809 #fetch dst EA
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
810 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
811
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
812 and immed dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
813 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
814 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
815 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
816
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
817 0000001000111100 andi_to_ccr
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
818 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
819 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
820 and prefetch ccr ccr
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
821 m68k_prefetch
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
822
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
823 1011DDD1ZZMMMRRR eor_dn_ea
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
824 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
825 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
826 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
827 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
828 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
829 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
830 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
831 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
832 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
833
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
834 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
835 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
836 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
837 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
838 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
839
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
840 xor dregs.D dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
841 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
842 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
843 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
844
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
845 00001010ZZMMMRRR eori
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
846 local immed 32
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
847 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
848 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
849 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
850 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
851 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
852 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
853 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
854 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
855 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
856 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
857 switch Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
858 case 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
859 lsl prefetch 16 immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
860 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
861 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
862 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
863 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
864 end
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
865 default
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
866 mov prefetch immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
867 end
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
868 #fetch dst EA
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
869 m68k_fetch_dst_ea M R Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
870
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
871 xor immed dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
872 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
873 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
874 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
875
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
876 0000001000111100 eori_to_ccr
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
877 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
878 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
879 xor prefetch ccr ccr
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
880 m68k_prefetch
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
881
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
882 1000DDD0ZZMMMRRR or_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
883 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
884 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
885 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
886 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
887 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
888 m68k_fetch_src_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
889
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
890 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
891 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
892 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
893 #dreg
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
894 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
895 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
896 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
897 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
898 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
899 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
900 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
901 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
902 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
903 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
904 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
905 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
906
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
907 or src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
908 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
909 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
910
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
911 1000DDD1ZZMMMRRR or_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
912 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
913 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
914 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
915 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
916 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
917 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
918 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
919 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
920 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
921 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
922
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
923 or dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
924 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
925 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
926 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
927
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
928 00000000ZZMMMRRR ori
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
929 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
930 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
931 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
932 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
933 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
934 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
935 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
936 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
937 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
938 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
939 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
940 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
941 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
942 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
943 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
944 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
945 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
946 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
947 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
948 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
949 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
950 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
951 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
952 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
953
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
954 or immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
955 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
956 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
957 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
958
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
959 0000000000111100 ori_to_ccr
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
960 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
961 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
962 or prefetch ccr ccr
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
963 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
964
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
965 1001DDD0ZZMMMRRR sub_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
966 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
967 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
968 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
969 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
970 m68k_fetch_src_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
971
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
972 sub src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
973 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
974 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
975
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
976 1001DDD1ZZMMMRRR sub_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
977 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
978 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
979 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
980 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
981 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
982 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
983 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
984 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
985 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
986 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
987
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
988 sub dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
989 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
990 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
991 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
992
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
993 1001AAAZ11MMMRRR suba
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
994 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
995 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
996 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
997 local size 16
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
998 local ext_src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
999 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1000 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1001 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1002 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1003 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1004 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1005 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1006 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1007 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1008 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1009 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1010 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1011 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1012 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1013 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1014 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1015 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1016 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1017 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1018 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1019 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1020 cycles 4
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1021 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1022 m68k_fetch_src_ea M R size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1023 switch size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1024 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1025 sext 32 src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1026 meta src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1027 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1028
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1029 sub src aregs.A aregs.A
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1030 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1031
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1032 00000100ZZMMMRRR subi
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1033 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1034 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1035 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1036 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1037 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1038 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1039 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1040 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1041 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1042 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1043 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1044 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1045 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1046 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1047 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1048 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1049 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1050 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1051 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1052 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1053 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1054 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1055 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1056 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1057
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1058 sub immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1059 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1060 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1061 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1062
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1063 0101III1ZZMMMRRR subq
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1064 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1065 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1066 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1067 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1068 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1069 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1070 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1071 local src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1072 switch I
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1073 case 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1074 mov 8 src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1075 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1076 mov I src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1077 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1078
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1079 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1080 switch M
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1081 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1082 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1083 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1084 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1085 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1086 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1087 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1088 m68k_prefetch
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1089
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1090 1110CCC0ZZ001RRR lsri
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1091 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1092 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1093 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1094 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1095 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1096 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1097 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1098 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1099 update_flags XNZV0C
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1100 local cyc 32
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1101 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1102 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1103 case 2
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1104 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1105 default
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1106 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1107 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1108 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1109 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1110 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1111
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1112 1110CCC0ZZ101RRR lsr_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1113 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1114 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1115 and dregs.C 63 shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1116 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1117 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1118 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1119 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1120 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1121 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1122 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1123 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1124 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1125 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1126 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1127 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1128
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1129 1110001011MMMRRR lsr_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1130 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1131 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1132 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1133 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1134 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1135 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1136 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1137 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1138
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1139 m68k_fetch_dst_ea M R 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1140 lsr dst 1 dst
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1141 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1142 m68k_save_dst 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1143 m68k_prefetch
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1144
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1145 1110CCC0ZZ000RRR asri
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1146 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1147 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1148 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1149 meta shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1150 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1151 meta shift C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1152 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1153 asr dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1154 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1155 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1156 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1157 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1158 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1159 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1160 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1161 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1162 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1163 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1164 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1165 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1166
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1167 1110CCC0ZZ100RRR asr_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1168 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1169 local shift 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1170 local shift_cycles 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1171 and dregs.C 63 shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1172 shift_cycles = shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1173 if shift = 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1174 cmp 0 dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1175 update_flags NZV0C0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1176 else
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1177 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1178 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1179 if shift >=U 9
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1180 shift = 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1181 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1182 case 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1183 if shift >=U 17
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1184 shift = 16
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1185 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1186 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1187 if shift >=U 33
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1188 shift = 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1189 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1190 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1191 asr dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1192 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1193 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1194 shift_cycles += shift_cycles
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1195 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1196 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1197 shift_cycles += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1198 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1199 shift_cycles += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1200 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1201 cycles shift_cycles
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1202 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1203 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1204
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1205 1110000011MMMRRR asr_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1206 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1207 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1208 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1209 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1210 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1211 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1212 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1213 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1214
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1215 m68k_fetch_dst_ea M R 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1216 asr dst 1 dst
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1217 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1218 m68k_save_dst 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1219 m68k_prefetch
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1220
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1221 1110CCC1ZZ001RRR lsli
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1222 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1223 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1224 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1225 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1226 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1227 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1228 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1229 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1230 update_flags XNZV0C
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1231 local cyc 32
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1232 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1233 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1234 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1235 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1236 default
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1237 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1238 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1239 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1240 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1241 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1242
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1243 1110CCC1ZZ101RRR lsl_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1244 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1245 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1246 and dregs.C 63 shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1247 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1248 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1249 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1250 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1251 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1252 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1253 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1254 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1255 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1256 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1257 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1258 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1259
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1260 1110001111MMMRRR lsl_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1261 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1262 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1263 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1264 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1265 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1266 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1267 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1268 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1269
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1270 m68k_fetch_dst_ea M R 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1271 lsl dst 1 dst
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1272 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1273 m68k_save_dst 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1274 m68k_prefetch
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1275
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1276 1110CCC1ZZ000RRR asli
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1277 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1278 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1279 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1280 meta shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1281 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1282 meta shift C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1283 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1284 lsl dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1285 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1286 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1287 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1288 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1289 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1290 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1291 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1292 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1293 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1294 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1295 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1296 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1297
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1298 1110CCC1ZZ100RRR asl_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1299 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1300 local shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1301 and dregs.C 63 shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1302 lsl dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1303 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1304 add shift shift shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1305 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1306 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1307 add 4 shift shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1308 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1309 add 2 shift shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1310 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1311 cycles shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1312 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1313 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1314
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1315 1110000111MMMRRR asl_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1316 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1317 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1318 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1319 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1320 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1321 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1322 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1323 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1324
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1325 m68k_fetch_dst_ea M R 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1326 lsl dst 1 dst
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1327 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1328 m68k_save_dst 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1329 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1330
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1331 00ZZRRRMMMEEESSS move
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1332 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1333 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1334 invalid M 7 #not actually invalid, but will be handled separately due to DSL limitations
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1335 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1336 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1337 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1338 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1339 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1340 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1341 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1342 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1343 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1344 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1345 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1346 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1347 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1348 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1349 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1350
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1351 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1352 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1353 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1354 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1355 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1356
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1357 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1358 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1359
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1360 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1361 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1362 mov src dregs.R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1363
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1364 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1365 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1366 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1367 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1368
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1369 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1370 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1371 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1372 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1373 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1374 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1375 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1376 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1377 addsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1378 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1379 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1380 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1381 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1382 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1383
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1384 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1385 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1386 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1387 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1388 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1389 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1390 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1391 decsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1392 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1393 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1394 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1395 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1396 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1397 m68k_write_size size 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1398
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1399 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1400 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1401 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1402 add aregs.R scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1403 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1404 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1405
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1406 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1407 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1408 add aregs.R scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1409 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1410 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1411 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1412 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1413
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1414
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1415 00ZZ00M111EEESSS move_abs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1416 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1417 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1418 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1419 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1420 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1421 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1422 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1423 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1424 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1425 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1426 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1427 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1428 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1429 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1430 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1431 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1432
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1433 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1434 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1435 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1436 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1437 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1438
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1439 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1440 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1441
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1442 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1443 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1444 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1445 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1446
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1447 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1448 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1449 lsl prefetch 16 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1450 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1451 or prefetch scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1452 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1453 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1454 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1455 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1456
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1457 00ZZRRR001EEESSS movea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1458 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1459 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1460 invalid Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1461 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1462 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1463 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1464 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1465 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1466 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1467 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1468 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1469 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1470 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1471 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1472 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1473 mov src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1474 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1475 sext 32 src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1476 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1477 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1478
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1479 0100010011MMMRRR move_to_ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1480 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1481 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1482 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1483 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1484 m68k_fetch_src_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1485 mov scratch1 ccr
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1486 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1487 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1488
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1489 0100011011MMMRRR move_to_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1490 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1491 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1492 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1493 invalid M 7 R 7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
1494 #TODO: privilege violation exception if in user mode
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1495 m68k_fetch_src_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1496 mov scratch1 ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1497 lsr scratch1 8 status
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1498 update_sync
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1499 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1500 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1501
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1502 0100000011MMMRRR move_from_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1503 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1504 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1505 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1506 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1507 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1508 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1509 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1510 m68k_fetch_dst_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1511 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1512 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1513 mov scratch1 dst
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1514 if M
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1515 cycles 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1516 else
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1517 cycles 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1518 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1519 m68k_save_dst 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1520 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1521
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1522 01000000ZZMMMRRR negx
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1523 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1524 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1525 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1526 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1527 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1528 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1529 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1530 m68k_fetch_dst_ea M R Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1531 sbc dst 0 dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1532 update_flags XNZVC
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1533 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1534 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1535 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1536 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1537 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1538 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1539 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1540
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1541 01000010ZZMMMRRR clr
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1542 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1543 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1544 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1545 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1546 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1547 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1548 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1549 invalid Z 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1550 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1551 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1552 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1553 #register clears have 2 cycle penalty for longword size
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1554 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1555 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1556 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1557 dst:Z = 0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1558 update_flags N0Z1V0C0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1559 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1560 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1561
2453
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1562 00001100ZZMMMRRR cmpi
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1563 local immed 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1564 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1565 invalid M 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1566 invalid M 7 R 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1567 invalid M 7 R 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1568 invalid M 7 R 4
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1569 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1570 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1571 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1572 #fetch immediate operand
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1573 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1574 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1575 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1576 immed = prefetch << 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1577 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1578 immed |= prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1579 if M = 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1580 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1581 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1582 default
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1583 immed = prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1584 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1585 #fetch dst EA
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1586 m68k_fetch_dst_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1587
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1588 cmp immed dst Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1589 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1590 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1591
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1592 1011DDD1ZZ001SSS cmpm
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1593 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1594 scratch1 = aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1595 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1596 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1597 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1598 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1599 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1600 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1601 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1602 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1603 scratch2 = scratch1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1604 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1605 addsize Z aregs.S aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1606 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1607 if S = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1608 aregs.S += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1609 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1610 aregs.S += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1611 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1612 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1613 scratch1 = aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1614 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1615 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1616 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1617 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1618 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1619 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1620 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1621 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1622 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1623 addsize Z aregs.D aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1624 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1625 if D = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1626 aregs.D += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1627 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1628 aregs.D += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1629 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1630 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1631 cmp scratch2 scratch1 Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1632 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1633 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1634
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1635 1011DDD0ZZMMMRRR cmp
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1636 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1637 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1638 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1639 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1640 m68k_fetch_src_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1641
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1642 if Z = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1643 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1644 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1645
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1646 cmp src dregs.D Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1647 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1648 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1649
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1650 1011DDDZ11MMMRRR cmpa
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1651 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1652 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1653 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1654 local size 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1655 local ext_src 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1656 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1657 size = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1658 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1659 size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1660 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1661 m68k_fetch_src_ea M R size
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1662 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1663 if size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1664 sext 32 src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1665 meta src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1666 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1667 cmp src aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1668 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1669 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1670
2454
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1671 0000100000MMMRRR btsti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1672 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1673 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1674 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1675 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1676
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1677 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1678 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1679 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1680 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1681 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1682 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1683 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1684 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1685 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1686 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1687 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1688 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1689 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1690 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1691 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1692
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1693 0000100001MMMRRR bchgi
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1694 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1695 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1696 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1697 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1698 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1699 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1700 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1701
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1702 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1703 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1704 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1705 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1706 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1707 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1708 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1709 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1710 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1711 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1712 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1713 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1714 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1715 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1716 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1717 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1718 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1719 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1720 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1721 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1722 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1723 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1724
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1725 0000100010MMMRRR bclri
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1726 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1727 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1728 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1729 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1730 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1731 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1732 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1733
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1734 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1735 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1736 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1737 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1738 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1739 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1740 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1741 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1742 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1743 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1744 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1745 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1746 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1747 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1748 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1749 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1750 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1751 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1752 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1753 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1754 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1755 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1756 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1757
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1758 0000100011MMMRRR bseti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1759 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1760 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1761 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1762 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1763 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1764 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1765 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1766
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1767 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1768 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1769 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1770 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1771 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1772 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1773 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1774 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1775 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1776 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1777 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1778 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1779 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1780 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1781 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1782 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1783 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1784 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1785 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1786 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1787 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1788 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1789
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1790 0000SSS100MMMRRR btst_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1791 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1792 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1793 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1794 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1795
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1796 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1797 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1798 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1799 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1800 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1801 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1802 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1803 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1804 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1805 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1806 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1807 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1808 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1809 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1810
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1811 0000SSS101MMMRRR bchg_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1812 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1813 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1814 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1815 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1816 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1817 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1818 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1819
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1820 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1821 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1822 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1823 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1824 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1825 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1826 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1827 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1828 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1829 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1830 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1831 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1832 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1833 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1834 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1835 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1836 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1837 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1838 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1839 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1840 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1841
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1842 0000SSS110MMMRRR bclr_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1843 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1844 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1845 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1846 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1847 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1848 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1849 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1850
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1851 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1852 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1853 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1854 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1855 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1856 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1857 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1858 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1859 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1860 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1861 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1862 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1863 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1864 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1865 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1866 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1867 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1868 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1869 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1870 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1871 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1872 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1873
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1874 0000SSS111MMMRRR bset_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1875 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1876 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1877 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1878 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1879 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1880 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1881 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1882
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1883 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1884 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1885 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1886 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1887 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1888 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1889 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1890 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1891 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1892 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1893 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1894 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1895 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1896 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1897 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1898 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1899 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1900 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1901 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1902 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1903 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1904
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1905 0000DDD10Z001AAA movep_ay_dx
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1906 local address 32
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1907 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1908 scratch1 += aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1909 address = scratch1 + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1910 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1911 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1912 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1913 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1914 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1915 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1916 address += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1917 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1918 dregs.D <<= 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1919 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1920 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1921 scratch1 = address + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1922 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1923 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1924 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1925 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1926
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1927 0000DDD11Z001AAA movep_dx_ay
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1928 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1929 scratch2 = scratch1 + aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1930 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1931 scratch1 = dregs.D >> 24
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1932 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1933 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1934 scratch1 = dregs.D >> 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1935 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1936 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1937 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1938 scratch1 = dregs.D >> 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1939 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1940 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1941 scratch1 = dregs.D
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1942 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1943 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
1944
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1945 01000100ZZMMMRRR neg
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1946 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1947 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1948 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1949 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1950 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1951 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1952 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1953 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1954
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1955 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1956 dst:Z = -dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1957 update_flags XNZVC
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1958 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1959 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1960 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1961 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1962 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1963 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1964 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1965
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1966 01000110ZZMMMRRR not
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1967 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1968 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1969 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1970 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1971 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1972 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1973 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1974 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1975
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1976 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1977 dst:Z = ~dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1978 update_flags NZV0C0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1979 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1980 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1981 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1982 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1983 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1984 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1985 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1986
2468
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1987 01001000ZZ000RRR ext
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1988 invalid Z 0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1989 invalid Z 1
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1990 if Z = 3
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1991 meta bits 32
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1992 else
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1993 meta bits 16
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1994 end
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1995 sext bits dregs.R dregs.R
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1996 update_flags NZV0C0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1997 m68k_prefetch
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
1998
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
1999 010011100100VVVV trap
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2000 local vector 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2001 scratch1 = pc
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2002 vector = V + 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2003 m68k_trap vector
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2004
2470
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2005 0100111001010RRR link
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2006 a7 -= 4
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2007 scratch2 = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2008 #TODO: confirm order of fetch and write
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2009 m68k_write32 aregs.R
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2010 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2011 aregs.R = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2012 sext 32 scratch1 scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2013 a7 += scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2014 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2015
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2016 0100111001011RRR unlk
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2017 a7 = aregs.R
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2018 scratch1 = a7
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2019 m68k_read32
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2020 a7 += 4
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2021 aregs.R = scratch1
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2022 m68k_prefetch
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2023
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2024 0100100001000RRR swap
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2025 ror dregs.R 16 dregs.R
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2026 update_flags NZV0C0
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2027 m68k_prefetch
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2028
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2029 m68k_calc_ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2030 arg mode 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2031 arg reg 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2032 arg index_penalty 32
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2033
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2034 switch mode
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2035 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2036 #address reg indirect
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2037 meta ea aregs.reg
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2038 case 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2039 #postincrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2040 meta ea aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2041 case 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2042 #predecrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2043 #note: this case is only used when m68k_calc_ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2044 #is called from movem_reg_to_mem which does its own decrementing
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2045 meta ea aregs.reg
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2046 case 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2047 #displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2048 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2049 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2050 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2051 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2052 case 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2053 #index
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2054 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2055 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2056 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2057 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2058 case 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2059 switch reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2060 case 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2061 #absolute short
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2062 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2063 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2064 case 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2065 #absoltue long
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2066 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2067 scratch2 = prefetch << 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2068 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2069 scratch1 = scratch2 | prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2070 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2071 #pc displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2072 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2073 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2074 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2075 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2076 case 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2077 #pc indexed
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2078 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2079 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2080 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2081 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2082 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2083 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2084 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2085
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2086 0100100001MMMRRR pea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2087 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2088 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2089 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2090 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2091 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2092 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2093 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2094 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2095
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2096 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2097 scratch2 = a7 - 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2098 m68k_write32_lowfirst ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2099 a7 -= 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2100
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2101 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2102
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2103 0100DDD111MMMRRR lea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2104 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2105 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2106 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2107 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2108 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2109 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2110 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2111 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2112
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2113 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2114 aregs.D = ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2115
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2116 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2117
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2118 01001010ZZMMMRRR tst
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2119 invalid M 7 R 5
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2120 invalid M 7 R 6
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2121 invalid M 7 R 7
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2122
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2123 m68k_fetch_dst_ea M R Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2124
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2125 cmp 0 dst Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2126 update_flags NZV0C0
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2127 m68k_prefetch
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2128
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2129 0100111001110000 reset
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2130 if reset_handler
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2131 pcall reset_handler m68k_reset_handler context
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2132 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2133 cycles 128
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2134 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2135
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2136 0100111001110001 nop
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2137 m68k_prefetch
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2138
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2139 0100111001110011 rte
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2140 #TODO: privilege violation exception if in user mode
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2141 #Read saved SR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2142 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2143 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2144 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2145 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2146 status = scratch1 >> 8
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2147 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2148 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2149 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2150 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2151 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2152
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2153 check_user_mode_swap_ssp_usp
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2154 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2155 update_sync
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2156 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2157
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2158 0100111001110101 m68k_rts
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2159 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2160 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2161 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2162 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2163
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2164 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2165 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2166
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2167 0100111001110111 rtr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2168 #Read saved CCR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2169 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2170 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2171 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2172 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2173 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2174 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2175 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2176 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2177 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2178
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2179 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2180 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2181
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2182 0100111010MMMRRR jsr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2183 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2184 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2185 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2186 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2187 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2188 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2189 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2190 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2191
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2192 a7 -= 4
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2193 scratch2 = a7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2194 m68k_write32 pc
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2195
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2196 m68k_calc_ea M R 2
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2197 pc = ea
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2198
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2199 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2200 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2201
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2202 0100111011MMMRRR jmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2203 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2204 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2205 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2206 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2207 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2208 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2209 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2210 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2211
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2212 m68k_calc_ea M R 2
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2213 pc = ea
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2214
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2215 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2216 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2217
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2218 m68k_movem_reg_to_mem
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2219 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2220 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2221 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2222 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2223
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2224 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2225 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2226 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2227 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2228 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2229 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2230 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2231
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2232 m68k_movem_reg_to_mem_dec
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2233 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2234 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2235 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2236 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2237
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2238 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2239 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2240 decsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2241 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2242 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2243 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2244 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2245
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2246
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2247 010010001ZMMMRRR movem_reg_to_mem
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2248 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2249 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2250 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2251 invalid M 7 R 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2252 invalid M 7 R 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2253 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2254 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2255 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2256 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2257 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2258 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2259 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2260 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2261
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2262 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2263 reglist = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2264
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2265 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2266 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2267 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2268 if M = 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2269 m68k_movem_reg_to_mem_dec reglist 1 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2270 m68k_movem_reg_to_mem_dec reglist 2 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2271 m68k_movem_reg_to_mem_dec reglist 4 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2272 m68k_movem_reg_to_mem_dec reglist 8 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2273 m68k_movem_reg_to_mem_dec reglist 16 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2274 m68k_movem_reg_to_mem_dec reglist 32 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2275 m68k_movem_reg_to_mem_dec reglist 64 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2276 m68k_movem_reg_to_mem_dec reglist 128 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2277 m68k_movem_reg_to_mem_dec reglist 256 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2278 m68k_movem_reg_to_mem_dec reglist 512 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2279 m68k_movem_reg_to_mem_dec reglist 1024 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2280 m68k_movem_reg_to_mem_dec reglist 2048 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2281 m68k_movem_reg_to_mem_dec reglist 4096 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2282 m68k_movem_reg_to_mem_dec reglist 8192 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2283 m68k_movem_reg_to_mem_dec reglist 16384 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2284 m68k_movem_reg_to_mem_dec reglist 32768 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2285 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2286 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2287 m68k_movem_reg_to_mem reglist 1 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2288 m68k_movem_reg_to_mem reglist 2 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2289 m68k_movem_reg_to_mem reglist 4 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2290 m68k_movem_reg_to_mem reglist 8 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2291 m68k_movem_reg_to_mem reglist 16 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2292 m68k_movem_reg_to_mem reglist 32 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2293 m68k_movem_reg_to_mem reglist 64 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2294 m68k_movem_reg_to_mem reglist 128 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2295 m68k_movem_reg_to_mem reglist 256 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2296 m68k_movem_reg_to_mem reglist 512 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2297 m68k_movem_reg_to_mem reglist 1024 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2298 m68k_movem_reg_to_mem reglist 2048 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2299 m68k_movem_reg_to_mem reglist 4096 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2300 m68k_movem_reg_to_mem reglist 8192 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2301 m68k_movem_reg_to_mem reglist 16384 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2302 m68k_movem_reg_to_mem reglist 32768 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2303 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2304 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2305
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2306 m68k_movem_mem_to_dreg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2307 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2308 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2309 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2310 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2311
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2312 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2313 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2314 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2315 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2316 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2317 sext 32 scratch1 dregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2318 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2319 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2320 dregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2321 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2322 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2323 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2324
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2325 m68k_movem_mem_to_areg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2326 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2327 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2328 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2329 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2330
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2331 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2332 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2333 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2334 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2335 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2336 sext 32 scratch1 aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2337 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2338 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2339 aregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2340 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2341 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2342 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2343
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2344 010011001ZMMMRRR movem_mem_to_reg
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2345 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2346 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2347 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2348 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2349 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2350 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2351 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2352 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2353 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2354 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2355 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2356
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2357 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2358 reglist = scratch1
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2359
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2360 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2361 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2362 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2363
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2364 m68k_movem_mem_to_dreg reglist 1 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2365 m68k_movem_mem_to_dreg reglist 2 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2366 m68k_movem_mem_to_dreg reglist 4 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2367 m68k_movem_mem_to_dreg reglist 8 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2368 m68k_movem_mem_to_dreg reglist 16 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2369 m68k_movem_mem_to_dreg reglist 32 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2370 m68k_movem_mem_to_dreg reglist 64 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2371 m68k_movem_mem_to_dreg reglist 128 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2372 m68k_movem_mem_to_areg reglist 256 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2373 m68k_movem_mem_to_areg reglist 512 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2374 m68k_movem_mem_to_areg reglist 1024 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2375 m68k_movem_mem_to_areg reglist 2048 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2376 m68k_movem_mem_to_areg reglist 4096 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2377 m68k_movem_mem_to_areg reglist 8192 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2378 m68k_movem_mem_to_areg reglist 16384 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2379 m68k_movem_mem_to_areg reglist 32768 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2380 #dummy read
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2381 scratch1 = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2382 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2383 if M = 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2384 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2385 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2386
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2387 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2388
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2389 0100111001100RRR move_to_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2390 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2391 other_sp = aregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2392 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2393
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2394 0100111001101RRR move_from_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2395 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2396 aregs.R = other_sp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2397 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2398
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2399 0111RRR0IIIIIIII moveq
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2400 local tmp 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2401 sext 16 I tmp
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2402 sext 32 tmp dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2403 cmp 0 dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2404 update_flags NZV0C0
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2405 m68k_prefetch
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2406
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2407 0110000100000000 bsr_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2408 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2409 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2410 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2411 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2412 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2413
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2414 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2415 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2416 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2417
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2418 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2419 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2420
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2421 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2422 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2423
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2424
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2425 01100001DDDDDDDD bsr
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2426 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2427 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2428 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2429 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2430 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2431
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2432 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2433 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2434 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2435
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2436 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2437
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2438 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2439 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2440
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2441 m68k_check_cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2442 arg cond 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2443 local invert 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2444 switch cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2445 case 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2446 #true
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2447 meta istrue 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2448 case 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2449 #false
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2450 meta istrue 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2451 case 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2452 #high
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2453 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2454 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2455 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2456 case 3
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2457 #low or same
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2458 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2459 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2460 case 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2461 #carry clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2462 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2463 invert = !cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2464 case 5
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2465 #carry set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2466 meta istrue cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2467 case 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2468 #not equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2469 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2470 invert = !zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2471 case 7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2472 #equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2473 meta istrue zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2474 case 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2475 #overflow clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2476 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2477 invert = !vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2478 case 9
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2479 #overflow set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2480 meta istrue vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2481 case 10
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2482 #plus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2483 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2484 invert = !nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2485 case 11
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2486 #minus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2487 meta istrue nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2488 case 12
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2489 #greater or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2490 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2491 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2492 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2493 case 13
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2494 #less
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2495 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2496 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2497 case 14
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2498 #greater
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2499 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2500 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2501 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2502 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2503 case 15
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2504 #less or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2505 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2506 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2507 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2508 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2509
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2510 0110CCCC00000000 bcc_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2511 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2512 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2513 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2514 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2515 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2516 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2517
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2518 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2519 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2520 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2521 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2522 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2523 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2524 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2525 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2526
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2527 0110CCCCDDDDDDDD bcc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2528 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2529 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2530 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2531 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2532 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2533 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2534 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2535
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2536 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2537
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2538 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2539 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2540 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2541 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2542 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2543
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2544 0101CCCC11001RRR dbcc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2545 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2546 local tmp 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2547 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2548 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2549 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2550 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2551 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2552 dregs.R:1 -= 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2553 tmp = dregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2554 if tmp = 65535
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2555 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2556 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2557 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2558 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2559 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2560 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2561 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2562 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2563 m68k_prefetch
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2564
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2565 1110CCC0ZZ011RRR rori
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2566 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2567 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2568 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2569 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2570 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2571 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2572 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2573 ror dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2574 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2575 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2576 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2577 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2578 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2579 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2580 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2581 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2582 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2583 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2584 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2585 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2586
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2587 1110CCC0ZZ111RRR ror_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2588 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2589 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2590 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2591 ror dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2592 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2593 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2594 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2595 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2596 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2597 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2598 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2599 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2600 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2601 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2602 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2603
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2604 1110011011MMMRRR ror_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2605 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2606 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2607 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2608 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2609 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2610 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2611 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2612 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2613
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2614 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2615 ror dst 1 dst 1
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2616 update_flags NZV0C
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2617 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2618 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2619
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2620 1110CCC1ZZ011RRR roli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2621 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2622 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2623 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2624 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2625 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2626 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2627 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2628 rol dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2629 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2630 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2631 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2632 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2633 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2634 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2635 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2636 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2637 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2638 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2639 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2640 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2641
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2642 1110CCC1ZZ111RRR rol_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2643 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2644 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2645 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2646 rol dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2647 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2648 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2649 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2650 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2651 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2652 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2653 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2654 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2655 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2656 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2657 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2658
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2659 1110011111MMMRRR rol_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2660 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2661 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2662 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2663 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2664 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2665 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2666 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2667 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2668
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2669 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2670 rol dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2671 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2672 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2673 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2674
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2675 1110CCC0ZZ010RRR roxri
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2676 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2677 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2678 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2679 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2680 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2681 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2682 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2683 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2684 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2685 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2686 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2687 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2688 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2689 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2690 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2691 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2692 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2693 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2694 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2695 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2696
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2697 1110CCC0ZZ110RRR roxr_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2698 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2699 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2700 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2701 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2702 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2703 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2704 if cycle_shift = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2705 rrc dregs.R 31 dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2706 rrc dregs.R 1 dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2707 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2708 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2709 shift = dregs.C & 31
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2710 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2711 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2712 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2713 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2714 shift = dregs.C & 31
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2715 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2716 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2717 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2718 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2719 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2720 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2721 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2722 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2723 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2724 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2725 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2726 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2727 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2728
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2729 1110010011MMMRRR roxr_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2730 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2731 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2732 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2733 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2734 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2735 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2736 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2737 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2738
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2739 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2740 rrc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2741 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2742 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2743 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2744
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2745 1110CCC1ZZ010RRR roxli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2746 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2747 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2748 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2749 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2750 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2751 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2752 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2753 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2754 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2755 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2756 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2757 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2758 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2759 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2760 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2761 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2762 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2763 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2764 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2765 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2766
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2767 1110CCC1ZZ110RRR roxl_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2768 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2769 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2770 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2771 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2772 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2773 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2774 if cycle_shift = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2775 rrc dregs.R 31 dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2776 rlc dregs.R 1 dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2777 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2778 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2779 shift = dregs.C & 31
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2780 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2781 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2782 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2783 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2784 shift = dregs.C & 31
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2785 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2786 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2787 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2788 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2789 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2790 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2791 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2792 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2793 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2794 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2795 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2796 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2797 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2798
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2799 1110010111MMMRRR roxl_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2800 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2801 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2802 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2803 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2804 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2805 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2806 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2807 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2808
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2809 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2810 rlc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2811 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2812 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2813 m68k_prefetch