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annotate runtime.S @ 217:acd29e2664c6

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Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
author Mike Pavone <pavone@retrodev.com>
date Sat, 20 Apr 2013 00:29:14 -0700
parents 922b59c09259
children 28a6697e847b
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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17
de0085d4ea40 Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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diff changeset
2 .global handle_cycle_limit
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
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3 .global do_sync
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4 handle_cycle_limit:
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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5 cmp 84(%rsi), %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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6 jb skip_sync
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3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
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7 do_sync:
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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8 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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9 mov %rsi, %rdi
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10 xor %esi, %esi
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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11 call sync_components
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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12 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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diff changeset
13 call m68k_load_context
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14 skip_sync:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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15 ret
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16
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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17 .global handle_cycle_limit_int
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18 handle_cycle_limit_int:
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19 cmp 88(%rsi), %eax
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20 jb skip_int
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21 /* swap USP and SSP if not already in supervisor mode */
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22 bt $5, 5(%rsi)
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23 jc already_supervisor
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24 mov 72(%rsi), %edi
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25 mov %r15d, 72(%rsi)
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26 mov %edi, %r15d
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27 already_supervisor:
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7504200cac86 Fix order of SR and PC saved in an exception stack frame
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28 /* save PC */
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29 sub $4, %r15d
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30 mov %r15d, %edi
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31 call m68k_write_long_lowfirst
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32 /* save status register on stack */
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33 sub $2, %r15d
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34 mov %r15d, %edi
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35 call get_sr
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36 call m68k_write_word
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37 /* update status register */
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38 andb $0xF8, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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39 mov 92(%rsi), %cl
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40 or $0x20, %cl
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41 or %cl, 5(%rsi)
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42 /* calculate interrupt vector address */
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43 mov 92(%rsi), %ecx
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44 shl $2, %ecx
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45 add $0x60, %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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46 call m68k_read_long_scratch1
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47 call m68k_native_addr_and_sync
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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48 add $24, %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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49 /* discard function return address */
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50 pop %rdi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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51 jmp *%rcx
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52 ret
82
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53 skip_int:
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3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
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54 cmp 84(%rsi), %eax
198
209a37eed3e7 Add support for breaking into the debugger while game is running
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55 jb skip_sync_int
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56 call m68k_save_context
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57 mov %rsi, %rdi
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58 mov %ecx, %esi
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59 call sync_components
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60 mov %rax, %rsi
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61 call m68k_load_context
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62 skip_sync_int:
82
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63 ret
87
60b5c9e2f4e0 vertical interrupts now work
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64
152
79958b95526f Implement TRAP (untested)
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65 .global m68k_trap
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66 m68k_trap:
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67 push %rdi
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68 push %rcx
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69 /* swap USP and SSP if not already in supervisor mode */
79958b95526f Implement TRAP (untested)
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70 bt $5, 5(%rsi)
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71 jc already_supervisor_trap
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72 mov 72(%rsi), %edi
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73 mov %r15d, 72(%rsi)
79958b95526f Implement TRAP (untested)
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74 mov %edi, %r15d
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75 already_supervisor_trap:
175
7504200cac86 Fix order of SR and PC saved in an exception stack frame
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76 /* save PC */
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77 sub $4, %r15d
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78 mov %r15d, %edi
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79 pop %rcx
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80 call m68k_write_long_lowfirst
152
79958b95526f Implement TRAP (untested)
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81 /* save status register on stack */
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82 sub $2, %r15d
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83 mov %r15d, %edi
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84 call get_sr
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85 call m68k_write_word
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86 /* update status register */
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87 andb $0xF8, 5(%rsi)
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88 mov 92(%rsi), %cl
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89 or $0x20, %cl
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90 or %cl, 5(%rsi)
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91 /* calculate interrupt vector address */
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92 pop %rcx
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93 shl $2, %ecx
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94 add $0x80, %ecx
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95 call m68k_read_long_scratch1
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96 call m68k_native_addr_and_sync
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97 add $24, %eax
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98 jmp *%rcx
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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99
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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100 invalid_msg:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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101 .asciz "Invalid instruction at %X\n"
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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102
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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103 .global m68k_invalid
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104 m68k_invalid:
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105 lea invalid_msg(%rip), %rdi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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106 mov %ecx, %esi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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107 xor %rax, %rax
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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108 call printf
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
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109 mov $1, %rdi
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110 call exit
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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111
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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112 .global bcd_add
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113 bcd_add:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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114 xchg %rax, %rdi
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115
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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116 mov %cl, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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117 mov %al, %ah
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118 and $0xF, %ch
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119 and $0xF, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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120 and $0xF0, %cl
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121 and $0xF0, %al
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122 add %ah, %ch
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123 cmp $10, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
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124 jb no_adjust
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
125 add $6, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
126 no_adjust:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
127 add %ch, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
128 add %al, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
129 mov $0, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
130 jc def_adjust
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
131 cmp $0xA0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
132 jb no_adjust_h
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
133 def_adjust:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
134 add $0x60, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
135 mov $1, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
136 no_adjust_h:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
137
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
138 mov %rdi, %rax
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
139 ret
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
140
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
141 .global bcd_sub
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
142 bcd_sub:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
143 xchg %rax, %rdi
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
144
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
145 mov %cl, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
146 mov %al, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
147 and $0xF, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
148 and $0xF, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
149 and $0xF0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
150 and $0xF0, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
151 sub %ah, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
152 cmp $10, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
153 jb no_adjusts
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
154 sub $6, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
155 no_adjusts:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
156 add %ch, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
157 sub %al, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
158 mov $0, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
159 jc def_adjusts
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
160 cmp $0xA0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
161 jb no_adjust_hs
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
162 def_adjusts:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
163 sub $0x60, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
164 mov $1, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
165 no_adjust_hs:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
166
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
167 mov %rdi, %rax
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
168 ret
150
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents: 149
diff changeset
169
87
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
170 int_dbg_msg:
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
171 .asciz "Executing Interrupt!"
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
172 print_int_dbg:
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
173 call m68k_save_context
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
174 push %rsi
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
175 lea int_dbg_msg(%rip), %rdi
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
176 call puts
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
177 pop %rsi
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
178 call m68k_load_context
60b5c9e2f4e0 vertical interrupts now work
Mike Pavone <pavone@retrodev.com>
parents: 86
diff changeset
179 ret
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
180
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
181 .global get_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
182 get_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
183 mov 5(%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
184 shl $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
185 mov (%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
186 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
187 or %bl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
188 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
189 or %dl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
190 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
191 or %bh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
192 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
193 or %dh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
194 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
195
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
196 .global set_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
197 set_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
198 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
199 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
200 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
201 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
202 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
203 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
204 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
205 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
206 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
207 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
208 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
209 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
210 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
211 mov %cl, (%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
212 shr $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
213 mov %cl, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
214 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
215
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
216 .global set_ccr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
217 set_ccr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
218 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
219 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
220 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
221 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
222 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
223 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
224 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
225 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
226 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
227 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
228 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
229 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
230 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
231 mov %cl, (%rsi)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
232 ret
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
233
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
234 do_vdp_port_write:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
235 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
236 mov %rcx, %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
237 call vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
238 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
239 call m68k_load_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
240 ret
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
241
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
242 do_vdp_port_read:
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
243 mov %ecx, %edi
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
244 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
245 call vdp_port_read
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
246 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
247 call m68k_load_context
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
248 mov 136(%rsi), %cx
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
249 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
250
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
251 do_io_write:
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
252 call m68k_save_context
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
253 and $0x1FFFF, %edi
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
254 mov %ecx, %edx
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
255 call io_write
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
256 mov %rax, %rsi
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
257 call m68k_load_context
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
258 ret
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
259 do_io_read:
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
260 mov %ecx, %edi
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
261 and $0x1FFFF, %edi
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
262 call m68k_save_context
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
263 call io_read
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
264 mov %rax, %rsi
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
265 call m68k_load_context
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
266 mov 136(%rsi), %cl
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
267 ret
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
268
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
269 do_io_write_w:
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
270 call m68k_save_context
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
271 and $0x1FFFF, %edi
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
272 mov %ecx, %edx
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
273 call io_write_w
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
274 mov %rax, %rsi
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
275 call m68k_load_context
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
276 ret
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
277 do_io_read_w:
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
278 mov %ecx, %edi
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
279 and $0x1FFFF, %edi
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
280 call m68k_save_context
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
281 call io_read_w
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
282 mov %rax, %rsi
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
283 call m68k_load_context
84
2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents: 83
diff changeset
284 mov 136(%rsi), %cx
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
285 ret
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
286
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
287 bad_access_msg:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
288 .asciz "Program tried to access illegal 68K address %X\n"
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
289
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
290 .global m68k_write_word
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
291 .global try_fifo_write
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
292 m68k_write_word:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
293 call inccycles
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
294 and $0xFFFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
295 cmp $0x400000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
296 jbe cart_w
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
297 cmp $0xE00000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
298 jae workram_w
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
299 cmp $0xC00000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
300 jae vdp_psg_w
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
301 cmp $0xA00000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
302 jb not_io_w
85
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents: 84
diff changeset
303 cmp $0xA12000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
304 jae not_io_w
85
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents: 84
diff changeset
305 jmp do_io_write_w
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents: 84
diff changeset
306 not_io_w:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
307 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
308 workram_w:
193
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
309 and $0xFFFF, %edi
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
310 mov %cx, (%r9, %rdi)
193
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
311 mov %edi, %ecx
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
312 shr $10, %ecx
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
313 bt %ecx, 160(%rsi)
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
314 jnc not_code
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
315 call m68k_save_context
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
316 call m68k_handle_code_write
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
317 mov %rax, %rsi
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
318 call m68k_load_context
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
319 not_code:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
320 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
321 cart_w:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
322 mov %cx, (%r8, %rdi)
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
323 ret
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
324 vdp_psg_w:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
325 test $0x2700E0, %edi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
326 jnz crash
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
327 and $0x1F, %edi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
328 cmp $4, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
329 jb try_fifo_write
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
330 jmp do_vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
331 try_fifo_write:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
332 push %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
333 push %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
334 /* fetch VDP context pointer from 68K context */
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
335 mov 128(%rsi), %rdx
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 145
diff changeset
336 /* check DMA flag */
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 145
diff changeset
337 bt $6, 19(%rdx)
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 145
diff changeset
338 jc fifo_fallback
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
339 /* get fifo_cur and compare it to fifo_end */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
340 mov (%rdx), %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
341 cmp %rbx, 8(%rdx)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
342 /* bail out if fifo is full */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
343 je fifo_fallback
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
344 /* populate FIFO entry */
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
345 mov %cx, 6(%rbx) /* value */
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
346 mov 16(%rdx), %cx
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
347 mov %cx, 4(%rbx) /* address */
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
348 mov 18(%rdx), %cl
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
349 mov %cl, 8(%rbx) /* cd */
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
350 movb $0, 9(%rbx) /* partial */
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
351 mov %eax, %ecx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
352 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
353 sub %eax, %ecx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
354 mov %ecx, (%rbx) /* cycle */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
355 /* update fifo_cur and store back in 68K context */
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
356 add $12, %rbx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
357 mov %rbx, (%rdx)
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
358 /* update address register */
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
359 movzbw 35(%rdx), %bx
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
360 add %bx, 16(%rdx)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
361 /* clear pending flag */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
362 andb $0xEF, 19(%rdx)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
363 pop %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
364 pop %rdx
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
365 ret
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
366 fifo_fallback:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
367 pop %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
368 pop %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
369 jmp do_vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
370 crash:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
371 mov %edi, %esi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
372 lea bad_access_msg(%rip), %rdi
160
69ac23d42897 Fix crash in printf from "crash" function due to lack of clearing rax
Mike Pavone <pavone@retrodev.com>
parents: 153
diff changeset
373 xor %rax, %rax
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
374 call printf
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
375 mov $1, %rdi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
376 call exit
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
377
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
378 .global m68k_write_byte
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
379 m68k_write_byte:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
380 call inccycles
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
381 and $0xFFFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
382 cmp $0x400000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
383 jbe cart_wb
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
384 cmp $0xE00000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
385 jae workram_wb
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
386 cmp $0xC00000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
387 jae vdp_psg_wb
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
388 cmp $0xA00000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
389 jb not_io_wb
85
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents: 84
diff changeset
390 cmp $0xA12000, %edi
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
391 jae not_io_wb
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
392 jmp do_io_write
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
393 not_io_wb:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
394 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
395 workram_wb:
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
396 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
397 xor $1, %edi
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
398 and $0xFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
399 mov %cl, (%r9, %rdi)
193
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
400 mov %edi, %ecx
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
401 shr $10, %ecx
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
402 bt %ecx, 160(%rsi)
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
403 jnc not_code_b
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
404 xor $1, %edi
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
405 call m68k_save_context
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
406 call m68k_handle_code_write
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
407 mov %rax, %rsi
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
408 call m68k_load_context
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
409 not_code_b:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
410 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
411 cart_wb:
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
412 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
413 xor $1, %edi
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
414 mov %cl, (%r8, %rdi)
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
415 ret
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
416 vdp_psg_wb:
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
417 push %rdx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
418 mov %cl, %dl
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
419 and $0xFF, %cx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
420 shl $8, %dx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
421 or %dx, %cx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
422 pop %rdx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
423 jmp vdp_psg_w
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
424
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
425 .global m68k_write_long_lowfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
426 m68k_write_long_lowfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
427 push %rdi
86
3d3966c254b2 RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents: 85
diff changeset
428 push %rcx
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
429 add $2, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
430 call m68k_write_word
86
3d3966c254b2 RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents: 85
diff changeset
431 pop %rcx
3d3966c254b2 RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents: 85
diff changeset
432 pop %rdi
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
433 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
434 jmp m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
435
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
436 .global m68k_write_long_highfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
437 m68k_write_long_highfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
438 push %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
439 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
440 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
441 call m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
442 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
443 pop %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
444 add $2, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
445 jmp m68k_write_word
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
446
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
447 inccycles:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
448 cmp %rbp, %rax
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
449 jnb do_limit
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
450 add $4, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
451 ret
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
452 do_limit:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
453 push %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
454 push %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
455 call handle_cycle_limit
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
456 pop %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
457 pop %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
458 add $4, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
459 ret
17
de0085d4ea40 Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
460
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
461 .global m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
462 m68k_read_word_scratch1:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
463 call inccycles
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
464 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
465 cmp $0x400000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
466 jbe cart
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
467 cmp $0xE00000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
468 jae workram
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
469 cmp $0xC00000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
470 jae vdp_psg
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
471 cmp $0xA00000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
472 jb not_io
85
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents: 84
diff changeset
473 cmp $0xA12000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
474 jae not_io
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
475 call do_io_read_w
72
7935cd64d5c8 Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
476 ret
7935cd64d5c8 Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
477 not_io:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
478 xor %cx, %cx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
479 dec %cx
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
480 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
481 workram:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
482 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
483 mov (%r9, %rcx), %cx
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
484 ret
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
485 vdp_psg:
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
486 test $0x2700E0, %ecx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
487 jnz crash
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
488 and $0x1F, %ecx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
489 jmp do_vdp_port_read
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
490 cart:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
491 mov (%r8, %rcx), %cx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
492 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
493
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
494 .global m68k_read_long_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
495 m68k_read_long_scratch1:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
496 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
497 call m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
498 mov %cx, %di
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
499 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
500 add $2, %ecx
84
2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents: 83
diff changeset
501 push %rdi
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
502 call m68k_read_word_scratch1
84
2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.
Mike Pavone <pavone@retrodev.com>
parents: 83
diff changeset
503 pop %rdi
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
504 and $0xFFFF, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
505 shl $16, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
506 or %edi, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
507 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
508
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
509 .global m68k_read_byte_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
510 m68k_read_byte_scratch1:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
511 call inccycles
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
512 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
513 cmp $0x400000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
514 jbe cart_b
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
515 cmp $0xE00000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
516 jae workram_b
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
517 cmp $0xC00000, %ecx
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
518 jae vdp_psg_b
153
42c031184e8a Implement access to Z80 RAM
Mike Pavone <pavone@retrodev.com>
parents: 152
diff changeset
519 cmp $0xA00000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
520 jb not_io_b
85
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation.
Mike Pavone <pavone@retrodev.com>
parents: 84
diff changeset
521 cmp $0xA12000, %ecx
104
a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
522 jae not_io_b
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
523 jmp do_io_read
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
524 not_io_b:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
525 xor %cl, %cl
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
526 dec %cl
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
527 ret
137
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
528 vdp_psg_b:
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
529 test $0x2700E0, %ecx
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
530 jnz crash
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
531 and $0x1F, %ecx
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
532 bt $0, %ecx
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
533 jnc vdp_swap
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
534 jmp do_vdp_port_read
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
535 vdp_swap:
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
536 call do_vdp_port_read
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
537 shr $8, %cx
0e7e1ccc0a81 Implemented HV counter
Mike Pavone <pavone@retrodev.com>
parents: 127
diff changeset
538 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
539 workram_b:
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
540 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
541 xor $1, %ecx
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
542 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
543 mov (%r9, %rcx), %cl
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
544 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
545 cart_b:
83
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
546 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers.
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
547 xor $1, %ecx
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
548 mov (%r8, %rcx), %cl
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
549 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
550
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
551 .global m68k_modified_ret_addr
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
552 m68k_modified_ret_addr:
145
15b8dce19cf4 Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents: 138
diff changeset
553 add $16, %rsp
15b8dce19cf4 Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents: 138
diff changeset
554 call m68k_native_addr
15b8dce19cf4 Implement m68k_modified_ret_addr
Mike Pavone <pavone@retrodev.com>
parents: 138
diff changeset
555 jmp *%rcx
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
556
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
557 dyn_addr_msg:
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
558 .asciz "Program needs dynamically calculated native address\n"
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
559
86
3d3966c254b2 RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents: 85
diff changeset
560 .global m68k_native_addr_and_sync
3d3966c254b2 RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents: 85
diff changeset
561 m68k_native_addr_and_sync:
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
562 call m68k_save_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
563 push %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
564 mov %rsi, %rdi
198
209a37eed3e7 Add support for breaking into the debugger while game is running
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
565 xor %esi, %esi
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
566 call sync_components
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
567 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
568 push %rax
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
569 mov %rax, %rdi
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
570 call get_native_address_trans
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
571 mov %rax, %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
572 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
573 call m68k_load_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
574 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
575
86
3d3966c254b2 RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents: 85
diff changeset
576 .global m68k_native_addr
3d3966c254b2 RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents: 85
diff changeset
577 m68k_native_addr:
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
578 call m68k_save_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
579 push %rsi
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
580 mov %rsi, %rdi
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
581 mov %ecx, %esi
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
582 call get_native_address_trans
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
583 mov %rax, %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
584 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
585 call m68k_load_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
586 ret
193
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
587
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
588 .global m68k_retrans_stub
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
589 m68k_retrans_stub:
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
590 call m68k_save_context
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
591 push %rsi
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
592 call m68k_retranslate_inst
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
593 pop %rsi
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
594 mov %rax, %rcx
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
595 call m68k_load_context
c66e4636f991 Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
596 jmp *%rcx
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
597
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
598 .global m68k_save_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
599 m68k_save_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
600 mov %bl, 1(%rsi) /* N Flag */
207
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 198
diff changeset
601 mov %dl, 2(%rsi) /* Z flag */
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 198
diff changeset
602 mov %bh, 3(%rsi) /* V flag */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
603 mov %dh, 4(%rsi) /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
604 mov %r10d, 8(%rsi) /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
605 mov %r11d, 12(%rsi) /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
606 mov %r12d, 16(%rsi) /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
607 mov %r13d, 40(%rsi) /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
608 mov %r14d, 44(%rsi) /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
609 mov %r15d, 68(%rsi) /* a7 */
72
7935cd64d5c8 Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
610 mov %eax, 80(%rsi) /* current cycle count */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
611 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
612
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
613 .global m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
614 m68k_load_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
615 mov 1(%rsi), %bl /* N Flag */
207
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 198
diff changeset
616 mov 2(%rsi), %dl /* Z flag */
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 198
diff changeset
617 mov 3(%rsi), %bh /* V flag */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
618 mov 4(%rsi), %dh /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
619 mov 8(%rsi), %r10d /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
620 mov 12(%rsi), %r11d /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
621 mov 16(%rsi), %r12d /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
622 mov 40(%rsi), %r13d /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
623 mov 44(%rsi), %r14d /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
624 mov 68(%rsi), %r15d /* a7 */
72
7935cd64d5c8 Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
625 mov 76(%rsi), %ebp /* target cycle count */
7935cd64d5c8 Implement word wide access to IO area
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
626 mov 80(%rsi), %eax /* current cycle count */
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
627 mov 96(%rsi), %r8d /* cartridge address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 72
diff changeset
628 mov 104(%rsi), %r9d /* work ram address */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
629 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
630
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
631 .global m68k_start_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
632 m68k_start_context:
208
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
633 push %rbp
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
634 push %r12
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
635 push %r13
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
636 push %r14
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
637 push %r15
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
638
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
639 call m68k_load_context
208
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
640 call *%rdi
209
922b59c09259 Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
641 call m68k_save_context
208
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
642
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
643 pop %r15
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
644 pop %r14
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
645 pop %r13
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
646 pop %r12
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
647 pop %rbp
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
648
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
649 ret