annotate m68k_util.c @ 2614:c5314c0779c2

Extended debug output in debug mode of new 68K core
author Michael Pavone <pavone@retrodev.com>
date Mon, 17 Feb 2025 23:40:14 -0800
parents 1c493b8c513b
children 620f30af9fdc
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1 #include <string.h>
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
3 void m68k_read_8(m68k_context *context)
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
4 {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
5 context->cycles += 4 * context->opts->gen.clock_divider;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
6 context->scratch1 = read_byte(context->scratch1, context->mem_pointers, &context->opts->gen, context);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
7 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
8
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
9 #ifdef DEBUG_DISASM
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
10 #include "68kinst.h"
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
11 static uint16_t debug_disasm_fetch(uint32_t address, void *vcontext)
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
12 {
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
13 m68k_context *context = vcontext;
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
14 return read_word(address, context->mem_pointers, &context->opts->gen, context);
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
15 }
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
16 #endif
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
17 void m68k_read_16(m68k_context *context)
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
18 {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
19 context->cycles += 4 * context->opts->gen.clock_divider;
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
20 #ifdef DEBUG_DISASM
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
21 uint32_t tmp = context->scratch1;
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
22 #endif
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
23 context->scratch1 = read_word(context->scratch1, context->mem_pointers, &context->opts->gen, context);
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
24 #ifdef DEBUG_DISASM
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
25 if (tmp == context->pc) {
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
26 m68kinst inst;
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
27 m68k_decode(debug_disasm_fetch, context, &inst, tmp);
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
28 static char disasm_buf[256];
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
29 m68k_disasm(&inst, disasm_buf);
2614
c5314c0779c2 Extended debug output in debug mode of new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2594
diff changeset
30 printf("Fetch %05X: %04X - %s, d0=%X, d1=%X, d2=%X, d3=%X, d4=%X, d6=%X, a7=%X, xflag=%d\n", tmp, context->scratch1, disasm_buf, context->dregs[0], context->dregs[1], context->dregs[2], context->dregs[3], context->dregs[4], context->dregs[6], context->aregs[7], context->xflag);
c5314c0779c2 Extended debug output in debug mode of new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2594
diff changeset
31 } else {
c5314c0779c2 Extended debug output in debug mode of new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2594
diff changeset
32 printf("Read %05X: %04X\n", tmp, context->scratch1);
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
33 }
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
34 #endif
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
35 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
36
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
37 void m68k_write_8(m68k_context *context)
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
38 {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
39 context->cycles += 4 * context->opts->gen.clock_divider;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
40 write_byte(context->scratch2, context->scratch1, context->mem_pointers, &context->opts->gen, context);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
41 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
42
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
43 void m68k_write_16(m68k_context *context)
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
44 {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
45 context->cycles += 4 * context->opts->gen.clock_divider;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
46 write_word(context->scratch2, context->scratch1, context->mem_pointers, &context->opts->gen, context);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
47 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
48
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
49 void m68k_sync_cycle(m68k_context *context, uint32_t target_cycle)
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
50 {
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
51 context->sync_cycle = target_cycle; //why?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
52 context->sync_components(context, 0);
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
53 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
54
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
55 static void divu(m68k_context *context, uint32_t dividend_reg, uint32_t divisor)
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
56 {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
57 uint32_t dividend = context->dregs[dividend_reg];
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
58 uint32_t divisor_shift = divisor << 16;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
59 uint16_t quotient = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
60 uint8_t force = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
61 uint16_t bit = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
62 uint32_t cycles = 2;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
63 if (divisor_shift < dividend) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
64 context->nflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
65 context->zflag = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
66 context->vflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
67 context->cycles += 6 * context->opts->gen.clock_divider;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
68 return;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
69 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
70 for (int i = 0; i < 16; i++)
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
71 {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
72 force = dividend >> 31;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
73 quotient = quotient << 1 | bit;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
74 dividend = dividend << 1;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
75
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
76 if (force || dividend >= divisor_shift) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
77 dividend -= divisor_shift;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
78 cycles += force ? 4 : 6;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
79 bit = 1;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
80 } else {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
81 bit = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
82 cycles += 8;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
83 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
84 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
85 cycles += force ? 6 : bit ? 4 : 2;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
86 context->cycles += cycles * context->opts->gen.clock_divider;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
87 quotient = quotient << 1 | bit;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
88 context->dregs[dividend_reg] = dividend | quotient;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
89 context->vflag = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
90 context->nflag = quotient >> 8 & 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
91 context->zflag = quotient == 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
92 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
93
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
94 static void divs(m68k_context *context, uint32_t dividend_reg, uint32_t divisor)
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
95 {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
96 uint32_t dividend = context->dregs[dividend_reg];
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
97 uint32_t divisor_shift = divisor << 16;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
98 uint32_t orig_divisor = divisor_shift, orig_dividend = dividend;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
99 if (divisor_shift & 0x80000000) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
100 divisor_shift = 0 - divisor_shift;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
101 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
102
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
103 uint32_t cycles = 8;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
104 if (dividend & 0x80000000) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
105 //dvs10
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
106 dividend = 0 - dividend;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
107 cycles += 2;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
108 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
109 if (divisor_shift <= dividend) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
110 context->vflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
111 context->nflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
112 context->zflag = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
113 cycles += 4;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
114 context->cycles += cycles * context->opts->gen.clock_divider;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
115 return;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
116 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
117 uint16_t quotient = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
118 uint16_t bit = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
119 for (int i = 0; i < 15; i++)
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
120 {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
121 quotient = quotient << 1 | bit;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
122 dividend = dividend << 1;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
123
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
124 if (dividend >= divisor_shift) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
125 dividend -= divisor_shift;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
126 cycles += 6;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
127 bit = 1;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
128 } else {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
129 bit = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
130 cycles += 8;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
131 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
132 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
133 quotient = quotient << 1 | bit;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
134 dividend = dividend << 1;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
135 if (dividend >= divisor_shift) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
136 dividend -= divisor_shift;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
137 quotient = quotient << 1 | 1;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
138 } else {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
139 quotient = quotient << 1;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
140 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
141 cycles += 4;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
142
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
143 context->vflag = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
144 if (orig_divisor & 0x80000000) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
145 cycles += 16; //was 10
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
146 if (orig_dividend & 0x80000000) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
147 if (quotient & 0x8000) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
148 context->vflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
149 context->nflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
150 context->zflag = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
151 context->cycles += cycles * context->opts->gen.clock_divider;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
152 return;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
153 } else {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
154 dividend = -dividend;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
155 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
156 } else {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
157 quotient = -quotient;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
158 if (quotient && !(quotient & 0x8000)) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
159 context->vflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
160 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
161 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
162 } else if (orig_dividend & 0x80000000) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
163 cycles += 18; // was 12
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
164 quotient = -quotient;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
165 if (quotient && !(quotient & 0x8000)) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
166 context->vflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
167 } else {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
168 dividend = -dividend;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
169 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
170 } else {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
171 cycles += 14; //was 10
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
172 if (quotient & 0x8000) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
173 context->vflag= 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
174 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
175 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
176 if (context->vflag) {
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
177 context->nflag = 128;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
178 context->zflag = 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
179 context->cycles += cycles * context->opts->gen.clock_divider;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
180 return;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
181 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
182 context->nflag = (quotient & 0x8000) ? 128 : 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
183 context->zflag = quotient == 0;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
184 //V was cleared above, C is cleared by the generated machine code
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
185 context->cycles += cycles * context->opts->gen.clock_divider;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
186 context->dregs[dividend_reg] = dividend | quotient;
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
187 }
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
188
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
189 static sync_fun *sync_comp_tmp;
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
190 static int_ack_fun int_ack_tmp;
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
191 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun *sync_components, int_ack_fun int_ack)
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192 {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 memset(opts, 0, sizeof(*opts));
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194 opts->gen.memmap = memmap;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195 opts->gen.memmap_chunks = num_chunks;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196 opts->gen.address_mask = 0xFFFFFF;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197 opts->gen.byte_swap = 1;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 opts->gen.max_address = 0x1000000;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199 opts->gen.bus_cycles = 4;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 opts->gen.clock_divider = clock_divider;
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
201 sync_comp_tmp = sync_components;
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
202 int_ack_tmp = int_ack;
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
205 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler *reset_handler)
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 m68k_context *context = calloc(1, sizeof(m68k_context));
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 context->opts = opts;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209 context->reset_handler = reset_handler;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 context->int_cycle = 0xFFFFFFFFU;
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
211 context->int_pending = 255;
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
212 context->sync_components = sync_comp_tmp;
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
213 sync_comp_tmp = NULL;
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
214 context->int_ack_handler = int_ack_tmp;
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
215 int_ack_tmp = NULL;
1951
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 return context;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 void m68k_reset(m68k_context *context)
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 //read initial SP
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 context->scratch1 = 0;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 m68k_read_16(context);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 context->aregs[7] = context->scratch1 << 16;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 context->scratch1 = 2;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 m68k_read_16(context);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 context->aregs[7] |= context->scratch1;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 //read initial PC
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 context->scratch1 = 4;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 m68k_read_16(context);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 context->pc = context->scratch1 << 16;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 context->scratch1 = 6;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 m68k_read_16(context);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 context->pc |= context->scratch1;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 context->scratch1 = context->pc;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 m68k_read_16(context);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 context->prefetch = context->scratch1;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 context->pc += 2;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 context->status = 0x27;
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 void m68k_print_regs(m68k_context *context)
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 printf("XNZVC\n%d%d%d%d%d\n", context->xflag != 0, context->nflag != 0, context->zflag != 0, context->vflag != 0, context->cflag != 0);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 for (int i = 0; i < 8; i++) {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 printf("d%d: %X\n", i, context->dregs[i]);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 for (int i = 0; i < 8; i++) {
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 printf("a%d: %X\n", i, context->aregs[i]);
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253 }
8494fe8d6b65 Add missing file from new 68K core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 }
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
255
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
256 void m68k_serialize(m68k_context *context, uint32_t pc, serialize_buffer *buf)
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
257 {
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
258 //TODO: implement me
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
259 }
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
260
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
261 void m68k_deserialize(deserialize_buffer *buf, void *vcontext)
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
262 {
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
263 //TODO: implement me
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2447
diff changeset
264 }
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
265
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
266 void start_68k_context(m68k_context *context, uint32_t pc)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
267 {
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
268 context->scratch1 = context->pc = pc;
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
269 m68k_read_16(context);
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
270 context->prefetch = context->scratch1;
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
271 context->pc += 2;
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
272 }