repos/blastem: gentests.py annotate

annotate gentests.py @ 1746:cd6f4cea97b6

Call srand in Z80 test generator so different values are used when regenerating tests

author	Michael Pavone <pavone@retrodev.com>
date	Wed, 06 Feb 2019 08:54:56 -0800
parents	188a60def81f
children	f6ee0df6bb48

rev	line source
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #!/usr/bin/env python
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	2
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 def split_fields(line):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	4 parts = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	5 while line:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 field,_,line = line.partition('\t')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 parts.append(field.strip())
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 while line.startswith('\t'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 line = line[1:]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 return parts
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	11
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 class Program(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 def __init__(self, instruction):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 self.avail_dregs = {0,1,2,3,4,5,6,7}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 self.avail_aregs = {0,1,2,3,4,5,6,7}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 instruction.consume_regs(self)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 self.inst = instruction
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	18
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	19 def dirname(self):
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	20 return self.inst.name + '_' + self.inst.size
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 def name(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	23
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 def write_rom_test(self, outfile):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 outfile.write('\tdc.l $0, start\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	26 needdivzero = self.inst.name.startswith('div')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	27 needchk = self.inst.name.startswith('chk')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 for i in xrange(0x8, 0x100, 0x4):
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	29 if needdivzero and i == 0x14:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	30 outfile.write('\tdc.l div_zero_handler\n')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	31 elif needchk and i == 0x18:
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	32 outfile.write('\tdc.l chk_handler\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	33 else:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	34 outfile.write('\tdc.l empty_handler\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	35 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	36 if needdivzero:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	37 outfile.write('div_zero_handler:\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	38 div_zero_count = self.get_dreg()
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	39 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	40 outfile.write('\trte\n')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	41 if needchk:
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	42 outfile.write('chk_handler:\n')
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	43 chk_count = self.get_dreg()
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	44 outfile.write('\taddq #1, ' + str(chk_count) + '\n')
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	45 outfile.write('\trte\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	46 outfile.write('start:\n\tmove #0, CCR\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	47 if needdivzero:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	48 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 already = {}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 self.inst.write_init(outfile, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 if 'label' in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 outfile.write('lbl_' + str(already['label']) + ':\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 outfile.write('\t'+str(self.inst)+'\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 save_ccr = self.get_dreg()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	57 outfile.write('\tmove #$1F, CCR\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	58 self.inst.invalidate_dest(already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	59 self.inst.write_init(outfile, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 if 'label' in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 outfile.write('lbl_' + str(already['label']) + ':\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 outfile.write('\t'+str(self.inst)+'\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	64 outfile.write('\treset\nforever:\n\tbra.s forever\n')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	65
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 def consume_dreg(self, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 self.avail_dregs.discard(num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	68
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 def consume_areg(self, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 self.avail_aregs.discard(num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	71
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 def get_dreg(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 return Register('d', self.avail_dregs.pop())
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	74
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	75 class Dummy(object):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	76 def __str__(self):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	77 return ''
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	78 def write_init(self, outfile, size, already):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	79 pass
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	80 def consume_regs(self, program):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	81 pass
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	82
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	83 dummy_op = Dummy()
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	84
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 class Register(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 def __init__(self, kind, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 self.kind = kind
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 self.num = num
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	89
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 if self.kind == 'd' or self.kind == 'a':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 return self.kind + str(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	93 return self.kind
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	94
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 if not str(self) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 val = randint(minv,maxv)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	99 already[str(self)] = val
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	101
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	102 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 if self.kind == 'd':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 program.consume_dreg(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 elif self.kind == 'a':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 program.consume_areg(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	107
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 def valid_ram_address(address, size='b'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	110
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	112 return randint(mina/2, maxa/2)*2 \| 0xE00000
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	113
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 class Indexed(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	115 def __init__(self, base, index, index_size, disp):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	116 self.base = base
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 self.index = index
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 self.index_size = index_size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 self.disp = disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	120
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	121 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	122 if self.base.kind == 'pc':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 if str(self.index) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 index = already[str(self.index)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 if self.index_size == 'w':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 index = index & 0xFFFF
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	127 #sign extend index
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 if index & 0x8000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	129 index -= 65536
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	130 if index > -1024:
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	131 index = already[str(self.index)] = 2 * randint(-16384, -512)
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	132 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	133 else:
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	134 index = already[str(self.index)] = 2 * randint(-16384, -512)
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	135 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	136 num = already.get('label', 0)+1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 already['label'] = num
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	138 if (already[str(self.index)] + self.disp) & 1:
188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	139 self.disp += 1
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	140 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 else:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	142 if self.base == self.index:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	143 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	144 if not valid_ram_address(already[str(self.base)]*2):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	145 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	146 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	147 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	148 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	149 base = index = already[str(self.base)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	150 else:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	151 base = index = already[str(self.base)] = random_ram_address()/2
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	152 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 else:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	154 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	155 if not valid_ram_address(already[str(self.base)]):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	156 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	157 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	158 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	159 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	160 base = already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	161 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	162 base = already[str(self.base)] = random_ram_address()
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	163 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	164 if str(self.index) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	165 index = already[str(self.index)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	166 if self.index_size == 'w':
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	167 index = index & 0xFFFF
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	168 #sign extend index
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	169 if index & 0x8000:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	170 index -= 65536
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	171 if not valid_ram_address(base + index):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	172 index = already[str(self.index)] = randint(-64, 63)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	173 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	174 else:
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 index = already[str(self.index)] = randint(-64, 63)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 if (address & 0xFFFFFF) < 0xE00000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 if (address & 0xFFFFFF) < 128:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	180 self.disp -= (address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 self.disp += 0xE00000-(address & 0xFFFFFF)
608 097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	183 if self.disp > 127:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	184 self.disp = 127
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	185 elif self.disp < -128:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	186 self.disp = -128
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 elif (address & 0xFFFFFF) > 0xFFFFFC:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
608 097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	190 if self.disp > 127:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	191 self.disp = 127
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	192 elif self.disp < -128:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	193 self.disp = -128
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 if size != 'b' and address & 1:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 self.disp = self.disp ^ 1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	200
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	203
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 self.base.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 self.index.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	207
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 class Displacement(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 def __init__(self, base, disp):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 self.base = base
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	211 if disp & 1:
188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	212 disp += 1
188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	213 self.disp = disp
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	214
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 if self.base.kind == 'pc':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	217 num = already.get('label', 0)+1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 already['label'] = num
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	219 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	220 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 if str(self.base) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	222 if not valid_ram_address(already[str(self.base)]):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 del already[str(self.base)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 base = already[str(self.base)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	229 base = already[str(self.base)] = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	230 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 if (address & 0xFFFFFF) < 0xE00000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 if (address & 0xFFFFFF) < 0x10000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	234 self.disp -= (address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	235 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 self.disp += 0xE00000-(address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	237 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 elif (address & 0xFFFFFF) > 0xFFFFFC:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 if size != 'b' and address & 1:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 self.disp = self.disp ^ 1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	246
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	249
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	250 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 self.base.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	252
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 class Indirect(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	255 self.reg = reg
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	256
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 return '(' + str(self.reg) + ')'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	259
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	265 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	267 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	269 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	270 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	274 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	275 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	276
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	279
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	280 class Increment(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 self.reg = reg
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	283
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	284 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	285 return '(' + str(self.reg) + ')+'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	286
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	287 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	288 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	289 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	294 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	299 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	301 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	303
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	305 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	306
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	307 class Decrement(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	309 self.reg = reg
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	310
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	311 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	312 return '-(' + str(self.reg) + ')'
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	313
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	314 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	318 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	319 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	320 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	321 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	322 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	323 address = random_ram_address(mina=0xE00004)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	324 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	325 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	326 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	327 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	328 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	329 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	330
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	331 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	332 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	333
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	334 class Absolute(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	335 def __init__(self, address, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	336 self.address = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 self.size = size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	338
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	339 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	340 return '(' + str(self.address) + ').' + self.size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	341
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	342 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	343 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	344 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	345
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	347 pass
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	348
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	349 class Immediate(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	350 def __init__(self, value):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	351 self.value = value
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	352
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	353 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	354 return '#' + str(self.value)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	355
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	356 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 pass
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	358
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	360 pass
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	361
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	362 all_dregs = [Register('d', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 all_aregs = [Register('a', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	364 all_indirect = [Indirect(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	365 all_predec = [Decrement(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 all_postinc = [Increment(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	367 from random import randint
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 def all_indexed():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	369 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	370
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 def all_disp():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	373
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 def rand_pc_disp():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	375 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	376
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 def all_pc_indexed():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	379
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	380 def rand_abs_short():
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	381 return [Absolute(random_ram_address(0xFFFF8000), 'w') for x in xrange(0, 8)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	382
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	383 def rand_abs_long():
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	384 return [Absolute(random_ram_address(), 'l') for x in xrange(0, 8)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	385
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	386 def get_size_range(size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	387 if size == 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	388 return (-128, 127)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	389 elif size == 'w':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	390 return (-32768, 32767)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	391 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	392 return (-2147483648, 2147483647)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	393
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	394 def rand_immediate(size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	395 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	396
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	397 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	398
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	399 def get_variations(mode, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	400 mapping = {
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	401 'd':all_dregs,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	402 'a':all_aregs,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	403 '(a)':all_indirect,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	404 '-(a)':all_predec,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	405 '(a)+':all_postinc,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	406 '(n,a)':all_disp,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	407 '(n,a,x)':all_indexed,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	408 '(n,pc)':rand_pc_disp,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	409 '(n,pc,x)':all_pc_indexed,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	410 '(n).w':rand_abs_short,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	411 '(n).l':rand_abs_long
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	412 }
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	413 if mode in mapping:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	414 ret = mapping[mode]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	415 if type(ret) != list:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	416 ret = ret()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	417 return ret
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	418 elif mode == '#n':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	419 return rand_immediate(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	420 elif mode.startswith('#(') and mode.endswith(')'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 inner = mode[2:-1]
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	422 start,sep,end = inner.rpartition('-')
220 cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	423 start,end = int(start),int(end)
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	424 if end-start > 16:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	425 return [Immediate(randint(start, end)) for x in range(0,8)]
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	426 else:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	427 return [Immediate(num) for num in range(start, end+1)]
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	428 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	429 print "Don't know what to do with source type", mode
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	430 return None
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	431
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	432 class Inst2Op(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	433 def __init__(self, name, size, src, dst):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	434 self.name = name
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	435 self.size = size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	436 self.src = src
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	437 self.dst = dst
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	438
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	439 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	440 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	441
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	442 def write_init(self, outfile, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	443 self.src.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	444 self.dst.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	445
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	446 def invalidate_dest(self, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 if type(self.dst) == Register:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	448 del already[str(self.dst)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	449
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	450 def save_result(self, reg, always):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	451 if always or type(self.dst) != Register:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	452 if type(self.dst) == Decrement:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	453 src = Increment(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	454 elif type(self.dst) == Increment:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	455 src = Decrement(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	456 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	457 src = self.dst
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	458 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	459 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	460 return ''
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	461
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	462 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	463 self.src.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	464 self.dst.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	465
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	466 class Inst1Op(Inst2Op):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	467 def __init__(self, name, size, dst):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	468 super(Inst1Op, self).__init__(name, size, dummy_op, dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	469
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	470 def __str__(self):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	471 return self.name + '.' + self.size + ' ' + str(self.dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	472
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	473 class Entry(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	474 def __init__(self, line):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	475 fields = split_fields(line)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	476 self.name = fields[0]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	477 sizes = fields[1]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	478 sources = fields[2].split(';')
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	479 if len(fields) > 3:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	480 dests = fields[3].split(';')
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	481 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	482 dests = None
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	483 combos = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	484 for size in sizes:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	485 for source in sources:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	486 if size != 'b' or source != 'a':
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	487 if dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	488 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	489 if size != 'b' or dest != 'a':
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	490 combos.append((size, source, dest))
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	491 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	492 combos.append((size, None, source))
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	493 self.cases = combos
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	494
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	495 def programs(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	496 res = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	497 for (size, src, dst) in self.cases:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	498 dests = get_variations(dst, size)
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	499 if src:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	500 sources = get_variations(src, size)
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	501 for source in sources:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	502 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	503 res.append(Program(Inst2Op(self.name, size, source, dest)))
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	504 else:
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	505 for dest in dests:
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	506 res.append(Program(Inst1Op(self.name, size, dest)))
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	507 return res
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	508
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	509 def process_entries(f):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	510 entries = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	511 for line in f:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	512 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	513 entries.append(Entry(line))
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	514 return entries
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	515
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	516 from os import path, mkdir
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	517 def main(args):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	518 entries = process_entries(open('testcases.txt'))
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	519 for entry in entries:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	520 programs = entry.programs()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	521 for program in programs:
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	522 dname = program.dirname()
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	523 if not path.exists('generated_tests/' + dname):
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	524 mkdir('generated_tests/' + dname)
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	525 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	526 program.write_rom_test(f)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	527 f.close()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	528
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	529 if __name__ == '__main__':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	530 import sys
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	531 main(sys.argv)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	532

Mercurial > repos > blastem

annotate gentests.py @ 1746:cd6f4cea97b6