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annotate m68k_to_x86.c @ 79:d212e0cd0b7e

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Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
author Mike Pavone <pavone@retrodev.com>
date Fri, 21 Dec 2012 22:24:45 -0800
parents 463641032588
children 6d231dbe75ab
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1 #include "gen_x86.h"
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2 #include "m68k_to_x86.h"
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3 #include <stdio.h>
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4 #include <stddef.h>
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5 #include <stdlib.h>
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6 #include <string.h>
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7
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8 #define BUS 4
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9 #define PREDEC_PENALTY 2
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10 #define CYCLES RAX
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11 #define LIMIT RBP
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12 #define SCRATCH1 RCX
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13 #define SCRATCH2 RDI
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14 #define CONTEXT RSI
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15
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16 #define FLAG_N RBX
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17 #define FLAG_V BH
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18 #define FLAG_Z RDX
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19 #define FLAG_C DH
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20
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21 typedef struct {
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22 int32_t disp;
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23 uint8_t mode;
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24 uint8_t base;
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25 uint8_t index;
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26 uint8_t cycles;
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27 } x86_ea;
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28
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29 void handle_cycle_limit();
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30 void m68k_read_word_scratch1();
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31 void m68k_read_long_scratch1();
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32 void m68k_read_byte_scratch1();
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33 void m68k_write_word();
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34 void m68k_write_long_lowfirst();
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35 void m68k_write_long_highfirst();
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36 void m68k_write_byte();
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37 void m68k_save_context();
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38 void m68k_modified_ret_addr();
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39 void m68k_native_addr();
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40 void m68k_start_context(uint8_t * addr, m68k_context * context);
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41
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42 uint8_t * cycles(uint8_t * dst, uint32_t num)
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43 {
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44 dst = add_ir(dst, num, CYCLES, SZ_D);
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45 }
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46
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47 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
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48 {
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49 if (op->addr_mode == MODE_REG) {
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50 return opts->dregs[op->params.regs.pri];
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51 }
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52 if (op->addr_mode == MODE_AREG) {
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53 return opts->aregs[op->params.regs.pri];
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54 }
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55 return -1;
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56 }
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57
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58 //must be called with an m68k_op_info that uses a register
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59 size_t reg_offset(m68k_op_info *op)
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60 {
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61 if (op->addr_mode == MODE_REG) {
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62 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
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63 }
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64 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
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65 }
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66
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67 void print_regs_exit(m68k_context * context)
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68 {
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69 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
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70 for (int i = 0; i < 8; i++) {
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71 printf("d%d: %X\n", i, context->dregs[i]);
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72 }
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73 for (int i = 0; i < 8; i++) {
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74 printf("a%d: %X\n", i, context->aregs[i]);
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75 }
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76 exit(0);
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77 }
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78
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79 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
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80 {
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81 int8_t reg = native_reg(&(inst->src), opts);
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82 int32_t dec_amount,inc_amount;
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83 if (reg >= 0) {
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84 ea->mode = MODE_REG_DIRECT;
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85 ea->base = reg;
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86 return out;
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87 }
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88 switch (inst->src.addr_mode)
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89 {
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90 case MODE_REG:
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91 case MODE_AREG:
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92 //We only get one memory parameter, so if the dst operand is a register in memory,
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93 //we need to copy this to a temp register first
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94 reg = native_reg(&(inst->dst), opts);
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95 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode == MODE_AREG)
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96 || inst->op == M68K_EXG) {
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97
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98 ea->mode = MODE_REG_DISPLACE8;
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99 ea->base = CONTEXT;
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100 ea->disp = reg_offset(&(inst->src));
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101 } else {
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102 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
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103 ea->mode = MODE_REG_DIRECT;
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104 ea->base = SCRATCH1;
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105 }
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106 break;
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107 case MODE_AREG_PREDEC:
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108 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
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109 out = cycles(out, PREDEC_PENALTY);
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110 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
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111 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
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112 } else {
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113 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
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114 }
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115 case MODE_AREG_INDIRECT:
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116 case MODE_AREG_POSTINC:
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117 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
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118 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
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119 } else {
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120 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
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121 }
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122 switch (inst->extra.size)
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123 {
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124 case OPSIZE_BYTE:
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125 out = call(out, (char *)m68k_read_byte_scratch1);
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Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
126 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
127 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
128 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
129 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
130 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
131 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
132 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
133 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
134
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
135 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
136 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
137 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
138 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
139 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
140 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
141 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
142 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
143 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
144 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
145 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
146 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
147 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
148 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
149 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
150 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
151 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
152 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
153 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
154 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
155 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
156 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
157 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
158 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
159 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
160 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
161 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
162 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
163 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
164 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
165 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
166 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
167 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
168 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
169 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
170 out = cycles(out, BUS);
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
171 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
172 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
173 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
174 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
175 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
176 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
177 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
178 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
179 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
180 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
181 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
182 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
183 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
184 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
185 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
186 break;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
187 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
188 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
189 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
190 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
191 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
192 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
193 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
194 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
195 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
196 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
197 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
198 out = call(out, (char *)m68k_read_byte_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
199 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
200 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
201 out = call(out, (char *)m68k_read_word_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
202 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
203 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
204 out = call(out, (char *)m68k_read_long_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
205 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
206 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
207 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
208 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
209 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
210 case MODE_IMMEDIATE:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
211 case MODE_IMMEDIATE_WORD:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
212 if (inst->variant != VAR_QUICK) {
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
213 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
214 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
215 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
216 ea->disp = inst->src.params.immed;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
217 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
218 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
219 printf("address mode %d not implemented (src)\n", inst->src.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
220 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
221 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
222 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
223 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
224
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
225 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
226 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
227 int8_t reg = native_reg(&(inst->dst), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
228 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
229 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
230 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
231 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
232 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
233 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
234 switch (inst->dst.addr_mode)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237 case MODE_AREG:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
238 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
239 ea->base = CONTEXT;
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
240 ea->disp = reg_offset(&(inst->dst));
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
241 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
242 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
243 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
244 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
245 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
246 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
247 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
248 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
249 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
250 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
251 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
252 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
253 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
254 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
255 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
256 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
257 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
258 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
259 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
260 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
261 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
262 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
263 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
264 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
265 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
266 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
267 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
268 //save reg value in SCRATCH2 so we can use it to save the result in memory later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
269 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
270 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
271 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
272 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
273 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
274
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
275 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
276 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
277 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
278 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
279 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
280 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
281 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
282 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
283 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
284 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
285 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
286 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
287 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
288 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
289 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
290 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
291 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
292 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
293 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
294 out = push_r(out, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
295 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
296 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
297 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
298 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
299 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
300 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
301 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
302 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
303 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
304 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
305 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
306 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
307 out = pop_r(out, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
308 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
309 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
310 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
311 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
312 out = cycles(out, BUS);
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
313 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
314 out = push_r(out, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
315 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
316 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
317 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
318 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
319 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
320 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
321 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
322 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
323 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
324 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
325 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
326 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
327 out = pop_r(out, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
328 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
329 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
330 break;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
331 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
332 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
333 //Add cycles for reading address from instruction stream
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
334 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
335 out = cycles(out, BUS*2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
336 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
337 out = cycles(out, BUS);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
338 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
339 out = mov_ir(out, inst->dst.params.immed, SCRATCH1, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
340 out = push_r(out, SCRATCH1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
341 switch (inst->extra.size)
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
342 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
343 case OPSIZE_BYTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
344 out = call(out, (char *)m68k_read_byte_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
345 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
346 case OPSIZE_WORD:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
347 out = call(out, (char *)m68k_read_word_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
348 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
349 case OPSIZE_LONG:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
350 out = call(out, (char *)m68k_read_long_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
351 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
352 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
353 out = pop_r(out, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
354 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
355 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
356 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
357 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
358 printf("address mode %d not implemented (dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
359 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
360 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
361 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
362 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
363
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
364 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
365 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
366 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
367 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
368 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
369 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
370 out = call(out, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
371 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
372 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
373 out = call(out, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
374 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
375 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
376 out = call(out, (char *)m68k_write_long_lowfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
377 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
378 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
379 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
380 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
381 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
382
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
383 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
384 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
385 address &= 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
386 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
387 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
388 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
389 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
390 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
391 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
392 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
393 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
394 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
395 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
396
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
397 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
398 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
399 deferred_addr * new_head = malloc(sizeof(deferred_addr));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
400 new_head->next = old_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
401 new_head->address = address & 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
402 new_head->dest = dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
403 return new_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
404 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
405
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
406 void process_deferred(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
407 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
408 deferred_addr * cur = opts->deferred;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
409 deferred_addr **last_next = &(opts->deferred);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
410 while(cur)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
411 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
412 uint8_t * native = get_native_address(opts->native_code_map, cur->address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
413 if (native) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
414 int32_t disp = native - (cur->dest + 4);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
415 uint8_t * out = cur->dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
416 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
417 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
418 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
419 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
420 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
421 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
422 *out = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
423 *last_next = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
424 free(cur);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
425 cur = *last_next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
426 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
427 last_next = &(cur->next);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
428 cur = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
429 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
430 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
431 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
432
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
433 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
434 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
435 //FIXME: This probably isn't going to work with real code in a lot of cases, no guarantee that
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
436 //all the code in 1KB block is going to be translated at the same time
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
437 address &= 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
438 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
439 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
440 native_code_map[chunk].base = native_addr;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
441 native_code_map[chunk].offsets = malloc(sizeof(uint16_t) * NATIVE_CHUNK_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
442 memset(native_code_map[chunk].offsets, 0xFF, sizeof(uint16_t) * NATIVE_CHUNK_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
443 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
444 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
445 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
446 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
447
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
448 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
449 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
450 int8_t reg, flags_reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
451 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
452 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
453 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
454 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
455 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
456 reg = native_reg(&(inst->dst), opts);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
457 //update statically set flags
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
458 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
459 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
460
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
461 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
462 flags_reg = src.base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
463 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
464 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
465 flags_reg = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
466 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
467 dst = mov_ir(dst, src.disp, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
468 src.mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
469 flags_reg = src.base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
470 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
471 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
472 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
473 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
474 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
475 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
476 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
477 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
478 dst = mov_rr(dst, src.base, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
479 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
480 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
481 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
482 dst = mov_ir(dst, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
483 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
484 } else if(src.mode == MODE_REG_DIRECT) {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
485 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
486 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
487 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
488 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
489 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
490 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
491 dst = setcc_r(dst, CC_S, FLAG_N);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
492 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
493 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
494 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
495 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
496 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
497 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
498 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
499 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
500 case MODE_AREG_INDIRECT:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
501 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
502 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
503 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
504 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
505 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
506 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
507 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
508 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
509 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
510 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
511 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
512 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
513 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
514 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
515 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
516 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
517 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
518 dst = setcc_r(dst, CC_S, FLAG_N);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
519 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
520 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
521 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
522 dst = call(dst, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
523 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
524 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
525 dst = call(dst, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
526 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
527 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
528 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
529 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
530 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
531 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
532 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
533 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
534 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
535 } else {
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
536 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
537 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
538 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
539 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
540 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
541 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
542 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
543 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
544 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
545 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
546 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
547 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
548 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
549 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
550 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
551 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
552 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
553 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
554 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
555 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
556 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
557 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
558 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
559 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
560 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
561 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
562 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
563 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
564 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
565 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
566 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
567 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
568 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
569 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
570 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
571 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
572 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
573 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
574 dst = cycles(dst, BUS);
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
575 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
576 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
577 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
578 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
579 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
580 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
581 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
582 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
583 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
584 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
585 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
586 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
587 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
588 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
589 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
590 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
591 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
592 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
593 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
594 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
595 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
596 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
597 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
598 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
599 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
600 break;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
601 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
602 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
603 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
604 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
605 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
606 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
607 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
608 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
609 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
610 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
611 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
612 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
613 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
614 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
615 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
616 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
617 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
618 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
619 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
620 dst = setcc_r(dst, CC_S, FLAG_N);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
621 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
622 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
623 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
624 dst = call(dst, (char *)m68k_write_byte);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
625 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
626 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
627 dst = call(dst, (char *)m68k_write_word);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
628 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
629 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
630 dst = call(dst, (char *)m68k_write_long_highfirst);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
631 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
632 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
633 break;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
634 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
635 printf("address mode %d not implemented (move dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
636 exit(1);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
637 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
638
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
639 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
640 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
641 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
642 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
643
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
644 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
645 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
646 int8_t bit,reg;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
647 uint8_t early_cycles;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
648 if(inst->src.addr_mode == MODE_REG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
649 //reg to mem
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
650 early_cycles = 8;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
651 int8_t dir;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
652 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
653 reg = 15;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
654 dir = -1;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
655 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
656 reg = 0;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
657 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
658 switch (inst->dst.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
659 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
660 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
661 case MODE_AREG_PREDEC:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
662 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
663 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
664 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
665 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
666 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
667 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
668 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
669 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
670 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
671 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
672 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
673 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
674 default:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
675 printf("address mode %d not implemented (movem dst)\n", inst->dst.addr_mode);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
676 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
677 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
678 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
679 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
680 if (inst->src.params.immed & (1 << bit)) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
681 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
682 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
683 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
684 dst = push_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
685 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
686 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
687 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
688 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
689 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
690 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
691 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
692 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
693 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
694 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
695 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
696 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
697 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
698 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
699 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
700 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
701 dst = call(dst, (uint8_t *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
702 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
703 dst = pop_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
704 if (inst->dst.addr_mode != MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
705 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
706 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
707 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
708 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
709 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
710 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
711 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
712 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
713 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
714 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
715 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
716 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
717 //mem to reg
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
718 early_cycles = 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
719 switch (inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
720 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
721 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
722 case MODE_AREG_POSTINC:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
723 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
724 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
725 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
726 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
727 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
728 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
729 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
730 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
731 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
732 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
733 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
734 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
735 default:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
736 printf("address mode %d not implemented (movem src)\n", inst->src.addr_mode);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
737 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
738 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
739 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
740 for(reg = 0; reg < 16; reg ++) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
741 if (inst->dst.params.immed & (1 << reg)) {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
742 dst = push_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
743 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
744 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
745 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
746 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
747 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
748 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
749 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
750 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
751 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
752 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
753 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
754 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
755 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
756 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
757 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
758 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
759 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
760 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
761 dst = pop_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
762 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
763 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
764 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
765 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
766 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
767 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
768 } else {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
769 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
770 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
771 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
772 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
773 //prefetch
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
774 dst = cycles(dst, 4);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
775 return dst;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
776 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
777
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
778 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
779 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
780 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
781 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
782 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
783 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
784 uint8_t reg = native_reg(&(inst->dst), opts);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
785 if (reg >= 0) {
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
786 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
787 return xor_rr(dst, reg, reg, inst->extra.size);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
788 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
789 int32_t dec_amount,inc_amount;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
790 switch (inst->dst.addr_mode)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
791 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
792 case MODE_REG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
793 case MODE_AREG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
794 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
795 dst = mov_irdisp8(dst, 0, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
796 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
797 case MODE_AREG_PREDEC:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
798 dst = cycles(dst, PREDEC_PENALTY);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
799 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
800 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
801 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
802 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
803 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
804 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
805 case MODE_AREG_INDIRECT:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
806 case MODE_AREG_POSTINC:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
807 //add cycles for prefetch and wasted read
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
808 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 12 : 8));
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
809 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
810 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
811 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
812 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
813 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
814 dst = xor_rr(dst, SCRATCH1, SCRATCH1, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
815 switch (inst->extra.size)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
816 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
817 case OPSIZE_BYTE:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
818 dst = call(dst, (char *)m68k_write_byte);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
819 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
820 case OPSIZE_WORD:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
821 dst = call(dst, (char *)m68k_write_word);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
822 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
823 case OPSIZE_LONG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
824 dst = call(dst, (char *)m68k_write_long_highfirst);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
825 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
826 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
827 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
828 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
829 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
830 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
831 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
832 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
833 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
834 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
835 break;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
836 default:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
837 printf("address mode %d not implemented (clr dst)\n", inst->dst.addr_mode);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
838 exit(1);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
839 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
840 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
841 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
842
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
843 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
844 {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
845 int8_t dst_reg = native_reg(&(inst->dst), opts);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
846 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
847 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
848 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
849 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
850 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
851 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
852 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
853 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
854 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
855 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
856 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
857 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
858 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
859 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
860 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
861 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
862 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
863 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
864 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
865 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
866 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
867 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
868 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
869 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
870 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
871 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
872 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
873 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
874 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
875 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
876 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
877 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
878 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
879 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
880 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
881 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
882 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
883 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
884 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
885 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
886 if (dst_reg >= 0) {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
887 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
888 } else {
74
6396dc91f61e Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents: 73
diff changeset
889 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
890 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
891 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
892 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
893 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
894 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
895 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
896 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
897 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
898 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
899 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
900 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
901 default:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
902 printf("address mode %d not implemented (lea src)\n", inst->src.addr_mode);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
903 exit(1);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
904 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
905 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
906 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
907
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
908 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
909 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
910 int32_t disp = inst->src.params.immed;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
911 uint32_t after = inst->address + 2;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
912 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
913 dst = cycles(dst, 10);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
914 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
915 dst = push_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
916 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
917 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
918 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
919 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
920 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
921 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
922 //dummy address to be replaced later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
923 dest_addr = dst + 5;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
924 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
925 dst = call(dst, (char *)dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
926 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
927 dst = pop_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
928 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
929 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
930
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
931 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
932 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
933 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
934 int32_t disp = inst->src.params.immed;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
935 uint32_t after = inst->address + 2;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
936 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
937 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
938 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
939 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
940 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
941 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
942 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
943 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
944 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
945 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
946 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
947 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
948 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
949 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
950 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
951 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
952 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
953 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
954 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
955 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
956 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
957 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
958 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
959 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
960 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
961 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
962 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
963 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
964 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
965 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
966 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
967 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
968 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
969 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
970 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
971 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
972 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
973 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
974 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
975 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
976 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
977 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
978 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
979 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
980 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
981 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
982 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
983 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
984 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
985 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
986 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
987 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
988 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
989 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
990 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
991 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
992 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
993 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
994 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
995 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
996
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
997 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
998 {
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
999 uint8_t * dest_addr;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1000 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1001 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1002 case MODE_AREG_INDIRECT:
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1003 dst = cycles(dst, BUS*2);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1004 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1005 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1006 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1007 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1008 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1009 dst = call(dst, (uint8_t *)m68k_native_addr);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1010 //TODO: Finish me
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1011 printf("address mode %d not yet supported (jmp)\n", inst->src.addr_mode);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1012 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1013 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1014 dst = cycles(dst, 10);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1015 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1016 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1017 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1018 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1019 dest_addr = dst + 256;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1020 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1021 dst = jmp(dst, dest_addr);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1022 break;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1023 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1024 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1025 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1026 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1027 if (!dest_addr) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1028 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1029 //dummy address to be replaced later, make sure it generates a 4-byte displacement
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1030 dest_addr = dst + 256;
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1031 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1032 dst = jmp(dst, dest_addr);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1033 break;
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1034 default:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1035 printf("address mode %d not yet supported (jmp)\n", inst->src.addr_mode);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1036 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1037 return dst;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1038 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1039
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1040 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1041 {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1042 uint8_t * dest_addr;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1043 uint32_t after;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1044 switch(inst->src.addr_mode)
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1045 {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1046 case MODE_AREG_INDIRECT:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1047 dst = cycles(dst, BUS*2);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1048 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1049 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1050 } else {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1051 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1052 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1053 dst = call(dst, (uint8_t *)m68k_native_addr);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1054 //TODO: Finish me
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1055 printf("address mode %d not yet supported (jsr)\n", inst->src.addr_mode);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1056 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1057 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1058 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1059 dst = cycles(dst, 10);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1060 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1061 dst = push_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1062 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1063 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1064 dst = call(dst, (char *)m68k_write_long_highfirst);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1065 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1066 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1067 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1068 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1069 dest_addr = dst + 5;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1070 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1071 dst = call(dst, (char *)dest_addr);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1072 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1073 dst = pop_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1074 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1075 case MODE_ABSOLUTE:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1076 case MODE_ABSOLUTE_SHORT:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1077 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1078 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1079 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1080 dst = push_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1081 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1082 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1083 dst = call(dst, (char *)m68k_write_long_highfirst);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1084 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1085 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1086 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1087 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1088 dest_addr = dst + 5;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1089 }
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1090 dst = call(dst, (char *)dest_addr);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1091 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1092 dst = pop_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1093 break;
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1094 default:
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1095 printf("address mode %d not yet supported (jsr)\n", inst->src.addr_mode);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1096 }
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1097 return dst;
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1098 }
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1099
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1100 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1101 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1102 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1103 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1104 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1105 dst = call(dst, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1106 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1107 dst = jcc(dst, CC_NZ, dst+3);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1108 dst = retn(dst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1109 dst = jmp(dst, (char *)m68k_modified_ret_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1110 return dst;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1111 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1112
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1113 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1114 {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1115 //best case duration
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1116 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1117 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1118 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1119 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1120 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1121 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1122 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1123 {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1124 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1125 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1126 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1127 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1128 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1129 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1130 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1131 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1132 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1133 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1134 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1135 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1136 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1137 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1138 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1139 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1140 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1141 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1142 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1143 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1144 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1145 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1146 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1147 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1148 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1149 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1150 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1151 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1152 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1153 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1154 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1155 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1156 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1157 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1158 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1159 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1160 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1161 break;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1162 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1163 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1164 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1165 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1166 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1167 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1168 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1169 } else {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1170 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1171 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1172 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1173 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1174 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1175 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1176 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1177 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1178 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1179 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1180 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1181 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1182 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1183 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1184 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1185 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1186 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1187 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1188 } else {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1189 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1190 }
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1191 return dst;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1192 }
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1193
78
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1194 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1195 {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1196 int8_t reg = native_reg(&(inst->src), opts);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1197 //compensate for displacement word
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1198 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1199 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1200 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1201 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1202 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1203 } else {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1204 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1205 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1206 dst = call(dst, (char *)m68k_write_long_highfirst);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1207 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1208 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1209 } else {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1210 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1211 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1212 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1213 //prefetch
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1214 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1215 return dst;
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1216 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1217
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1218 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1219 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1220 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1221 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1222
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1223 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1224 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1225 uint8_t * end_off = NULL;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1226 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1227 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1228 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1229 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1230 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1231 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1232 if (src_op->mode == MODE_IMMED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1233 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1234 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1235 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1236 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1237 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1238 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1239 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1240 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1241 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1242 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1243 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1244 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1245 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1246 dst = and_ir(dst, 63, RCX, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1247 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1248 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1249 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1250 //x86 shifts modulo 32 for operand sizes less than 64-bits
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1251 //but M68K shifts modulo 64, so we need to check for large shifts here
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1252 dst = cmp_ir(dst, 32, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1253 uint8_t * norm_shift_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1254 dst = jcc(dst, CC_L, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1255 if (special) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1256 if (inst->extra.size == OPSIZE_LONG) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1257 uint8_t * neq_32_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1258 dst = jcc(dst, CC_NZ, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1259
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1260 //set the carry bit to the lsb
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1261 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1262 dst = special(dst, 1, dst_op->base, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1263 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1264 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1265 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1266 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1267 dst = jmp(dst, dst+4);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1268 *neq_32_off = dst - (neq_32_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1269 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1270 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1271 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1272 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1273 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1274 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1275 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1276 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1277 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1278 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1279 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1280 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1281 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1282 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1283 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1284 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1285 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1286
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1287 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1288 end_off = dst+1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1289 dst = jmp(dst, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1290 *norm_shift_off = dst - (norm_shift_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1291 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1292 dst = shift_clr(dst, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1293 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1294 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1295 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1296
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1297 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1298
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1299 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1300 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1301 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1302 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1303 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1304 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1305 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1306 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1307 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1308 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1309 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1310 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1311 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1312 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1313 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1314 }
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
1315 return dst;
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1316 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1317
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1318 #define BIT_SUPERVISOR 5
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1319
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1320 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1321 {
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1322 uint8_t * end_off;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1323 map_native_address(opts->native_code_map, inst->address, dst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1324 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1325 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1326 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1327 return translate_m68k_lea(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1328 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1329 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1330 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1331 return translate_m68k_bcc(dst, inst, opts);
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1332 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 52
diff changeset
1333 return translate_m68k_jmp(dst, inst, opts);
76
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1334 } else if(inst->op == M68K_JSR) {
187c65f40a64 Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 74
diff changeset
1335 return translate_m68k_jsr(dst, inst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1336 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1337 return translate_m68k_rts(dst, inst, opts);
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1338 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 19
diff changeset
1339 return translate_m68k_dbcc(dst, inst, opts);
52
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1340 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1341 return translate_m68k_clr(dst, inst, opts);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1342 } else if(inst->op == M68K_MOVEM) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1343 return translate_m68k_movem(dst, inst, opts);
78
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1344 } else if(inst->op == M68K_LINK) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1345 return translate_m68k_link(dst, inst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1346 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1347 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1348 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1349 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1350 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1351 if (inst->dst.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1352 dst = translate_m68k_dst(inst, &dst_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1353 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1354 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1355 {
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1356 //case M68K_ABCD:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1357 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1358 case M68K_ADD:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1359 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1360 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1361 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1362 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1363 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1364 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1365 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1366 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1367 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1368 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1369 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1370 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1371 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1372 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1373 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1374 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1375 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1376 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1377 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1378 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1379 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1380 dst = m68k_save_result(inst, dst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1381 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1382 //case M68K_ADDX:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1383 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1384 case M68K_AND:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1385 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1386 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1387 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1388 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1389 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1390 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1391 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1392 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1393 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1394 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1395 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1396 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1397 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1398 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1399 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1400 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1401 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1402 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1403 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1404 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1405 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1406 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1407 case M68K_ANDI_CCR:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1408 case M68K_ANDI_SR:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1409 dst = cycles(dst, 20);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1410 //TODO: If ANDI to SR, trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1411 if (!(inst->src.params.immed & 0x1)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1412 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1413 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1414 if (!(inst->src.params.immed & 0x2)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1415 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1416 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1417 if (!(inst->src.params.immed & 0x4)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1418 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1419 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1420 if (!(inst->src.params.immed & 0x8)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1421 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1422 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1423 if (!(inst->src.params.immed & 0x10)) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1424 dst = mov_irind(dst, 0, CONTEXT, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1425 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1426 if (inst->op == M68K_ANDI_SR) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1427 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1428 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1429 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1430 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1431 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1432 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1433 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1434 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1435 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1436 case M68K_ASL:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1437 case M68K_LSL:
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1438 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1439 break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1440 case M68K_ASR:
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1441 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1442 break;
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1443 case M68K_LSR:
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1444 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
1445 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1446 /*case M68K_BCHG:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1447 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1448 case M68K_BSET:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1449 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1450 case M68K_BTST:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1451 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
67
534eb4976423 Fix BTST
Mike Pavone <pavone@retrodev.com>
parents: 66
diff changeset
1452 if (src_op.mode == MODE_IMMED) {
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1453 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1454 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1455 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1456 if (dst_op.mode == MODE_REG_DIRECT) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1457 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1458 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1459 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1460 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1461 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1462 if (src_op.mode == MODE_REG_DISPLACE8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1463 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1464 dst = push_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1465 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1466 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1467 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1468 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1469 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1470 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1471 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1472 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1473 dst = and_ir(dst, 0x7, src_op.base, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1474 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1475 if (dst_op.mode == MODE_REG_DIRECT) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1476 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1477 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1478 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1479 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1480 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1481 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1482 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1483 dst = setcc_r(dst, CC_NC, FLAG_Z);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1484 if (src_op.base == SCRATCH2) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1485 dst = pop_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1486 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
1487 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1488 /*case M68K_CHK:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1489 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1490 case M68K_CMP:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1491 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1492 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1493 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1494 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1495 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1496 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1497 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1498 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1499 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1500 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1501 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1502 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1503 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1504 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1505 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1506 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1507 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1508 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1509 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1510 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1511 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1512 /*case M68K_DIVS:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1513 case M68K_DIVU:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1514 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1515 case M68K_EOR:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1516 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1517 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1518 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1519 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1520 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1521 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1522 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1523 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1524 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1525 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1526 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1527 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1528 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1529 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1530 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1531 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1532 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1533 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1534 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1535 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1536 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1537 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1538 /*case M68K_EORI_CCR:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1539 case M68K_EORI_SR:*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1540 case M68K_EXG:
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1541 dst = cycles(dst, 6);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1542 if (dst_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1543 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1544 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1545 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1546 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1547 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1548 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1549 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1550 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1551 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1552 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1553 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1554 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1555 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1556 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1557 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1558 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1559 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1560 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1561 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1562 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1563 //case M68K_EXT:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1564 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1565 case M68K_ILLEGAL:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1566 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1567 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1568 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1569 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1570 /*case M68K_JSR:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1571 case M68K_LEA:
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1572 case M68K_MOVE_FROM_SR:
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1573 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1574 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1575 case M68K_MOVE_SR:
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1576 //TODO: Privilege check for MOVE to SR
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1577 if (src_op.mode == MODE_IMMED) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1578 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1579 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1580 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1581 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1582 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1583 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1584 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1585 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1586 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1587 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1588 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1589 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1590 }
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1591 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1592 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1593 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1594 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1595 dst = mov_rr(dst, src_op.base, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1596 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1597 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1598 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1599 dst = mov_rr(dst, FLAG_C, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1600 dst = and_ir(dst, 1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1601 dst = shr_ir(dst, 1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1602 dst = mov_rr(dst, FLAG_V, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1603 dst = and_ir(dst, 1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1604 dst = shr_ir(dst, 1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1605 dst = mov_rr(dst, FLAG_Z, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1606 dst = and_ir(dst, 1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1607 dst = shr_ir(dst, 1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1608 dst = mov_rr(dst, 1, SCRATCH2, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1609 dst = shr_ir(dst, 1, SCRATCH2, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1610 dst = and_ir(dst, 1, SCRATCH2, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1611 dst = mov_rrind(dst, SCRATCH2, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1612 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1613 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1614 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1615 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_W);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1616 } else {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1617 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1618 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1619 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1620 dst = shr_ir(dst, 8, SCRATCH2, SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1621 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, status), SZ_B);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1622 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1623 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1624 case M68K_MOVE_USP:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1625 dst = cycles(dst, BUS);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1626 //TODO: Trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1627 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1628 if (inst->src.addr_mode == MODE_UNUSED) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1629 if (dst_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1630 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1631 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1632 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1633 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1634 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1635 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1636 if (src_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1637 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1638 } else {
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1639 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1640 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1641 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1642 }
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1643 break;
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1644 /*case M68K_MOVEP:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1645 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1646 case M68K_MULU:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1647 case M68K_NBCD:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1648 case M68K_NEG:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1649 case M68K_NEGX:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1650 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1651 case M68K_NOP:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1652 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1653 break;
73
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1654 //case M68K_NOT:
8da611e69b32 Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1655 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1656 case M68K_OR:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1657 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1658 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1659 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1660 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1661 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1662 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1663 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1664 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1665 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1666 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1667 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1668 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1669 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1670 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1671 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1672 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1673 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1674 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1675 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1676 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1677 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1678 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1679 /*case M68K_ORI_CCR:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1680 case M68K_ORI_SR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1681 case M68K_PEA:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1682 case M68K_RESET:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1683 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1684 case M68K_ROR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1685 case M68K_ROXL:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1686 case M68K_ROXR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1687 case M68K_RTE:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1688 case M68K_RTR:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1689 case M68K_SBCD:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1690 case M68K_SCC:
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1691 case M68K_STOP:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1692 break;*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1693 case M68K_SUB:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1694 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1695 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1696 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1697 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1698 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1699 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1700 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1701 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1702 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1703 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1704 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1705 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1706 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1707 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1708 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1709 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1710 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1711 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1712 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1713 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1714 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1715 dst = m68k_save_result(inst, dst, opts);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1716 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1717 //case M68K_SUBX:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1718 // break;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1719 case M68K_SWAP:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1720 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1721 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1722 dst = rol_ir(dst, 16, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1723 } else{
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1724 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1725 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1726 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1727 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1728 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1729 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1730 break;
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1731 /*case M68K_TAS:
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1732 case M68K_TRAP:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1733 case M68K_TRAPV:*/
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1734 case M68K_TST:
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1735 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1736 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1737 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1738 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1739 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1740 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1741 dst = setcc_r(dst, CC_C, FLAG_C);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1742 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1743 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1744 dst = setcc_r(dst, CC_O, FLAG_V);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1745 break;
78
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1746 case M68K_UNLK:
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1747 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1748 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1749 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1750 } else {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1751 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1752 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1753 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1754 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1755 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1756 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1757 } else {
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1758 dst = mov_rdisp8r(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1759 }
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1760 break;
463641032588 Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents: 77
diff changeset
1761 /*case M68K_INVALID:
70
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1762 break;*/
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1763 default:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1764 printf("instruction %d not yet implemented\n", inst->op);
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents: 67
diff changeset
1765 exit(1);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1766 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1767 return dst;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1768 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1769
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1770 uint8_t * translate_m68k_stream(uint8_t * dst, uint8_t * dst_end, uint32_t address, m68k_context * context)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1771 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1772 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1773 x86_68k_options * opts = context->options;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1774 char disbuf[1024];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1775 uint16_t *encoded = context->mem_pointers[0] + address/2, *next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1776 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1777 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1778 if (dst_end-dst < 128) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1779 puts("out of code memory");
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1780 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1781 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1782 next = m68k_decode(encoded, &instbuf, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1783 address += (next-encoded)*2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1784 encoded = next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1785 m68k_disasm(&instbuf, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1786 printf("%X: %s\n", instbuf.address, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1787 dst = translate_m68k(dst, &instbuf, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1788 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1789 process_deferred(opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1790 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1791 address = opts->deferred->address;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1792 encoded = context->mem_pointers[0] + address/2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1793 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1794 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1795 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1796 } while(encoded != NULL);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1797 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1798 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1799
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1800 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1801 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1802 uint8_t * addr = get_native_address(context->native_code_map, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1803 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1804 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1805
19
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1806 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1807 {
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1808 //TODO: Make this actually use the normal read functions
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1809 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1];
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1810 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3];
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 70
diff changeset
1811 start_68k_context(context, address);
19
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1812 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1813
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1814 void init_x86_68k_opts(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1815 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1816 opts->flags = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1817 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1818 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1819 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1820 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1821 opts->dregs[2] = R12;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1822 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1823 opts->aregs[1] = R14;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1824 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1825 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
1826 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
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diff changeset
1827 opts->deferred = NULL;
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1828 }
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diff changeset
1829
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diff changeset
1830 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
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1831 {
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1832 memset(context, 0, sizeof(m68k_context));
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1833 context->native_code_map = native_code_map;
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diff changeset
1834 context->options = opts;
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diff changeset
1835 }
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diff changeset
1836