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annotate gentests.py @ 660:e7cae6d9aaa6

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Add the 3 cycle delay back in to Z80 bank area access
author Michael Pavone <pavone@retrodev.com>
date Thu, 01 Jan 2015 22:18:32 -0800
parents 097c172839d4
children 188a60def81f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #!/usr/bin/env python
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2
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3 def split_fields(line):
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4 parts = []
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5 while line:
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6 field,_,line = line.partition('\t')
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7 parts.append(field.strip())
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8 while line.startswith('\t'):
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9 line = line[1:]
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10 return parts
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11
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12 class Program(object):
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13 def __init__(self, instruction):
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14 self.avail_dregs = {0,1,2,3,4,5,6,7}
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15 self.avail_aregs = {0,1,2,3,4,5,6,7}
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16 instruction.consume_regs(self)
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17 self.inst = instruction
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18
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19 def dirname(self):
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20 return self.inst.name + '_' + self.inst.size
214
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21 def name(self):
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22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
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23
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24 def write_rom_test(self, outfile):
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25 outfile.write('\tdc.l $0, start\n')
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26 needdivzero = self.inst.name.startswith('div')
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27 needchk = self.inst.name.startswith('chk')
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28 for i in xrange(0x8, 0x100, 0x4):
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29 if needdivzero and i == 0x14:
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30 outfile.write('\tdc.l div_zero_handler\n')
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31 elif needchk and i == 0x18:
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32 outfile.write('\tdc.l chk_handler\n')
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33 else:
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34 outfile.write('\tdc.l empty_handler\n')
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35 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n')
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36 if needdivzero:
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37 outfile.write('div_zero_handler:\n')
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38 div_zero_count = self.get_dreg()
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39 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n')
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40 outfile.write('\trte\n')
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41 if needchk:
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42 outfile.write('chk_handler:\n')
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43 chk_count = self.get_dreg()
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44 outfile.write('\taddq #1, ' + str(chk_count) + '\n')
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45 outfile.write('\trte\n')
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46 outfile.write('start:\n\tmove #0, CCR\n')
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47 if needdivzero:
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48 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n')
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49 already = {}
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50 self.inst.write_init(outfile, already)
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51 if 'label' in already:
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52 outfile.write('lbl_' + str(already['label']) + ':\n')
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53 outfile.write('\t'+str(self.inst)+'\n')
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54 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
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55 save_ccr = self.get_dreg()
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56 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
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57 outfile.write('\tmove #$1F, CCR\n')
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58 self.inst.invalidate_dest(already)
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59 self.inst.write_init(outfile, already)
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60 if 'label' in already:
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61 outfile.write('lbl_' + str(already['label']) + ':\n')
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62 outfile.write('\t'+str(self.inst)+'\n')
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63 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
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64 outfile.write('\treset\n')
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65
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66 def consume_dreg(self, num):
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67 self.avail_dregs.discard(num)
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68
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69 def consume_areg(self, num):
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70 self.avail_aregs.discard(num)
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71
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72 def get_dreg(self):
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73 return Register('d', self.avail_dregs.pop())
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74
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75 class Dummy(object):
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76 def __str__(self):
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77 return ''
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78 def write_init(self, outfile, size, already):
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79 pass
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80 def consume_regs(self, program):
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81 pass
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82
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83 dummy_op = Dummy()
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84
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85 class Register(object):
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86 def __init__(self, kind, num):
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87 self.kind = kind
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88 self.num = num
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89
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90 def __str__(self):
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91 if self.kind == 'd' or self.kind == 'a':
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92 return self.kind + str(self.num)
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93 return self.kind
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94
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95 def write_init(self, outfile, size, already):
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96 if not str(self) in already:
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97 minv,maxv = get_size_range(size)
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98 val = randint(minv,maxv)
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99 already[str(self)] = val
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100 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
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101
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102 def consume_regs(self, program):
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103 if self.kind == 'd':
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104 program.consume_dreg(self.num)
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105 elif self.kind == 'a':
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106 program.consume_areg(self.num)
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107
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108 def valid_ram_address(address, size='b'):
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109 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
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110
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111 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
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112 return randint(mina, maxa) | 0xE00000
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113
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114 class Indexed(object):
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115 def __init__(self, base, index, index_size, disp):
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116 self.base = base
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117 self.index = index
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118 self.index_size = index_size
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119 self.disp = disp
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120
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121 def write_init(self, outfile, size, already):
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122 if self.base.kind == 'pc':
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123 if str(self.index) in already:
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124 index = already[str(self.index)]
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125 if self.index_size == 'w':
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126 index = index & 0xFFFF
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127 #sign extend index
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128 if index & 0x8000:
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129 index -= 65536
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130 if index > -1024:
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131 index = already[str(self.index)] = randint(-32768, -1024)
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132 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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133 else:
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134 index = already[str(self.index)] = randint(-32768, -1024)
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135 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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136 num = already.get('label', 0)+1
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137 already['label'] = num
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138 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
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139 else:
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140 if self.base == self.index:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
141 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
142 if not valid_ram_address(already[str(self.base)]*2):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
143 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
144 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
145 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
146 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
147 base = index = already[str(self.base)]
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
148 else:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
149 base = index = already[str(self.base)] = random_ram_address()/2
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
150 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
151 else:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
152 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
153 if not valid_ram_address(already[str(self.base)]):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
154 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
155 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
156 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
157 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
158 base = already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
159 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
160 base = already[str(self.base)] = random_ram_address()
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
161 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
162 if str(self.index) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
163 index = already[str(self.index)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
164 if self.index_size == 'w':
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
165 index = index & 0xFFFF
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
166 #sign extend index
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
167 if index & 0x8000:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
168 index -= 65536
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
169 if not valid_ram_address(base + index):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
170 index = already[str(self.index)] = randint(-64, 63)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
171 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
172 else:
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
173 index = already[str(self.index)] = randint(-64, 63)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
174 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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parents:
diff changeset
175 address = base + index + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
176 if (address & 0xFFFFFF) < 0xE00000:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 if (address & 0xFFFFFF) < 128:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
178 self.disp -= (address & 0xFFFFFF)
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parents:
diff changeset
179 else:
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parents:
diff changeset
180 self.disp += 0xE00000-(address & 0xFFFFFF)
608
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
181 if self.disp > 127:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
182 self.disp = 127
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
183 elif self.disp < -128:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
184 self.disp = -128
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
185 address = base + index + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
186 elif (address & 0xFFFFFF) > 0xFFFFFC:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
187 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
608
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
188 if self.disp > 127:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
189 self.disp = 127
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
190 elif self.disp < -128:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range
Michael Pavone <pavone@retrodev.com>
parents: 439
diff changeset
191 self.disp = -128
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 address = base + index + self.disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
193 if size != 'b' and address & 1:
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parents:
diff changeset
194 self.disp = self.disp ^ 1
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parents:
diff changeset
195 address = base + index + self.disp
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parents:
diff changeset
196 minv,maxv = get_size_range(size)
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parents:
diff changeset
197 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
diff changeset
198
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parents:
diff changeset
199 def __str__(self):
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parents:
diff changeset
200 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
201
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
203 self.base.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 self.index.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
205
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
206 class Displacement(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 def __init__(self, base, disp):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
208 self.base = base
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209 self.disp = disp
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 if self.base.kind == 'pc':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213 num = already.get('label', 0)+1
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 already['label'] = num
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
215 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 if str(self.base) in already:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
218 if not valid_ram_address(already[str(self.base)]):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219 del already[str(self.base)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
220 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
222 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 base = already[str(self.base)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 base = already[str(self.base)] = random_ram_address()
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parents:
diff changeset
226 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
227 address = base + self.disp
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 if (address & 0xFFFFFF) < 0xE00000:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
229 if (address & 0xFFFFFF) < 0x10000:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
230 self.disp -= (address & 0xFFFFFF)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
231 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
232 self.disp += 0xE00000-(address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 address = base + self.disp
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
234 elif (address & 0xFFFFFF) > 0xFFFFFC:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 address = base + self.disp
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237 if size != 'b' and address & 1:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 self.disp = self.disp ^ 1
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 address = base + self.disp
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
240 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242
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parents:
diff changeset
243 def __str__(self):
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parents:
diff changeset
244 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
245
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parents:
diff changeset
246 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
247 self.base.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
248
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
249 class Indirect(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250 def __init__(self, reg):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
251 self.reg = reg
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
252
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
253 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
254 return '(' + str(self.reg) + ')'
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
255
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
256 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
257 if str(self.reg) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
258 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
259 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
260 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
261 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
262 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
263 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
264 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
266 if size != 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 address = address & 0xFFFFFFFE
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
268 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
269 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
270 minv,maxv = get_size_range(size)
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271 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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272
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273 def consume_regs(self, program):
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274 self.reg.consume_regs(program)
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275
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276 class Increment(object):
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277 def __init__(self, reg):
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278 self.reg = reg
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279
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280 def __str__(self):
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281 return '(' + str(self.reg) + ')+'
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282
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283 def write_init(self, outfile, size, already):
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284 if str(self.reg) in already:
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285 if not valid_ram_address(already[str(self.reg)], size):
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286 del already[str(self.reg)]
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287 self.write_init(outfile, size, already)
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288 return
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289 else:
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290 address = already[str(self.reg)]
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291 else:
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292 address = random_ram_address()
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293 if size != 'b':
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294 address = address & 0xFFFFFFFE
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295 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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296 already[str(self.reg)] = address
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297 minv,maxv = get_size_range(size)
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298 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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299
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300 def consume_regs(self, program):
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301 self.reg.consume_regs(program)
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302
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303 class Decrement(object):
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304 def __init__(self, reg):
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305 self.reg = reg
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306
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307 def __str__(self):
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308 return '-(' + str(self.reg) + ')'
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309
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310 def write_init(self, outfile, size, already):
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311 if str(self.reg) in already:
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312 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
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313 del already[str(self.reg)]
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314 self.write_init(outfile, size, already)
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315 return
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diff changeset
316 else:
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317 address = already[str(self.reg)]
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318 else:
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319 address = random_ram_address(mina=0xE00004)
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320 if size != 'b':
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321 address = address & 0xFFFFFFFE
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diff changeset
322 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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diff changeset
323 already[str(self.reg)] = address
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324 minv,maxv = get_size_range(size)
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diff changeset
325 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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326
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327 def consume_regs(self, program):
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328 self.reg.consume_regs(program)
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329
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330 class Absolute(object):
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parents:
diff changeset
331 def __init__(self, address, size):
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parents:
diff changeset
332 self.address = address
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diff changeset
333 self.size = size
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parents:
diff changeset
334
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parents:
diff changeset
335 def __str__(self):
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parents:
diff changeset
336 return '(' + str(self.address) + ').' + self.size
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parents:
diff changeset
337
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parents:
diff changeset
338 def write_init(self, outfile, size, already):
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diff changeset
339 minv,maxv = get_size_range(size)
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diff changeset
340 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
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parents:
diff changeset
341
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diff changeset
342 def consume_regs(self, program):
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parents:
diff changeset
343 pass
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parents:
diff changeset
344
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diff changeset
345 class Immediate(object):
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parents:
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346 def __init__(self, value):
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parents:
diff changeset
347 self.value = value
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parents:
diff changeset
348
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parents:
diff changeset
349 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
350 return '#' + str(self.value)
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parents:
diff changeset
351
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parents:
diff changeset
352 def write_init(self, outfile, size, already):
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parents:
diff changeset
353 pass
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parents:
diff changeset
354
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parents:
diff changeset
355 def consume_regs(self, program):
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parents:
diff changeset
356 pass
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parents:
diff changeset
357
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parents:
diff changeset
358 all_dregs = [Register('d', i) for i in range(0, 8)]
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parents:
diff changeset
359 all_aregs = [Register('a', i) for i in range(0, 8)]
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parents:
diff changeset
360 all_indirect = [Indirect(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
361 all_predec = [Decrement(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
362 all_postinc = [Increment(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
363 from random import randint
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
364 def all_indexed():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
365 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
366
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parents:
diff changeset
367 def all_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
368 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
369
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
370 def rand_pc_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
371 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
372
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
373 def all_pc_indexed():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
374 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
375
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
376 def rand_abs_short():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
377 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
378
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
379 def rand_abs_long():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
381
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
382 def get_size_range(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
383 if size == 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
384 return (-128, 127)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
385 elif size == 'w':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
386 return (-32768, 32767)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
387 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
388 return (-2147483648, 2147483647)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
390 def rand_immediate(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
391 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
392
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
393 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
394
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
395 def get_variations(mode, size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
396 mapping = {
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
397 'd':all_dregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398 'a':all_aregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
399 '(a)':all_indirect,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
400 '-(a)':all_predec,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
401 '(a)+':all_postinc,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
402 '(n,a)':all_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
403 '(n,a,x)':all_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
404 '(n,pc)':rand_pc_disp,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
405 '(n,pc,x)':all_pc_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
406 '(n).w':rand_abs_short,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
407 '(n).l':rand_abs_long
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
408 }
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409 if mode in mapping:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
410 ret = mapping[mode]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
411 if type(ret) != list:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
412 ret = ret()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413 return ret
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
414 elif mode == '#n':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
415 return rand_immediate(size)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
416 elif mode.startswith('#(') and mode.endswith(')'):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
417 inner = mode[2:-1]
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
418 start,sep,end = inner.rpartition('-')
220
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
419 start,end = int(start),int(end)
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
420 if end-start > 16:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
421 return [Immediate(randint(start, end)) for x in range(0,8)]
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
422 else:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 217
diff changeset
423 return [Immediate(num) for num in range(start, end+1)]
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
424 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
425 print "Don't know what to do with source type", mode
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
426 return None
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
427
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
428 class Inst2Op(object):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
429 def __init__(self, name, size, src, dst):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
430 self.name = name
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
431 self.size = size
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
432 self.src = src
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
433 self.dst = dst
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
434
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
435 def __str__(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
436 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
437
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
438 def write_init(self, outfile, already):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
439 self.src.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
440 self.dst.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
441
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
442 def invalidate_dest(self, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
443 if type(self.dst) == Register:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
444 del already[str(self.dst)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
445
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
446 def save_result(self, reg, always):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
447 if always or type(self.dst) != Register:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
448 if type(self.dst) == Decrement:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
449 src = Increment(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
450 elif type(self.dst) == Increment:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
451 src = Decrement(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
452 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
453 src = self.dst
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
454 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
455 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
456 return ''
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
457
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
458 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
459 self.src.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
460 self.dst.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
461
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
462 class Inst1Op(Inst2Op):
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
463 def __init__(self, name, size, dst):
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
464 super(Inst1Op, self).__init__(name, size, dummy_op, dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
465
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
466 def __str__(self):
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
467 return self.name + '.' + self.size + ' ' + str(self.dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
468
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
469 class Entry(object):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
470 def __init__(self, line):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
471 fields = split_fields(line)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
472 self.name = fields[0]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
473 sizes = fields[1]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
474 sources = fields[2].split(';')
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
475 if len(fields) > 3:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
476 dests = fields[3].split(';')
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
477 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
478 dests = None
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
479 combos = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
480 for size in sizes:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
481 for source in sources:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
482 if size != 'b' or source != 'a':
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
483 if dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
484 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
485 if size != 'b' or dest != 'a':
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
486 combos.append((size, source, dest))
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
487 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
488 combos.append((size, None, source))
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
489 self.cases = combos
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
490
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
491 def programs(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
492 res = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
493 for (size, src, dst) in self.cases:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
494 dests = get_variations(dst, size)
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
495 if src:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
496 sources = get_variations(src, size)
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
497 for source in sources:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
498 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
499 res.append(Program(Inst2Op(self.name, size, source, dest)))
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
500 else:
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
501 for dest in dests:
439
bfbb8613efb4 Add support for single operand instructions to 68K test generator
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
502 res.append(Program(Inst1Op(self.name, size, dest)))
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
503 return res
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
504
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
505 def process_entries(f):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
506 entries = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
507 for line in f:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
508 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
509 entries.append(Entry(line))
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
510 return entries
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
511
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
512 from os import path, mkdir
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
513 def main(args):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
514 entries = process_entries(open('testcases.txt'))
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
515 for entry in entries:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
516 programs = entry.programs()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
517 for program in programs:
224
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
518 dname = program.dirname()
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
519 if not path.exists('generated_tests/' + dname):
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
520 mkdir('generated_tests/' + dname)
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools.
Mike Pavone <pavone@retrodev.com>
parents: 220
diff changeset
521 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w')
214
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
522 program.write_rom_test(f)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
523 f.close()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
524
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
525 if __name__ == '__main__':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
526 import sys
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
527 main(sys.argv)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
528