repos/blastem: 68kinst.c annotate

annotate 68kinst.c @ 652:f822d9216968

Merge

author	Michael Pavone <pavone@retrodev.com>
date	Tue, 30 Dec 2014 19:11:34 -0800
parents	09d5adf8d1ca da52f7b72156
children	b1b5a7e7d955

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 412 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 412 diff changeset	2 Copyright 2013 Michael Pavone
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 412 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 412 diff changeset	5 */
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "68kinst.h"
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	7 #include <string.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	8 #include <stdio.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	9
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	10 uint32_t sign_extend16(uint32_t val)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	11 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	12 return (val & 0x8000) ? val \| 0xFFFF0000 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	13 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	14
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	15 uint32_t sign_extend8(uint32_t val)
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	17 return (val & 0x80) ? val \| 0xFFFFFF00 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	18 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	19
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	20 uint16_t m68k_decode_op_ex(uint16_t cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	21 {
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	22 uint16_t ext, tmp;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 dst->addr_mode = mode;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 switch(mode)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 case MODE_REG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 case MODE_AREG:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	28 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	29 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	30 case MODE_AREG_PREDEC:
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 dst->params.regs.pri = reg;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	33 case MODE_AREG_DISPLACE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	34 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	35 dst->params.regs.pri = reg;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	36 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	37 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	38 case MODE_AREG_INDEX_MEM:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	39 dst->params.regs.pri = reg;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	40 ext = *(++cur);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	41 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	42 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	43 dst->params.regs.scale = ext >> 9 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	44 if (ext & 0x100)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	45 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	46 dst->params.regs.disp_sizes = ext >> 4 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	47 switch (dst->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	48 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	49 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	50 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	51 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	52 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	53 dst->params.regs.displacement = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	54 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	55 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	56 dst->params.regs.displacement = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	57 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	58 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	59 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	60 dst->params.regs.displacement = tmp << 16 \| *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	61 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	62 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	63 if (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	64 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	65 //memory indirect
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	66 switch (ext & 0xC4)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	67 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	68 case 0x00:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	69 dst->addr_mode = MODE_AREG_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	70 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	71 case 0x04:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	72 dst->addr_mode = MODE_AREG_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	73 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	74 case 0x40:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	75 dst->addr_mode = MODE_AREG_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	76 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	77 case 0x80:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	78 dst->addr_mode = MODE_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	79 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	80 case 0x84:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	81 dst->addr_mode = MODE_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	82 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	83 case 0xC0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	84 dst->addr_mode = MODE_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	85 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	86 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	87 dst->params.regs.disp_sizes \|= ext << 4 & 0x30;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	88 switch (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	89 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	90 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	91 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	92 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	93 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	94 dst->params.regs.outer_disp = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	95 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	96 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	97 dst->params.regs.outer_disp = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	98 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	99 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	100 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	101 dst->params.regs.outer_disp = tmp << 16 \| *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	102 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	103 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	104 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	105 switch (ext >> 6 & 3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	106 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	107 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	108 dst->addr_mode = MODE_AREG_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	109 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	110 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	111 dst->addr_mode = MODE_AREG_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	112 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	113 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	114 dst->addr_mode = MODE_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	115 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	116 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	117 dst->addr_mode = MODE_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	118 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	119 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	120 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	121 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	122 #endif
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	123 dst->addr_mode = MODE_AREG_INDEX_DISP8;
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	124 dst->params.regs.displacement = sign_extend8(ext&0xFF);
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	125 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	126 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	127 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	128 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	129 case MODE_PC_INDIRECT_ABS_IMMED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	130 switch(reg)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	131 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	132 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	133 dst->addr_mode = MODE_ABSOLUTE_SHORT;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	134 ext = *(++cur);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	135 dst->params.immed = sign_extend16(ext);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	136 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	137 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	138 dst->addr_mode = MODE_ABSOLUTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	139 ext = *(++cur);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	140 dst->params.immed = ext << 16 \| *(++cur);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	141 break;
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	142 case 3:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	143 ext = *(++cur);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	144 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	145 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	146 dst->params.regs.scale = ext >> 9 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	147 if (ext & 0x100)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	148 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	149 dst->params.regs.disp_sizes = ext >> 4 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	150 switch (dst->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	151 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	152 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	153 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	154 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	155 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	156 dst->params.regs.displacement = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	157 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	158 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	159 dst->params.regs.displacement = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	160 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	161 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	162 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	163 dst->params.regs.displacement = tmp << 16 \| *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	164 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	165 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	166 if (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	167 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	168 //memory indirect
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	169 switch (ext & 0xC4)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	170 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	171 case 0x00:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	172 dst->addr_mode = MODE_PC_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	173 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	174 case 0x04:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	175 dst->addr_mode = MODE_PC_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	176 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	177 case 0x40:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	178 dst->addr_mode = MODE_PC_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	179 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	180 case 0x80:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	181 dst->addr_mode = MODE_ZPC_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	182 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	183 case 0x84:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	184 dst->addr_mode = MODE_ZPC_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	185 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	186 case 0xC0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	187 dst->addr_mode = MODE_ZPC_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	188 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	189 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	190 dst->params.regs.disp_sizes \|= ext << 4 & 0x30;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	191 switch (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	192 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	193 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	194 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	195 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	196 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	197 dst->params.regs.outer_disp = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	198 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	199 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	200 dst->params.regs.outer_disp = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	201 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	202 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	203 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	204 dst->params.regs.outer_disp = tmp << 16 \| *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	205 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	206 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	207 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	208 switch (ext >> 6 & 3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	209 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	210 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	211 dst->addr_mode = MODE_PC_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	212 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	213 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	214 dst->addr_mode = MODE_PC_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	215 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	216 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	217 dst->addr_mode = MODE_ZPC_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	218 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	219 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	220 dst->addr_mode = MODE_ZPC_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	221 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	222 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	223 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	224 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	225 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	226 dst->addr_mode = MODE_PC_INDEX_DISP8;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	227 dst->params.regs.displacement = sign_extend8(ext&0xFF);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	228 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	229 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	230 #endif
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 94 diff changeset	231 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	232 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	233 dst->addr_mode = MODE_PC_DISPLACE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	234 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	235 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	236 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	237 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	238 dst->addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	239 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	240 switch (size)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	241 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	242 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	243 dst->params.immed = ext & 0xFF;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	244 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	245 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	246 dst->params.immed = ext;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	247 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	248 case OPSIZE_LONG:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	249 dst->params.immed = ext << 16 \| *(++cur);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	250 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	251 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	252 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	253 default:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	254 return NULL;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	255 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	256 break;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	258 return cur;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	259 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	260
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	261 uint16_t m68k_decode_op(uint16_t cur, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	262 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	263 uint8_t mode = (*cur >> 3) & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	264 uint8_t reg = *cur & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	265 return m68k_decode_op_ex(cur, mode, reg, size, dst);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	266 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	267
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	268 void m68k_decode_cond(uint16_t op, m68kinst * decoded)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	269 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	270 decoded->extra.cond = (op >> 0x8) & 0xF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	271 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	272
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	273 uint8_t m68k_reg_quick_field(uint16_t op)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	274 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	275 return (op >> 9) & 0x7;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	276 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	277
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	278 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address)
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	279 {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	280 uint16_t *start = istream;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 uint8_t optype = *istream >> 12;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 uint8_t size;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	283 uint8_t reg;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	284 uint8_t opmode;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	285 uint32_t immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	286 decoded->op = M68K_INVALID;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	287 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	288 decoded->variant = VAR_NORMAL;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	289 decoded->address = address;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 switch(optype)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 case BIT_MOVEP_IMMED:
163 5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	293 if ((*istream & 0x138) == 0x108) {
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	294 //MOVEP
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	295 decoded->op = M68K_MOVEP;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	296 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	297 if (*istream & 0x80) {
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	298 //memory dest
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	299 decoded->src.addr_mode = MODE_REG;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	300 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	301 decoded->dst.addr_mode = MODE_AREG_DISPLACE;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	302 decoded->dst.params.regs.pri = *istream & 0x7;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	303 decoded->dst.params.regs.displacement = *(++istream);
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	304 } else {
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	305 //memory source
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	306 decoded->dst.addr_mode = MODE_REG;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	307 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	308 decoded->src.addr_mode = MODE_AREG_DISPLACE;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	309 decoded->src.params.regs.pri = *istream & 0x7;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	310 decoded->src.params.regs.displacement = *(++istream);
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	311 }
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	312 } else if (*istream & 0x100) {
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	313 //BTST, BCHG, BCLR, BSET
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	314 switch ((*istream >> 6) & 0x3)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	315 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	316 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	317 decoded->op = M68K_BTST;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	318 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	319 case 1:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	320 decoded->op = M68K_BCHG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	321 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	322 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	323 decoded->op = M68K_BCLR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	324 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	325 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	326 decoded->op = M68K_BSET;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	327 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	328 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	329 decoded->src.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	330 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	331 decoded->extra.size = OPSIZE_BYTE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	332 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	333 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	334 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	335 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	336 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	337 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	338 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	339 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	340 } else if ((*istream & 0xF00) == 0x800) {
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	341 //BTST, BCHG, BCLR, BSET
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	342 switch ((*istream >> 6) & 0x3)
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	343 {
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	344 case 0:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	345 decoded->op = M68K_BTST;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	346 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	347 case 1:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	348 decoded->op = M68K_BCHG;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	349 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	350 case 2:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	351 decoded->op = M68K_BCLR;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	352 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	353 case 3:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	354 decoded->op = M68K_BSET;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	355 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	356 }
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	357 opmode = (*istream >> 3) & 0x7;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	358 reg = *istream & 0x7;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	359 decoded->src.addr_mode = MODE_IMMEDIATE_WORD;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	360 decoded->src.params.immed = *(++istream) & 0xFF;
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	361 decoded->extra.size = OPSIZE_BYTE;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	362 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	363 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	364 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	365 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	366 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	367 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	368 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	369 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	370 } else if ((*istream & 0xC0) == 0xC0) {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	371 #ifdef M68020
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	372 //CMP2, CHK2, CAS, CAS2, RTM, CALLM
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	373 #endif
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	374 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	375 switch ((*istream >> 9) & 0x7)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	376 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	377 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	378 if ((*istream & 0xFF) == 0x3C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	379 decoded->op = M68K_ORI_CCR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	380 decoded->extra.size = OPSIZE_BYTE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	381 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	382 decoded->src.params.immed = *(++istream) & 0xFF;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	383 } else if((*istream & 0xFF) == 0x7C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	384 decoded->op = M68K_ORI_SR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	385 decoded->extra.size = OPSIZE_WORD;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	386 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	387 decoded->src.params.immed = *(++istream);
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	388 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	389 decoded->op = M68K_OR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	390 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	391 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	392 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	393 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	394 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	395 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	396 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	397 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	398 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	399 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	400 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	401 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	402 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	403 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	404 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	405 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	406 break;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	407 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	408 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	409 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	410 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	411 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	412 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	413 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	414 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	415 case 1:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	416 //ANDI, ANDI to CCR, ANDI to SR
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	417 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	418 decoded->op = M68K_ANDI_CCR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	419 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	420 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	421 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	422 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	423 decoded->op = M68K_ANDI_SR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	424 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	425 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	426 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	427 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	428 decoded->op = M68K_AND;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	429 decoded->variant = VAR_IMMEDIATE;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	430 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	431 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	432 reg = *istream & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	433 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	434 switch (size)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	435 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	436 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	437 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	438 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	439 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	440 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	441 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	442 case OPSIZE_LONG:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	443 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	444 decoded->src.params.immed = immed << 16 \| *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	445 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	446 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	447 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	448 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	449 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	450 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	451 }
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	452 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	453 break;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	454 case 2:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	455 decoded->op = M68K_SUB;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	456 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	457 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	458 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	459 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	460 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	461 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	462 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	463 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	464 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	465 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	466 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	467 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	468 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	469 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	470 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	471 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	472 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	473 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	474 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	475 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	476 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	477 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	478 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	479 break;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	480 case 3:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	481 decoded->op = M68K_ADD;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	482 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	483 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	484 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	485 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	486 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	487 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	488 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	489 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	490 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	491 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	492 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	493 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	494 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	495 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	496 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	497 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	498 break;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	499 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	500 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	501 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	502 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	503 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	504 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	505 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	506 case 4:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	507 //BTST, BCHG, BCLR, BSET
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	508 switch ((*istream >> 6) & 0x3)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	509 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	510 case 0:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	511 decoded->op = M68K_BTST;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	512 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	513 case 1:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	514 decoded->op = M68K_BCHG;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	515 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	516 case 2:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	517 decoded->op = M68K_BCLR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	518 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	519 case 3:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	520 decoded->op = M68K_BSET;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	521 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	522 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	523 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	524 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	525 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	526 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	527 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	528 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	529 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	530 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	531 case 5:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	532 //EORI, EORI to CCR, EORI to SR
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	533 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	534 decoded->op = M68K_EORI_CCR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	535 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	536 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	537 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	538 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	539 decoded->op = M68K_EORI_SR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	540 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	541 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	542 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	543 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	544 decoded->op = M68K_EOR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	545 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	546 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	547 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	548 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	549 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	550 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	551 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	552 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	553 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	554 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	555 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	556 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	557 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	558 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	559 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	560 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	561 break;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	562 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	563 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	564 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	565 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	566 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	567 }
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	568 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	569 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	570 case 6:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	571 decoded->op = M68K_CMP;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	572 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	573 decoded->extra.size = (*istream >> 6) & 0x3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	574 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	575 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	576 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	577 switch (decoded->extra.size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	578 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	579 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	580 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	581 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	582 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	583 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	584 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	585 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	586 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	587 decoded->src.params.immed = (immed << 16) \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	588 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	589 }
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	590 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	591 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	592 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	593 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	594 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	595 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	596 case 7:
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	597 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	598 decoded->op = M68K_MOVES;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	599 decoded->extra.size = *istream >> 6 & 0x3;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	600 immed = *(++istream);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	601 reg = immed >> 12 & 0x7;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	602 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	603 if (immed & 0x800) {
642 08d0e3e7d0d8 Fix interpretation of moves direction field Michael Pavone <pavone@retrodev.com> parents: 641 diff changeset	604 decoded->src.addr_mode = opmode;
08d0e3e7d0d8 Fix interpretation of moves direction field Michael Pavone <pavone@retrodev.com> parents: 641 diff changeset	605 decoded->src.params.regs.pri = reg;
08d0e3e7d0d8 Fix interpretation of moves direction field Michael Pavone <pavone@retrodev.com> parents: 641 diff changeset	606 m68k_decode_op_ex(istream, start >> 3 & 0x7, start & 0x7, decoded->extra.size, &(decoded->dst));
08d0e3e7d0d8 Fix interpretation of moves direction field Michael Pavone <pavone@retrodev.com> parents: 641 diff changeset	607 } else {
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	608 m68k_decode_op_ex(istream, start >> 3 & 0x7, start & 0x7, decoded->extra.size, &(decoded->src));
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	609 decoded->dst.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	610 decoded->dst.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	611 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	612 #endif
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	613 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	614 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	615 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	616 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	617 case MOVE_BYTE:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	618 case MOVE_LONG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	619 case MOVE_WORD:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	620 decoded->op = M68K_MOVE;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	621 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	622 opmode = (*istream >> 6) & 0x7;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	623 reg = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	624 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	625 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	626 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	627 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	628 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	629 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
197 7c227a8ec53d Add instruction address logging to translator and support for reading an address log to the disassembler Mike Pavone <pavone@retrodev.com> parents: 184 diff changeset	630 if (!istream \|\| decoded->dst.addr_mode == MODE_IMMEDIATE) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	631 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	632 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	633 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	634 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	635 case MISC:
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	636
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	637 if ((*istream & 0x1C0) == 0x1C0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	638 decoded->op = M68K_LEA;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	639 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	640 decoded->dst.addr_mode = MODE_AREG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	641 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	642 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	643 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	644 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	645 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	646 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	647 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	648 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	649 decoded->op = M68K_CHK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	650 if ((*istream & 0x180) == 0x180) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	651 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	652 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	653 //only on M68020+
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	654 #ifdef M68020
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	655 decoded->extra.size = OPSIZE_LONG;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	656 #else
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	657 decoded->op = M68K_INVALID;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	658 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	659 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	660 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	661 decoded->dst.addr_mode = MODE_REG;
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	662 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	663 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	664 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	665 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	666 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	667 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	668 } else {
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	669 opmode = (*istream >> 3) & 0x7;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	670 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	671 //TODO: Check for invalid modes that are dependent on direction
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	672 decoded->op = M68K_MOVEM;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	673 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	674 reg = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	675 if(*istream & 0x400) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	676 decoded->dst.addr_mode = MODE_REG;
68 1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	677 decoded->dst.params.immed = *(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	678 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	679 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	680 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	681 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	682 }
412 00d5a2b532f4 Fix movem with pc displacement or pc indexed source Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	683 if (decoded->src.addr_mode == MODE_PC_DISPLACE \|\| decoded->src.addr_mode == MODE_PC_INDEX_DISP8) {
00d5a2b532f4 Fix movem with pc displacement or pc indexed source Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	684 //adjust displacement to account for extra instruction word
00d5a2b532f4 Fix movem with pc displacement or pc indexed source Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	685 decoded->src.params.regs.displacement += 2;
00d5a2b532f4 Fix movem with pc displacement or pc indexed source Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	686 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	687 } else {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	688 decoded->src.addr_mode = MODE_REG;
68 1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	689 decoded->src.params.immed = *(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	690 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	691 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	692 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	693 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	694 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	695 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	696 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	697 optype = (*istream >> 9) & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	698 size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	699 switch(optype)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	700 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	701 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	702 //Move from SR or NEGX
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	703 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	704 decoded->op = M68K_MOVE_FROM_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	705 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	706 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	707 decoded->op = M68K_NEGX;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	708 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	709 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	710 istream= m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	711 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	712 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	713 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	714 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	715 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	716 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	717 //MOVE from CCR or CLR
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	718 if (size == OPSIZE_INVALID) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	719 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	720 decoded->op = M68K_MOVE_FROM_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	721 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	722 #else
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	723 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	724 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	725 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	726 decoded->op = M68K_CLR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	727 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	728 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	729 istream= m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	730 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	731 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	732 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	733 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	734 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	735 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	736 //MOVE to CCR or NEG
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	737 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	738 decoded->op = M68K_MOVE_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	739 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	740 istream= m68k_decode_op(istream, size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	741 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	742 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	743 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	744 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	745 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	746 decoded->op = M68K_NEG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	747 istream= m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	748 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	749 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	750 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	751 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	752 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	753 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	754 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	755 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	756 //MOVE to SR or NOT
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	757 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	758 decoded->op = M68K_MOVE_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	759 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	760 istream= m68k_decode_op(istream, size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	761 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	762 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	763 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	764 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	765 } else {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	766 decoded->op = M68K_NOT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	767 istream= m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	768 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	769 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	770 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	771 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	772 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	773 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	774 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	775 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	776 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	777 switch((*istream >> 3) & 0x3F)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	778 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	779 case 1:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	780 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	781 decoded->op = M68K_LINK;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	782 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	783 reg = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	784 immed = *(++istream) << 16;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	785 immed \|= *(++istream);
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	786 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	787 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	788 case 8:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	789 decoded->op = M68K_SWAP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	790 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	791 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	792 decoded->extra.size = OPSIZE_WORD;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	793 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	794 case 9:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	795 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	796 decoded->op = M68K_BKPT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	797 decoded->src.addr_mode = MODE_IMMEDIATE;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	798 decoded->extra.size = OPSIZE_UNSIZED;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	799 decoded->src.params.immed = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	800 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	801 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	802 case 0x10:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	803 decoded->op = M68K_EXT;
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	804 decoded->dst.addr_mode = MODE_REG;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	805 decoded->dst.params.regs.pri = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	806 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	807 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	808 case 0x18:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	809 decoded->op = M68K_EXT;
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	810 decoded->dst.addr_mode = MODE_REG;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	811 decoded->dst.params.regs.pri = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	812 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	813 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	814 case 0x38:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	815 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	816 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	817 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	818 default:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	819 if (!(*istream & 0x1C0)) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	820 decoded->op = M68K_NBCD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	821 decoded->extra.size = OPSIZE_BYTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	822 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	823 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	824 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	825 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	826 }
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	827 } else if((*istream & 0x1C0) == 0x40) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	828 decoded->op = M68K_PEA;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	829 decoded->extra.size = OPSIZE_LONG;
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 111 diff changeset	830 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	831 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	832 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	833 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	834 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	835 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	836 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	837 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	838 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	839 //BGND, ILLEGAL, TAS, TST
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	840 optype = *istream & 0xFF;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	841 if (optype == 0xFA) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	842 //BGND - CPU32 only
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	843 } else if (optype == 0xFC) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	844 decoded->op = M68K_ILLEGAL;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	845 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	846 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	847 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	848 decoded->op = M68K_TAS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	849 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	850 decoded->op = M68K_TST;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	851 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	852 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	853 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	854 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	855 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	856 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	857 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	858 }
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	859 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	860 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	861 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	862 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	863 //TODO: Implement these for 68020+ support
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	864 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	865 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	866 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	867 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	868 if (*istream & 0x80) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	869 //JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	870 if (*istream & 0x40) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	871 decoded->op = M68K_JMP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	872 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	873 decoded->op = M68K_JSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	874 }
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	875 decoded->extra.size = OPSIZE_UNSIZED;
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	876 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	877 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	878 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	879 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	880 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	881 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	882 //it would appear bit 6 needs to be set for it to be a valid instruction here
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	883 switch((*istream >> 3) & 0x7)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	884 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	885 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	886 case 1:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	887 //TRAP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	888 decoded->op = M68K_TRAP;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	889 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	890 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	891 decoded->src.params.immed = *istream & 0xF;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	892 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	893 case 2:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	894 //LINK.w
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	895 decoded->op = M68K_LINK;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	896 decoded->extra.size = OPSIZE_WORD;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	897 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	898 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	899 decoded->dst.addr_mode = MODE_IMMEDIATE;
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	900 decoded->dst.params.immed = sign_extend16(*(++istream));
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	901 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	902 case 3:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	903 //UNLK
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	904 decoded->op = M68K_UNLK;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	905 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	906 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	907 decoded->dst.params.regs.pri = *istream & 0x7;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	908 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	909 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	910 case 5:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	911 //MOVE USP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	912 decoded->op = M68K_MOVE_USP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	913 if (*istream & 0x8) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	914 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	915 decoded->dst.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	916 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	917 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	918 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	919 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	920 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	921 case 6:
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	922 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	923 switch(*istream & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	924 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	925 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	926 decoded->op = M68K_RESET;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	927 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	928 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	929 decoded->op = M68K_NOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	930 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	931 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	932 decoded->op = M68K_STOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	933 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	934 decoded->src.params.immed =*(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	935 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	936 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	937 decoded->op = M68K_RTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	938 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	939 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	940 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	941 decoded->op = M68K_RTD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	942 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	943 decoded->src.params.immed =*(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	944 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	945 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	946 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	947 decoded->op = M68K_RTS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	948 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	949 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	950 decoded->op = M68K_TRAPV;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	951 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	952 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	953 decoded->op = M68K_RTR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	954 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	955 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	956 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	957 case 7:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	958 //MOVEC
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	959 #ifdef M68010
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	960 decoded->op = M68K_MOVEC;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	961 immed = *(++istream);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	962 reg = immed >> 12 & 0x7;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	963 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG;
641 66857bd2df0b Fix decoding of movec Michael Pavone <pavone@retrodev.com> parents: 638 diff changeset	964 immed &= 0xFFF;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	965 if (immed & 0x800) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	966 if (immed > MAX_HIGH_CR) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	967 decoded->op = M68K_INVALID;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	968 break;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	969 } else {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	970 immed = immed - 0x800 + CR_USP;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	971 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	972 } else {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	973 if (immed > MAX_LOW_CR) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	974 decoded->op = M68K_INVALID;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	975 break;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	976 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	977 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	978 if (*start & 1) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	979 decoded->src.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	980 decoded->src.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	981 decoded->dst.params.immed = immed;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	982 } else {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	983 decoded->dst.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	984 decoded->dst.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	985 decoded->src.params.immed = immed;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	986 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	987 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	988 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	989 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	990 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	991 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	992 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	993 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	994 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	995 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	996 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	997 case QUICK_ARITH_LOOP:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	998 size = (*istream >> 6) & 3;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	999 if (size == 0x3) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1000 //DBcc, TRAPcc or Scc
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1001 m68k_decode_cond(*istream, decoded);
111 8b50d2c975b2 Fix decoding of Scc Mike Pavone <pavone@retrodev.com> parents: 101 diff changeset	1002 if (((*istream >> 3) & 0x7) == 1) {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1003 decoded->op = M68K_DBCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1004 decoded->src.addr_mode = MODE_IMMEDIATE;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1005 decoded->dst.addr_mode = MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1006 decoded->dst.params.regs.pri = *istream & 0x7;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1007 decoded->src.params.immed = sign_extend16(*(++istream));
111 8b50d2c975b2 Fix decoding of Scc Mike Pavone <pavone@retrodev.com> parents: 101 diff changeset	1008 } else if(((istream >> 3) & 0x7) == 1 && (istream & 0x7) > 1 && (*istream & 0x7) < 5) {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1009 #ifdef M68020
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1010 decoded->op = M68K_TRAPCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1011 decoded->src.addr_mode = MODE_IMMEDIATE;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1012 //TODO: Figure out what to do with OPMODE and optional extention words
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1013 #endif
111 8b50d2c975b2 Fix decoding of Scc Mike Pavone <pavone@retrodev.com> parents: 101 diff changeset	1014 } else {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1015 decoded->op = M68K_SCC;
111 8b50d2c975b2 Fix decoding of Scc Mike Pavone <pavone@retrodev.com> parents: 101 diff changeset	1016 decoded->extra.cond = (*istream >> 8) & 0xF;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1017 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1018 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1019 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1020 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1021 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1022 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1023 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1024 //ADDQ, SUBQ
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1025 decoded->variant = VAR_QUICK;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1026 decoded->extra.size = size;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1027 decoded->src.addr_mode = MODE_IMMEDIATE;
91 8c446fc19cc0 Fix decoding bug in addq/subq Mike Pavone <pavone@retrodev.com> parents: 90 diff changeset	1028 immed = m68k_reg_quick_field(*istream);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1029 if (!immed) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1030 immed = 8;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1031 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1032 decoded->src.params.immed = immed;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1033 if (*istream & 0x100) {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1034 decoded->op = M68K_SUB;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1035 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1036 decoded->op = M68K_ADD;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1037 }
94 a668a35a3463 Fix decoding bug for addq/subq Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1038 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1039 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1040 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1041 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1042 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1043 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1044 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1045 case BRANCH:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1046 m68k_decode_cond(*istream, decoded);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1047 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1048 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1049 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1050 if (immed == 0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1051 decoded->variant = VAR_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1052 immed = *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1053 immed = sign_extend16(immed);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 140 diff changeset	1054 #ifdef M68020
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1055 } else if (immed == 0xFF) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1056 decoded->variant = VAR_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1057 immed = *(++istream) << 16;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1058 immed \|= *(++istream);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 140 diff changeset	1059 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1060 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1061 decoded->variant = VAR_BYTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1062 immed = sign_extend8(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1063 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1064 decoded->src.params.immed = immed;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1065 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1066 case MOVEQ:
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	1067 if (*istream & 0x100) {
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	1068 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1069 break;
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	1070 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1071 decoded->op = M68K_MOVE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1072 decoded->variant = VAR_QUICK;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1073 decoded->extra.size = OPSIZE_LONG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1074 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1075 decoded->src.params.immed = sign_extend8(*istream & 0xFF);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1076 decoded->dst.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1077 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1078 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1079 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1080 case OR_DIV_SBCD:
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1081 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea>
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1082 opmode = (*istream >> 6) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1083 size = opmode & 0x3;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1084 if (size == OPSIZE_INVALID \|\| (opmode & 0x4 && !(*istream & 0x30))) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1085 switch(opmode)
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1086 {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1087 case 3:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1088 decoded->op = M68K_DIVU;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1089 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1090 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1091 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1092 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
183 2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid Mike Pavone <pavone@retrodev.com> parents: 181 diff changeset	1093 if (!istream \|\| decoded->src.addr_mode == MODE_AREG) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1094 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1095 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1096 }
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1097 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1098 case 4:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1099 decoded->op = M68K_SBCD;
613 09d5adf8d1ca Fix opsize for sbcd in 68K instruction decoder. This fixes the timer bug in Strider 2 Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1100 decoded->extra.size = OPSIZE_BYTE;
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1101 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1102 decoded->src.params.regs.pri = *istream & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1103 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1104 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1105 case 5:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1106 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1107 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1108 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1109 case 6:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1110 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1111 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1112 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1113 case 7:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1114 decoded->op = M68K_DIVS;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1115 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1116 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1117 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1118 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
183 2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid Mike Pavone <pavone@retrodev.com> parents: 181 diff changeset	1119 if (!istream \|\| decoded->src.addr_mode == MODE_AREG) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1120 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1121 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1122 }
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1123 break;
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1124 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1125 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1126 decoded->op = M68K_OR;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1127 decoded->extra.size = size;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1128 if (opmode & 0x4) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1129 decoded->src.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1130 decoded->src.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1131 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1132 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1133 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1134 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1135 }
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1136 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1137 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1138 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1139 istream = m68k_decode_op(istream, size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1140 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1141 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1142 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1143 }
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1144 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1145 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1146 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1147 case SUB_SUBX:
101 d7789186ba5e Some fixes to add/addx sub/subx decoding Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	1148 size = (*istream >> 6) & 0x3;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1149 decoded->op = M68K_SUB;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1150 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1151 //<ea> destination, SUBA.l or SUBX
101 d7789186ba5e Some fixes to add/addx sub/subx decoding Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	1152 if (*istream & 0x30 \|\| size == OPSIZE_INVALID) {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1153 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1154 //SUBA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1155 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1156 decoded->dst.addr_mode = MODE_AREG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1157 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1158 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1159 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1160 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1161 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1162 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1163 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1164 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1165 decoded->src.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1166 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1167 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1168 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1169 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1170 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1171 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1172 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1173 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1174 //SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1175 decoded->op = M68K_SUBX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1176 decoded->extra.size = size;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1177 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1178 decoded->src.params.regs.pri = *istream & 0x7;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1179 if (*istream & 0x8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1180 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1181 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1182 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1183 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1184 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1185 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1186 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1187 //SUBA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1188 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1189 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1190 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1191 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1192 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1193 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1194 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1195 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1196 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1197 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1198 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1199 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1200 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1201 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1202 case RESERVED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1203 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1204 case CMP_XOR:
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1205 size = (*istream >> 6) & 0x3;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1206 decoded->op = M68K_CMP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1207 if (*istream & 0x100) {
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1208 //CMPM or CMPA.l or EOR
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1209 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1210 decoded->extra.size = OPSIZE_LONG;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1211 decoded->dst.addr_mode = MODE_AREG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1212 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
136 e64554246d11 Fix some bugs in decoding cmp Mike Pavone <pavone@retrodev.com> parents: 134 diff changeset	1213 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1214 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1215 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1216 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1217 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1218 } else {
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1219 reg = m68k_reg_quick_field(*istream);
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1220 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1221 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1222 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1223 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1224 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	1225 decoded->extra.size = size;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	1226 if (decoded->dst.addr_mode == MODE_AREG) {
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1227 //CMPM
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1228 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1229 decoded->src.params.regs.pri = decoded->dst.params.regs.pri;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1230 decoded->dst.params.regs.pri = reg;
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1231 } else {
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1232 //EOR
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1233 decoded->op = M68K_EOR;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1234 decoded->src.addr_mode = MODE_REG;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1235 decoded->src.params.regs.pri = reg;
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1236 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1237 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1238 } else {
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1239 //CMP or CMPA.w
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1240 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1241 decoded->extra.size = OPSIZE_WORD;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1242 decoded->dst.addr_mode = MODE_AREG;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1243 } else {
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1244 decoded->extra.size = size;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1245 decoded->dst.addr_mode = MODE_REG;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1246 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1247 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
136 e64554246d11 Fix some bugs in decoding cmp Mike Pavone <pavone@retrodev.com> parents: 134 diff changeset	1248 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1249 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1250 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1251 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1252 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1253 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1254 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1255 case AND_MUL_ABCD_EXG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1256 //page 575 for summary
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1257 //EXG opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1258 //01000 -data regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1259 //01001 -addr regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1260 //10001 -one of each
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1261 //AND opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1262 //operand order bit + 2 size bits (00 - 10)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1263 //no address register direct addressing
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1264 //data register direct not allowed when <ea> is the source (operand order bit of 1)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1265 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1266 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1267 decoded->op = M68K_MULS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1268 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1269 decoded->dst.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1270 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1271 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1272 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1273 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1274 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1275 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1276 } else if(!(*istream & 0xF0)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1277 decoded->op = M68K_ABCD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1278 decoded->extra.size = OPSIZE_BYTE;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1279 decoded->src.params.regs.pri = *istream & 0x7;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1280 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1281 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1282 } else if(!(*istream & 0x30)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1283 decoded->op = M68K_EXG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1284 decoded->extra.size = OPSIZE_LONG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1285 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1286 decoded->dst.params.regs.pri = *istream & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1287 if (*istream & 0x8) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1288 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1289 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1290 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1291 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1292 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1293 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1294 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1295 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1296 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1297 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1298 decoded->op = M68K_AND;
90 645fe435cb48 Fix decoding of and Mike Pavone <pavone@retrodev.com> parents: 79 diff changeset	1299 decoded->extra.size = (*istream >> 6) & 0x3;
60 6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1300 decoded->src.addr_mode = MODE_REG;
6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1301 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1302 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1303 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1304 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1305 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1306 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1307 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1308 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1309 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1310 decoded->op = M68K_MULU;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1311 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1312 decoded->dst.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1313 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1314 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1315 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1316 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1317 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1318 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1319 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1320 decoded->op = M68K_AND;
90 645fe435cb48 Fix decoding of and Mike Pavone <pavone@retrodev.com> parents: 79 diff changeset	1321 decoded->extra.size = (*istream >> 6) & 0x3;
60 6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1322 decoded->dst.addr_mode = MODE_REG;
6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1323 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1324 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1325 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1326 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1327 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1328 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1329 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1330 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1331 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1332 case ADD_ADDX:
101 d7789186ba5e Some fixes to add/addx sub/subx decoding Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	1333 size = (*istream >> 6) & 0x3;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1334 decoded->op = M68K_ADD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1335 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1336 //<ea> destination, ADDA.l or ADDX
101 d7789186ba5e Some fixes to add/addx sub/subx decoding Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	1337 if (*istream & 0x30 \|\| size == OPSIZE_INVALID) {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1338 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1339 //ADDA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1340 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1341 decoded->dst.addr_mode = MODE_AREG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1342 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1343 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1344 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1345 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1346 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1347 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1348 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1349 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1350 decoded->src.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1351 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1352 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1353 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1354 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1355 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1356 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1357 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1358 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1359 //ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1360 decoded->op = M68K_ADDX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1361 decoded->extra.size = size;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1362 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1363 decoded->src.params.regs.pri = *istream & 0x7;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1364 if (*istream & 0x8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1365 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1366 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1367 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1368 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1369 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1370 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1371 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1372 //ADDA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1373 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1374 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1375 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1376 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1377 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1378 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1379 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1380 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1381 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1382 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1383 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1384 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1385 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1386 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1387 case SHIFT_ROTATE:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1388 if ((*istream & 0x8C0) == 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1389 switch((*istream >> 8) & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1390 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1391 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1392 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1393 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1394 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1395 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1396 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1397 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1398 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1399 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1400 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1401 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1402 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1403 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1404 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1405 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1406 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1407 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1408 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1409 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1410 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1411 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1412 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1413 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1414 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1415 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1416 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1417 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1418 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1419 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1420 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1421 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1422 } else if((*istream & 0xC0) != 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1423 switch(((istream >> 2) & 0x6) \| ((istream >> 8) & 1))
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1424 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1425 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1426 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1427 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1428 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1429 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1430 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1431 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1432 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1433 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1434 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1435 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1436 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1437 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1438 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1439 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1440 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1441 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1442 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1443 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1444 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1445 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1446 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1447 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1448 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1449 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1450 decoded->extra.size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1451 immed = (*istream >> 9) & 0x7;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 50 diff changeset	1452 if (*istream & 0x20) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1453 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1454 decoded->src.params.regs.pri = immed;
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1455 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1456 decoded->src.addr_mode = MODE_IMMEDIATE;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1457 if (!immed) {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1458 immed = 8;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1459 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1460 decoded->src.params.immed = immed;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1461 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1462 decoded->dst.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1463 decoded->dst.params.regs.pri = *istream & 0x7;
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1464
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1465 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1466 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1467 //TODO: Implement bitfield instructions for M68020+ support
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1468 switch (*istream >> 8 & 7)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1469 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1470 case 0:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1471 decoded->op = M68K_BFTST; //<ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1472 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1473 case 1:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1474 decoded->op = M68K_BFEXTU; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1475 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1476 case 2:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1477 decoded->op = M68K_BFCHG; //<ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1478 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1479 case 3:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1480 decoded->op = M68K_BFEXTS; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1481 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1482 case 4:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1483 decoded->op = M68K_BFCLR; //<ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1484 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1485 case 5:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1486 decoded->op = M68K_BFFFO; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1487 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1488 case 6:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1489 decoded->op = M68K_BFSET; //<ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1490 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1491 case 7:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1492 decoded->op = M68K_BFINS; //Dn, <ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1493 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1494 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1495 opmode = *istream >> 3 & 0x7;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1496 reg = *istream & 0x7;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1497 m68k_op_info ea, other;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1498 if (decoded->op == M68K_BFEXTU \|\| decoded->op == M68K_BFEXTS \|\| decoded->op == M68K_BFFFO)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1499 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1500 ea = &(decoded->src);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1501 other = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1502 } else {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1503 ea = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1504 other = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1505 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1506 if (*istream & 0x100)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1507 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1508 immed = *(istream++);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1509 other->addr_mode = MODE_REG;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1510 other->params.regs.pri = immed >> 12 & 0x7;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1511 } else {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1512 immed = *(istream++);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1513 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1514 decoded->extra.size = OPSIZE_UNSIZED;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1515 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, ea);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1516 ea->addr_mode \|= M68K_FLAG_BITFIELD;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1517 ea->bitfield = immed & 0xFFF;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1518 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1519 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1520 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1521 case COPROC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1522 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1523 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1524 }
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1525 if (decoded->op == M68K_INVALID) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1526 decoded->src.params.immed = *start;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1527 return start + 1;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1528 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1529 return istream+1;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1530 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1531
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1532 uint32_t m68k_branch_target(m68kinst * inst, uint32_t dregs, uint32_t aregs)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1533 {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1534 if(inst->op == M68K_BCC \|\| inst->op == M68K_BSR \|\| inst->op == M68K_DBCC) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1535 return inst->address + 2 + inst->src.params.immed;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1536 } else if(inst->op == M68K_JMP \|\| inst->op == M68K_JSR) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1537 uint32_t ret = 0;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1538 switch(inst->src.addr_mode)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1539 {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1540 case MODE_AREG_INDIRECT:
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1541 ret = aregs[inst->src.params.regs.pri];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1542 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1543 case MODE_AREG_INDEX_DISP8: {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1544 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1545 ret = aregs[inst->src.params.regs.pri];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1546 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1547 if (inst->src.params.regs.sec & 1) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1548 //32-bit index register
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1549 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1550 } else {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1551 //16-bit index register
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1552 if (regfile[sec_reg] & 0x8000) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1553 ret += (0xFFFF0000 \| regfile[sec_reg]);
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1554 } else {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1555 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1556 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1557 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1558 ret += inst->src.params.regs.displacement;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1559 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1560 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1561 case MODE_PC_DISPLACE:
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1562 ret = inst->src.params.regs.displacement + inst->address + 2;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1563 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1564 case MODE_PC_INDEX_DISP8: {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1565 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1566 ret = inst->address + 2;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1567 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1568 if (inst->src.params.regs.sec & 1) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1569 //32-bit index register
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1570 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1571 } else {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1572 //16-bit index register
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1573 if (regfile[sec_reg] & 0x8000) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1574 ret += (0xFFFF0000 \| regfile[sec_reg]);
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1575 } else {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1576 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1577 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1578 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1579 ret += inst->src.params.regs.displacement;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1580 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1581 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1582 case MODE_ABSOLUTE:
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1583 case MODE_ABSOLUTE_SHORT:
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1584 ret = inst->src.params.immed;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1585 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1586 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1587 return ret;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1588 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1589 return 0;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1590 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1591
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1592 uint8_t m68k_is_branch(m68kinst * inst)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1593 {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1594 return (inst->op == M68K_BCC && inst->extra.cond != COND_FALSE)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1595 \|\| (inst->op == M68K_DBCC && inst->extra.cond != COND_TRUE)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1596 \|\| inst->op == M68K_BSR \|\| inst->op == M68K_JMP \|\| inst->op == M68K_JSR;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1597 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1598
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1599 uint8_t m68k_is_noncall_branch(m68kinst * inst)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1600 {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1601 return m68k_is_branch(inst) && inst->op != M68K_BSR && inst->op != M68K_JSR;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1602 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1603
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1604
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1605 char * mnemonics[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1606 "abcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1607 "add",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1608 "addx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1609 "and",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1610 "andi",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1611 "andi",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1612 "asl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1613 "asr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1614 "bcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1615 "bchg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1616 "bclr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1617 "bset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1618 "bsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1619 "btst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1620 "chk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1621 "clr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1622 "cmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1623 "dbcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1624 "divs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1625 "divu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1626 "eor",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1627 "eori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1628 "eori",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1629 "exg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1630 "ext",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1631 "illegal",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1632 "jmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1633 "jsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1634 "lea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1635 "link",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1636 "lsl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1637 "lsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1638 "move",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1639 "move",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1640 "move",//from_sr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1641 "move",//sr
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1642 "move",//usp
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1643 "movem",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1644 "movep",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1645 "muls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1646 "mulu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1647 "nbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1648 "neg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1649 "negx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1650 "nop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1651 "not",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1652 "or",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1653 "ori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1654 "ori",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1655 "pea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1656 "reset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1657 "rol",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1658 "ror",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1659 "roxl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1660 "roxr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1661 "rte",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1662 "rtr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1663 "rts",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1664 "sbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1665 "scc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1666 "stop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1667 "sub",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1668 "subx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1669 "swap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1670 "tas",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1671 "trap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1672 "trapv",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1673 "tst",
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	1674 "unlk",
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1675 "invalid",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1676 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1677 "bkpt",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1678 "move", //from ccr
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1679 "movec",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1680 "moves",
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1681 "rtd",
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1682 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1683 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1684 "bfchg",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1685 "bfclr",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1686 "bfexts",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1687 "bfextu",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1688 "bfffo",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1689 "bfins",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1690 "bfset",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1691 "bftst",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1692 "callm",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1693 "cas",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1694 "cas2",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1695 "chk2",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1696 "cmp2",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1697 "cpbcc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1698 "cpdbcc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1699 "cpgen",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1700 "cprestore",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1701 "cpsave",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1702 "cpscc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1703 "cptrapcc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1704 "divsl",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1705 "divul",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1706 "extb",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1707 "pack",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1708 "rtm",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1709 "trapcc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1710 "unpk"
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1711 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1712 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1713
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1714 char * cond_mnem[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1715 "ra",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1716 "f",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1717 "hi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1718 "ls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1719 "cc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1720 "cs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1721 "ne",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1722 "eq",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1723 "vc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1724 "vs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1725 "pl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1726 "mi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1727 "ge",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1728 "lt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1729 "gt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1730 "le"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1731 };
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1732 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1733 char * cr_mnem[] = {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1734 "SFC",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1735 "DFC",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1736 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1737 "CACR",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1738 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1739 "USP",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1740 "VBR",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1741 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1742 "CAAR",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1743 "MSP",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1744 "ISP"
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1745 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1746 };
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1747 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1748
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	1749 int m68k_disasm_op(m68k_op_info decoded, char dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1750 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1751 char * c = need_comma ? "," : "";
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1752 int ret = 0;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1753 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1754 uint8_t addr_mode = decoded->addr_mode & (~M68K_FLAG_BITFIELD);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1755 #else
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1756 uint8_t addr_mode = decoded->addr_mode;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1757 #endif
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1758 switch(addr_mode)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1759 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1760 case MODE_REG:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1761 ret = sprintf(dst, "%s d%d", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1762 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1763 case MODE_AREG:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1764 ret = sprintf(dst, "%s a%d", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1765 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1766 case MODE_AREG_INDIRECT:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1767 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1768 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1769 case MODE_AREG_POSTINC:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1770 ret = sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1771 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1772 case MODE_AREG_PREDEC:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1773 ret = sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1774 break;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1775 case MODE_AREG_DISPLACE:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1776 ret = sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1777 break;
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	1778 case MODE_AREG_INDEX_DISP8:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1779 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1780 if (decoded->params.regs.scale)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1781 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1782 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1783 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1784 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1785 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1786 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1787 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1788 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1789 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1790 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1791 case MODE_AREG_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1792 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1793 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1794 ret = sprintf(dst, "%s (%d.%c, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1795 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1796 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1797 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1798 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1799 ret = sprintf(dst, "%s (a%d, %c%d.%c*%d)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1800 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1801 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1802 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1803 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1804 case MODE_AREG_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1805 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1806 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1807 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1808 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1809 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d])", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1810 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1811 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1812 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1813 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1814 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1815 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1816 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1817 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1818 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1819 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1820 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1821 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1822 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1823 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1824 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1825 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1826 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1827 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1828 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1829 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1830 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1831 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1832 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1833 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1834 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1835 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1836 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1837 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1838 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1839 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1840 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1841 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1842 case MODE_AREG_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1843 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1844 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1845 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1846 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1847 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1848 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1849 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1850 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1851 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1852 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1853 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1854 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1855 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1856 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1857 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1858 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1859 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1860 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1861 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1862 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1863 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1864 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1865 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1866 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1867 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1868 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1869 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1870 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1871 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1872 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1873 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1874 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1875 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1876 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1877 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1878 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1879 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1880 case MODE_AREG_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1881 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1882 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1883 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1884 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1885 ret = sprintf(dst, "%s ([a%d])", c, decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1886 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1887 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1888 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1889 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1890 ret = sprintf(dst, "%s ([%d.%c, a%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1891 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1892 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1893 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1894 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1895 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1896 ret = sprintf(dst, "%s ([a%d], %d.%c)", c, decoded->params.regs.pri, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1897 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1898 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1899 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1900 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1901 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1902 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1903 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1904 ret = sprintf(dst, "%s ([%d.%c, a%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1905 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1906 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1907 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1908 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1909 break;
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1910 case MODE_AREG_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1911 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1912 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1913 ret = sprintf(dst, "%s (%d.%c, a%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1914 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1915 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1916 //this is a lossy representation of the encoded instruction
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1917 //not sure if there's a better way to print it though
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1918 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1919 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1920 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1921 case MODE_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1922 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1923 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1924 ret = sprintf(dst, "%s (%d.%c, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1925 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1926 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1927 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1928 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1929 ret = sprintf(dst, "%s (%c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1930 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1931 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1932 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1933 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1934 case MODE_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1935 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1936 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1937 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1938 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1939 ret = sprintf(dst, "%s ([%c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1940 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1941 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1942 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1943 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1944 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1945 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1946 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1947 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1948 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1949 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1950 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1951 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1952 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1953 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1954 ret = sprintf(dst, "%s ([%c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1955 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1956 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1957 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1958 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1959 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1960 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1961 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1962 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1963 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1964 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1965 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1966 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1967 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1968 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1969 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1970 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1971 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1972 case MODE_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1973 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1974 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1975 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1976 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1977 ret = sprintf(dst, "%s ([], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1978 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1979 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1980 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1981 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1982 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1983 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1984 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1985 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1986 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1987 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1988 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1989 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1990 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1991 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1992 ret = sprintf(dst, "%s ([], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1993 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1994 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1995 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1996 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1997 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1998 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1999 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2000 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2001 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2002 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2003 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2004 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2005 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2006 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2007 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2008 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2009 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2010 case MODE_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2011 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2012 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2013 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2014 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2015 ret = sprintf(dst, "%s ([])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2016 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2017 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2018 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2019 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2020 ret = sprintf(dst, "%s ([%d.%c])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2021 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2022 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2023 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2024 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2025 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2026 ret = sprintf(dst, "%s ([], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2027 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2028 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2029 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2030 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2031 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2032 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2033 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2034 ret = sprintf(dst, "%s ([%d.%c], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2035 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2036 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2037 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2038 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2039 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2040 case MODE_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2041 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2042 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2043 ret = sprintf(dst, "%s (%d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2044 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2045 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2046 ret = sprintf(dst, "%s ()", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2047 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2048 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2049 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2050 case MODE_IMMEDIATE:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	2051 case MODE_IMMEDIATE_WORD:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2052 ret = sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2053 break;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2054 case MODE_ABSOLUTE_SHORT:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2055 if (labels) {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2056 ret = sprintf(dst, "%s ", c);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2057 ret += label_fun(dst+ret, decoded->params.immed, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2058 strcat(dst+ret, ".w");
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2059 ret = ret + 2;
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2060 } else {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2061 ret = sprintf(dst, "%s $%X.w", c, decoded->params.immed);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2062 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2063 break;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2064 case MODE_ABSOLUTE:
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2065 if (labels) {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2066 ret = sprintf(dst, "%s ", c);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2067 ret += label_fun(dst+ret, decoded->params.immed, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2068 strcat(dst+ret, ".l");
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2069 ret = ret + 2;
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2070 } else {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2071 ret = sprintf(dst, "%s $%X", c, decoded->params.immed);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2072 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2073 break;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2074 case MODE_PC_DISPLACE:
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2075 if (labels) {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2076 ret = sprintf(dst, "%s ", c);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2077 ret += label_fun(dst+ret, address + 2 + decoded->params.regs.displacement, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2078 strcat(dst+ret, "(pc)");
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2079 ret = ret + 4;
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2080 } else {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2081 ret = sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2082 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2083 break;
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	2084 case MODE_PC_INDEX_DISP8:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2085 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2086 if (decoded->params.regs.scale)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2087 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2088 ret = sprintf(dst, "%s (%d, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2089 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2090 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2091 ret = sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2092 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2093 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2094 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2095 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2096 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2097 case MODE_PC_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2098 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2099 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2100 ret = sprintf(dst, "%s (%d.%c, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2101 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2102 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2103 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2104 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2105 ret = sprintf(dst, "%s (pc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2106 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2107 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2108 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2109 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2110 case MODE_PC_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2111 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2112 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2113 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2114 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2115 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2116 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2117 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2118 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2119 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2120 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2121 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2122 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2123 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2124 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2125 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2126 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2127 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2128 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2129 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2130 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2131 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2132 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2133 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2134 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2135 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2136 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2137 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2138 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2139 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2140 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2141 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2142 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2143 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2144 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2145 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2146 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2147 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2148 case MODE_PC_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2149 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2150 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2151 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2152 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2153 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2154 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2155 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2156 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2157 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2158 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2159 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2160 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2161 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2162 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2163 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2164 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2165 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2166 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2167 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2168 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2169 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2170 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2171 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2172 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2173 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2174 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2175 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2176 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2177 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2178 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2179 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2180 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2181 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2182 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2183 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2184 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2185 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2186 case MODE_PC_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2187 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2188 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2189 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2190 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2191 ret = sprintf(dst, "%s ([pc])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2192 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2193 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2194 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2195 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2196 ret = sprintf(dst, "%s ([%d.%c, pc])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2197 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2198 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2199 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2200 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2201 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2202 ret = sprintf(dst, "%s ([pc], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2203 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2204 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2205 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2206 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2207 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2208 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2209 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2210 ret = sprintf(dst, "%s ([%d.%c, pc], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2211 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2212 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2213 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2214 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2215 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2216 case MODE_PC_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2217 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2218 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2219 ret = sprintf(dst, "%s (%d.%c, pc)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2220 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2221 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2222 ret = sprintf(dst, "%s (pc)", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2223 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2224 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2225 case MODE_ZPC_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2226 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2227 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2228 ret = sprintf(dst, "%s (%d.%c, zpc, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2229 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2230 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2231 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2232 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2233 ret = sprintf(dst, "%s (zpc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2234 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2235 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2236 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2237 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2238 case MODE_ZPC_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2239 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2240 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2241 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2242 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2243 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2244 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2245 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2246 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2247 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2248 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2249 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2250 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2251 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2252 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2253 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2254 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2255 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2256 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2257 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2258 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2259 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2260 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2261 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2262 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2263 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2264 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2265 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2266 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2267 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2268 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2269 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2270 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2271 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2272 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2273 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2274 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2275 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2276 case MODE_ZPC_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2277 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2278 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2279 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2280 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2281 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2282 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2283 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2284 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2285 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2286 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2287 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2288 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2289 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2290 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2291 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2292 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2293 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2294 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2295 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2296 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2297 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2298 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2299 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2300 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2301 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2302 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2303 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2304 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2305 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2306 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2307 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2308 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2309 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2310 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2311 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2312 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2313 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2314 case MODE_ZPC_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2315 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2316 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2317 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2318 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2319 ret = sprintf(dst, "%s ([zpc])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2320 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2321 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2322 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2323 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2324 ret = sprintf(dst, "%s ([%d.%c, zpc])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2325 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2326 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2327 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2328 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2329 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2330 ret = sprintf(dst, "%s ([zpc], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2331 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2332 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2333 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2334 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2335 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2336 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2337 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2338 ret = sprintf(dst, "%s ([%d.%c, zpc], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2339 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2340 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2341 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2342 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2343 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2344 case MODE_ZPC_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2345 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2346 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2347 ret = sprintf(dst, "%s (%d.%c, zpc)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2348 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2349 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2350 ret = sprintf(dst, "%s (zpc)", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2351 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2352 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2353 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2354 default:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2355 ret = 0;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	2356 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2357 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2358 if (decoded->addr_mode & M68K_FLAG_BITFIELD)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2359 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2360 switch (decoded->bitfield & 0x820)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2361 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2362 case 0:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2363 return ret + sprintf(dst+ret, " {$%X:%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2364 case 0x20:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2365 return ret + sprintf(dst+ret, " {$%X:d%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x7);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2366 case 0x800:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2367 return ret + sprintf(dst+ret, " {d%d:%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2368 case 0x820:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2369 return ret + sprintf(dst+ret, " {d%d:d%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x7);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2370 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2371 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2372 #endif
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2373 return ret;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	2374 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2375
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2376 int m68k_disasm_movem_op(m68k_op_info decoded, m68k_op_info other, char dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void data)
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2377 {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2378 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2379 char rtype, last_rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2380 int oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2381 if (decoded->addr_mode == MODE_REG) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2382 if (other->addr_mode == MODE_AREG_PREDEC) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2383 bit = 15;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2384 dir = -1;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2385 } else {
69 36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination Mike Pavone <pavone@retrodev.com> parents: 68 diff changeset	2386 dir = 1;
36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination Mike Pavone <pavone@retrodev.com> parents: 68 diff changeset	2387 bit = 0;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2388 }
68 1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2389 if (need_comma) {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2390 strcat(dst, ", ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2391 oplen = 2;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2392 } else {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2393 strcat(dst, " ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2394 oplen = 1;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2395 }
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2396 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	2397 if (decoded->params.immed & (1 << bit)) {
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2398 if (reg > 7) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2399 rtype = "a";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2400 regnum = reg - 8;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2401 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2402 rtype = "d";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2403 regnum = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2404 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2405 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2406 last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2407 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2408 } else if(last >= 0) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2409 if (first != last) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2410 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2411 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2412 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2413 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2414 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2415 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2416 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2417 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2418 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2419 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2420 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2421 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2422 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2423 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2424 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2425 if (last >= 0 && last != first) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2426 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2427 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2428 return oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2429 } else {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2430 return m68k_disasm_op(decoded, dst, need_comma, labels, address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2431 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2432 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2433
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2434 int m68k_default_label_fun(char * dst, uint32_t address, void * data)
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2435 {
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2436 return sprintf(dst, "ADR_%X", address);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2437 }
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2438
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2439 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels, format_label_fun label_fun, void * data)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2440 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2441 int ret,op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2442 uint8_t size;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2443 char * special_op = "CCR";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2444 switch (decoded->op)
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2445 {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2446 case M68K_BCC:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2447 case M68K_DBCC:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2448 case M68K_SCC:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2449 ret = strlen(mnemonics[decoded->op]) - 2;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2450 memcpy(dst, mnemonics[decoded->op], ret);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2451 dst[ret] = 0;
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2452 strcpy(dst+ret, cond_mnem[decoded->extra.cond]);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2453 ret = strlen(dst);
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2454 if (decoded->op != M68K_SCC) {
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2455 if (labels) {
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2456 if (decoded->op == M68K_DBCC) {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2457 ret += sprintf(dst+ret, " d%d, ", decoded->dst.params.regs.pri);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2458 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2459 } else {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2460 dst[ret++] = ' ';
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2461 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2462 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2463 } else {
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2464 if (decoded->op == M68K_DBCC) {
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2465 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2466 } else {
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2467 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2468 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2469 }
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2470 return ret;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2471 }
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2472 break;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2473 case M68K_BSR:
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2474 if (labels) {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2475 ret = sprintf(dst, "bsr%s ", decoded->variant == VAR_BYTE ? ".s" : "");
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2476 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2477 } else {
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2478 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2479 }
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2480 return ret;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2481 case M68K_MOVE_FROM_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2482 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2483 ret += sprintf(dst + ret, " SR");
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2484 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2485 return ret;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2486 case M68K_ANDI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2487 case M68K_EORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2488 case M68K_MOVE_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2489 case M68K_ORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2490 special_op = "SR";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2491 case M68K_ANDI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2492 case M68K_EORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2493 case M68K_MOVE_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2494 case M68K_ORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2495 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2496 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2497 ret += sprintf(dst + ret, ", %s", special_op);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2498 return ret;
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2499 case M68K_MOVE_USP:
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2500 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2501 if (decoded->src.addr_mode != MODE_UNUSED) {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2502 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2503 ret += sprintf(dst + ret, ", USP");
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2504 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2505 ret += sprintf(dst + ret, "USP, ");
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2506 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2507 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2508 return ret;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2509 case M68K_INVALID:
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2510 ret = sprintf(dst, "dc.w $%X", decoded->src.params.immed);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2511 return ret;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2512 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2513 case M68K_MOVEC:
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2514 ret = sprintf(dst, "%s ", mnemonics[decoded->op]);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2515 if (decoded->src.addr_mode == MODE_UNUSED) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2516 ret += sprintf(dst + ret, "%s, ", cr_mnem[decoded->src.params.immed]);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2517 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2518 } else {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2519 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2520 ret += sprintf(dst + ret, ", %s", cr_mnem[decoded->dst.params.immed]);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2521 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2522 return ret;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2523 #endif
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2524 default:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2525 size = decoded->extra.size;
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2526 ret = sprintf(dst, "%s%s%s",
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2527 mnemonics[decoded->op],
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2528 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""),
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2529 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : "")));
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2530 }
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2531 if (decoded->op == M68K_MOVEM) {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2532 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2533 ret += op1len;
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2534 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2535 } else {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2536 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2537 ret += op1len;
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2538 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2539 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2540 return ret;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2541 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2542
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2543 int m68k_disasm(m68kinst * decoded, char * dst)
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2544 {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2545 return m68k_disasm_ex(decoded, dst, 0, NULL, NULL);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2546 }
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2547
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2548 int m68k_disasm_labels(m68kinst * decoded, char * dst, format_label_fun label_fun, void * data)
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2549 {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2550 if (!label_fun)
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2551 {
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2552 label_fun = m68k_default_label_fun;
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2553 }
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2554 return m68k_disasm_ex(decoded, dst, 1, label_fun, data);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2555 }

Mercurial > repos > blastem

annotate 68kinst.c @ 652:f822d9216968