| Fri, 18 May 2018 19:00:10 -0700 |
Michael Pavone |
Fix cycle counts for BCD instructions, RESET, and MOVE from SR
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| Thu, 17 May 2018 00:43:16 -0700 |
Michael Pavone |
Fix instruction timing for a number of instructions with only a single operand
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| Wed, 03 Jan 2018 07:09:39 -0800 |
Michael Pavone |
Fix silly bug in STOP implementation that caused excessive CPU usage
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| Wed, 13 Sep 2017 21:13:11 -0700 |
Michael Pavone |
Push correct PC onto stack on divide by zero for pc-relative case
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| Wed, 13 Sep 2017 21:06:25 -0700 |
Michael Pavone |
Preserve original address when retranslating instructions instead of switching to the lowest alias
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| Wed, 06 Sep 2017 23:10:11 -0700 |
Michael Pavone |
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
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| Fri, 11 Aug 2017 18:43:48 -0700 |
Michael Pavone |
Avoid generating an instruction that would require a REX prefix when a7 is used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
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| Fri, 26 May 2017 19:18:19 -0700 |
Michael Pavone |
Avoid splitting m68k_check_cycles_int_latch code across memory chunks since it expects a byte-sized jump offset. Avoid an unnecessary m68k_check_cycles_int_latch for register to register moves
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| Tue, 23 May 2017 21:07:56 -0700 |
Michael Pavone |
Fix interrupt latency for move.l with memory destination
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| Fri, 19 May 2017 20:27:35 -0700 |
Michael Pavone |
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
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| Wed, 26 Apr 2017 21:55:12 -0700 |
Michael Pavone |
Fix timing for branch not taken case in the M68K BCC intruction
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| Mon, 24 Apr 2017 20:49:31 -0700 |
Michael Pavone |
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
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| Tue, 28 Mar 2017 09:39:54 -0700 |
Michael Pavone |
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
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| Tue, 28 Mar 2017 00:13:35 -0700 |
Michael Pavone |
Implemented M68K trace mode. Some edge cases/SR update paths still need work
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| Wed, 22 Mar 2017 22:16:39 -0700 |
Michael Pavone |
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
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| Fri, 17 Mar 2017 08:05:55 -0700 |
Michael Pavone |
Minor fix to timing of "early" overflow case in divs when the dividend is negative
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| Wed, 15 Mar 2017 19:05:27 -0700 |
Michael Pavone |
Cycle accurate implementation of divs
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| Thu, 09 Mar 2017 23:50:46 -0800 |
Michael Pavone |
Fix undefined flags on overflow and divide by zero for divu based on hardware test. Fix saving result of divu when destination is not stored in a host register
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| Thu, 09 Mar 2017 21:31:31 -0800 |
Michael Pavone |
Forgot to update flags in the "good" case of the new divu code
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| Fri, 03 Mar 2017 23:51:29 -0800 |
Michael Pavone |
Cycle accurate divu and undefined flags for overflow case
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| Thu, 23 Feb 2017 00:08:37 -0800 |
Michael Pavone |
WIP support for XBAND mapper hardware
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| Sun, 12 Feb 2017 12:38:31 -0800 |
Michael Pavone |
Fix timing for instructions using BINARY_IMPL
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| Sat, 04 Feb 2017 00:41:15 -0800 |
Michael Pavone |
Cycle accurate MULU/MULS emulation
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| Tue, 24 Jan 2017 00:15:27 -0800 |
Michael Pavone |
Inefficient fix for overlapping instruction problem that was causing issues with Outrunners
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| Wed, 28 Dec 2016 20:39:27 -0800 |
Michael Pavone |
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
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| Mon, 19 Dec 2016 13:28:18 -0800 |
Michael Pavone |
Mostly working changes to allow support for multiple emulated system types in main blastem program
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| Sat, 05 Nov 2016 00:23:11 -0700 |
Michael Pavone |
Get Jaguar video interrupt working
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| Thu, 06 Oct 2016 21:11:58 -0700 |
Michael Pavone |
Remove hacky assumption about Genesis memory map in M68K core
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| Thu, 06 Oct 2016 09:34:31 -0700 |
Michael Pavone |
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
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| Tue, 10 May 2016 08:59:17 -0700 |
Michael Pavone |
Fix bug in 68K movep.l when the destination is a register mapped to a host register
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| Sat, 30 Apr 2016 09:45:53 -0700 |
Michael Pavone |
Fix 68K interrupt handling some more. Fatal Rewind is working again.
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| Wed, 27 Apr 2016 23:11:24 -0700 |
Michael Pavone |
Implement privelege violation exceptions
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| Wed, 27 Apr 2016 21:39:17 -0700 |
Michael Pavone |
Implemented IR and undefined bits of info word for address error exception frames
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| Tue, 26 Apr 2016 23:13:37 -0700 |
Michael Pavone |
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
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| Tue, 26 Apr 2016 00:07:15 -0700 |
Michael Pavone |
Implement illegal instruction trap
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| Sun, 24 Apr 2016 21:23:28 -0700 |
Michael Pavone |
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
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| Sun, 24 Apr 2016 02:19:48 -0700 |
Michael Pavone |
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
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| Sun, 24 Apr 2016 00:22:38 -0700 |
Michael Pavone |
Fix order of writes for move.l with a predec destination
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| Sat, 23 Apr 2016 12:43:23 -0700 |
Michael Pavone |
Properly imlement btst with an immediate destination. Fixes a crash in NHL 95.
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| Wed, 02 Dec 2015 07:06:03 -0800 |
Michael Pavone |
Fix problem in 68K debugger caused by stack alignment change
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| Fri, 27 Nov 2015 13:10:02 -0800 |
Michael Pavone |
Fix a few lingering stack alignment rework bugs
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| Wed, 25 Nov 2015 08:40:45 -0800 |
Michael Pavone |
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
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| Sat, 14 Nov 2015 13:56:41 -0800 |
Michael Pavone |
Prevent the current interrupt number from being changed while interrupt is being processed. This fixes a bug in Sonic 2 split screen that showed up when interrupt timing was adjusted
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| Fri, 13 Nov 2015 19:15:37 -0800 |
Michael Pavone |
It is now possible to switch back and forth between the menu ROM and the game
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| Sun, 08 Nov 2015 15:51:57 -0800 |
Michael Pavone |
Initial work for allowing loading a ROM from menu
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| Sun, 01 Nov 2015 00:12:52 -0700 |
Michael Pavone |
Update timing and order of steps in interrupt processing to match latest measurements
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| Sat, 31 Oct 2015 22:17:50 -0700 |
Michael Pavone |
Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives accurate results in my test ROM
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| Thu, 29 Oct 2015 19:06:06 -0700 |
Michael Pavone |
Implement TRAPV
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| Wed, 28 Oct 2015 19:45:24 -0700 |
Michael Pavone |
Implement TAS
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| Wed, 21 Oct 2015 23:31:17 -0700 |
Michael Pavone |
Implemented nbcd
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| Mon, 19 Oct 2015 19:16:57 -0700 |
Michael Pavone |
Fix for abcd/sbcd. Hopefully got it 100% right this time.
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| Sat, 25 Jul 2015 18:22:07 -0700 |
Michael Pavone |
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
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| Sun, 28 Jun 2015 09:53:17 -0700 |
Michael Pavone |
More clang warning cleanup
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| Mon, 22 Jun 2015 22:00:02 -0700 |
Michael Pavone |
Fix negative offsets in calc_areg_displace
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| Mon, 25 May 2015 15:01:38 -0700 |
Michael Pavone |
Fix crash bug in 32-bit build for certain secnarios with bcd instructions
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| Mon, 25 May 2015 13:21:24 -0700 |
Michael Pavone |
Fix div instruction when dest is d0 in 32-bit build
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| Sat, 23 May 2015 20:24:27 -0700 |
Michael Pavone |
Eliminate runtime.S/runtime_32.S.
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| Fri, 22 May 2015 23:49:32 -0700 |
Michael Pavone |
Don't attempt to translate or map code at odd addresses. This fixes a bug that shows up when playing College Footbal USA 96
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| Mon, 11 May 2015 20:30:13 -0700 |
Michael Pavone |
Fixed a missed call to do_sync when updating SR in 68K core
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| Wed, 14 Jan 2015 09:38:54 -0800 |
Michael Pavone |
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
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