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Mon, 19 Feb 2024 23:00:49 -0800 Michael Pavone Fix bit instruction penalty cycle check for cases when bit number is out of range
Fri, 19 Jan 2024 22:30:25 -0800 Michael Pavone Properly handle stack alignment in m68k breakpoint implementation
Sat, 23 Dec 2023 17:37:57 -0800 Michael Pavone Implement 68K watchpoints in internal debugger
Mon, 16 Oct 2023 23:30:04 -0700 Michael Pavone Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Fri, 13 Oct 2023 22:44:36 -0700 Michael Pavone Fix regression from asan/ubsan fix
Wed, 23 Aug 2023 22:09:35 -0700 Michael Pavone Fix M68K STOP instruction for sub CPU
Sun, 08 Jan 2023 14:20:43 -0800 Michael Pavone Fix edge case in m68k_invalidate_code_range that caused problems when loading save states
Mon, 26 Dec 2022 07:17:29 -0800 Michael Pavone Hopefully make older versions of gcc happy
Sun, 25 Dec 2022 18:16:44 -0800 Michael Pavone Avoid code mem allocation bomb when a div instruction gets rewritten
Wed, 21 Sep 2022 23:16:39 -0700 Michael Pavone Fix crash regression in m68k bit instruction implementation
Thu, 08 Sep 2022 20:50:18 -0700 Michael Pavone Make sure 68K interrupt is executed immediately when resuming core if it has a target cycle <= current. Fixes IRQ tests in mcd-verificator
Mon, 05 Sep 2022 12:00:02 -0700 Michael Pavone Fix implementation ot 68K trapv instruction
Mon, 05 Sep 2022 01:15:15 -0700 Michael Pavone Fix some 68K exception processing cycle times
Mon, 05 Sep 2022 00:49:03 -0700 Michael Pavone Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
Fri, 11 Feb 2022 22:55:01 -0800 Michael Pavone Fix regression in booting games with Japanese Mega CD BIOS
Wed, 09 Feb 2022 23:39:33 -0800 Michael Pavone Fix handling of address error for 32-bit accesses
Sat, 05 Feb 2022 16:41:01 -0800 Michael Pavone Fix instruction retranslation for write protectable region of SCD Program RAM
Tue, 18 Jan 2022 00:03:50 -0800 Michael Pavone Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM segacd
Wed, 10 Jun 2020 19:08:41 -0700 Michael Pavone Fix cycle timing of a number of 68K instructions
Sat, 25 Apr 2020 18:10:40 -0700 Michael Pavone Fix instruction timing for addq.w #i, (ay) in dynarec
Sun, 07 Apr 2019 00:06:29 -0700 Michael Pavone Get 64-bit builds working for Windows target
Fri, 18 May 2018 19:00:10 -0700 Michael Pavone Fix cycle counts for BCD instructions, RESET, and MOVE from SR
Thu, 17 May 2018 00:43:16 -0700 Michael Pavone Fix instruction timing for a number of instructions with only a single operand
Wed, 03 Jan 2018 07:09:39 -0800 Michael Pavone Fix silly bug in STOP implementation that caused excessive CPU usage
Wed, 13 Sep 2017 21:13:11 -0700 Michael Pavone Push correct PC onto stack on divide by zero for pc-relative case
Wed, 13 Sep 2017 21:06:25 -0700 Michael Pavone Preserve original address when retranslating instructions instead of switching to the lowest alias
Wed, 06 Sep 2017 23:10:11 -0700 Michael Pavone Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
Fri, 11 Aug 2017 18:43:48 -0700 Michael Pavone Avoid generating an instruction that would require a REX prefix when a7 is used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
Fri, 26 May 2017 19:18:19 -0700 Michael Pavone Avoid splitting m68k_check_cycles_int_latch code across memory chunks since it expects a byte-sized jump offset. Avoid an unnecessary m68k_check_cycles_int_latch for register to register moves
Tue, 23 May 2017 21:07:56 -0700 Michael Pavone Fix interrupt latency for move.l with memory destination
Fri, 19 May 2017 20:27:35 -0700 Michael Pavone Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Wed, 26 Apr 2017 21:55:12 -0700 Michael Pavone Fix timing for branch not taken case in the M68K BCC intruction
Mon, 24 Apr 2017 20:49:31 -0700 Michael Pavone Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Tue, 28 Mar 2017 09:39:54 -0700 Michael Pavone Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Tue, 28 Mar 2017 00:13:35 -0700 Michael Pavone Implemented M68K trace mode. Some edge cases/SR update paths still need work
Wed, 22 Mar 2017 22:16:39 -0700 Michael Pavone Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
Fri, 17 Mar 2017 08:05:55 -0700 Michael Pavone Minor fix to timing of "early" overflow case in divs when the dividend is negative
Wed, 15 Mar 2017 19:05:27 -0700 Michael Pavone Cycle accurate implementation of divs
Thu, 09 Mar 2017 23:50:46 -0800 Michael Pavone Fix undefined flags on overflow and divide by zero for divu based on hardware test. Fix saving result of divu when destination is not stored in a host register
Thu, 09 Mar 2017 21:31:31 -0800 Michael Pavone Forgot to update flags in the "good" case of the new divu code
Fri, 03 Mar 2017 23:51:29 -0800 Michael Pavone Cycle accurate divu and undefined flags for overflow case
Thu, 23 Feb 2017 00:08:37 -0800 Michael Pavone WIP support for XBAND mapper hardware
Sun, 12 Feb 2017 12:38:31 -0800 Michael Pavone Fix timing for instructions using BINARY_IMPL
Sat, 04 Feb 2017 00:41:15 -0800 Michael Pavone Cycle accurate MULU/MULS emulation
Tue, 24 Jan 2017 00:15:27 -0800 Michael Pavone Inefficient fix for overlapping instruction problem that was causing issues with Outrunners
Wed, 28 Dec 2016 20:39:27 -0800 Michael Pavone Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Mon, 19 Dec 2016 13:28:18 -0800 Michael Pavone Mostly working changes to allow support for multiple emulated system types in main blastem program
Sat, 05 Nov 2016 00:23:11 -0700 Michael Pavone Get Jaguar video interrupt working
Thu, 06 Oct 2016 21:11:58 -0700 Michael Pavone Remove hacky assumption about Genesis memory map in M68K core
Thu, 06 Oct 2016 09:34:31 -0700 Michael Pavone Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Tue, 10 May 2016 08:59:17 -0700 Michael Pavone Fix bug in 68K movep.l when the destination is a register mapped to a host register
Sat, 30 Apr 2016 09:45:53 -0700 Michael Pavone Fix 68K interrupt handling some more. Fatal Rewind is working again.
Wed, 27 Apr 2016 23:11:24 -0700 Michael Pavone Implement privelege violation exceptions
Wed, 27 Apr 2016 21:39:17 -0700 Michael Pavone Implemented IR and undefined bits of info word for address error exception frames
Tue, 26 Apr 2016 23:13:37 -0700 Michael Pavone Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Tue, 26 Apr 2016 00:07:15 -0700 Michael Pavone Implement illegal instruction trap
Sun, 24 Apr 2016 21:23:28 -0700 Michael Pavone Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Sun, 24 Apr 2016 02:19:48 -0700 Michael Pavone Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Sun, 24 Apr 2016 00:22:38 -0700 Michael Pavone Fix order of writes for move.l with a predec destination
Sat, 23 Apr 2016 12:43:23 -0700 Michael Pavone Properly imlement btst with an immediate destination. Fixes a crash in NHL 95.
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