| Wed, 27 Apr 2016 23:57:00 -0700 |
Michael Pavone |
Properly emulate machine freeze when reading from VDP while configured for writes
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| Sun, 24 Apr 2016 14:30:15 -0700 |
Michael Pavone |
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
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| Sun, 24 Apr 2016 11:53:59 -0700 |
Michael Pavone |
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
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| Sun, 24 Apr 2016 02:19:48 -0700 |
Michael Pavone |
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
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| Sun, 24 Apr 2016 01:24:38 -0700 |
Michael Pavone |
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
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| Tue, 12 Apr 2016 21:38:24 -0700 |
Michael Pavone |
Remove the int number argument to vdp_int_ack since it is no longer used
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| Tue, 12 Apr 2016 08:35:44 -0700 |
Michael Pavone |
Fix VDP interrupt ack. Big thanks to Eke-Eke or whoever left that helpful comment in Genesis Plus GX. Fixes Fatal Rewind
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| Tue, 02 Feb 2016 18:33:00 -0800 |
Michael Pavone |
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
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| Tue, 02 Feb 2016 18:24:15 -0800 |
Michael Pavone |
Perform the same slot mapping shift for H32 mode as I did for H40
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| Thu, 28 Jan 2016 09:10:14 -0800 |
Michael Pavone |
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
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| Tue, 26 Jan 2016 19:23:10 -0800 |
Michael Pavone |
After reviewing the results of my test ROM again it seems pretty clear that the VBlank flag gets set at the same time as the vcounter changes
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| Sun, 17 Jan 2016 14:46:12 -0800 |
Michael Pavone |
Fix calculation of window start column when it's on the right side. This removes graphical glitches in Afterburner 2, Fireshark and Dungeons and Dragons: Warriors of the Eternal Sun and probably others
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| Fri, 13 Nov 2015 22:56:59 -0800 |
Michael Pavone |
Selecting a second game from the menu now works
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| Mon, 03 Aug 2015 20:06:56 -0700 |
Michael Pavone |
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
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| Fri, 17 Jul 2015 08:49:23 -0700 |
Michael Pavone |
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
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| Sun, 28 Jun 2015 09:53:17 -0700 |
Michael Pavone |
More clang warning cleanup
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| Sat, 30 May 2015 15:53:59 -0700 |
Michael Pavone |
Fixed shadow/highlight mode
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| Fri, 22 May 2015 18:38:44 -0700 |
Michael Pavone |
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
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| Thu, 21 May 2015 00:55:46 -0700 |
Michael Pavone |
Restore the other 2 debug display modes
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| Wed, 20 May 2015 22:27:51 -0700 |
Michael Pavone |
Add some tests for hint timing and fix it properly this time.
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| Wed, 20 May 2015 19:05:11 -0700 |
Michael Pavone |
Upgrade to SDL 2.0 and drop support for the non-OpenGL render path
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| Wed, 20 May 2015 10:35:03 -0700 |
Michael Pavone |
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
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| Tue, 19 May 2015 23:23:53 -0700 |
Michael Pavone |
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
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| Sun, 17 May 2015 15:43:20 -0700 |
Michael Pavone |
Fix VDP status register PAL bit based on observations of the Titan Overdrive demo
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| Sat, 16 May 2015 23:08:07 -0700 |
Michael Pavone |
Adjust H32 vint slot in response to latest test ROM data
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| Sat, 16 May 2015 23:04:57 -0700 |
Michael Pavone |
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
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| Thu, 14 May 2015 23:17:55 -0700 |
Michael Pavone |
Small horizontal interrupt fixes
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| Wed, 13 May 2015 19:19:43 -0700 |
Michael Pavone |
Add description of cd register value to vr debugger command
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| Mon, 11 May 2015 20:30:35 -0700 |
Michael Pavone |
Fix frame counter increment and VINT cycle time calculation
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| Mon, 11 May 2015 00:28:47 -0700 |
Michael Pavone |
Sync fixes and logging to fix more sync issues
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| Sun, 04 Jan 2015 23:05:37 -0800 |
Michael Pavone |
Some small synchronization improvements that do not seem to fix anything
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| Sun, 04 Jan 2015 12:24:34 -0800 |
Michael Pavone |
Adjusted h40_hsync_cycles so that lines actually take 3420 mclks. Fixed vdp_cycles_next_line to take h40_sync_cycles into account
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| Sun, 14 Dec 2014 18:14:50 -0800 |
Michael Pavone |
Fix the HV counter and adjust the slots of certain VDP events
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| Thu, 14 Aug 2014 09:38:32 -0700 |
Michael Pavone |
Small fix to display of DMA source address in vr debug command
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| Wed, 18 Jun 2014 16:39:42 -0700 |
Michael Pavone |
Remove debug printf that escaped into my previous commit
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| Wed, 18 Jun 2014 16:30:19 -0700 |
Michael Pavone |
Fix most of the breakage caused by the vcounter/hcounter changes
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| Tue, 17 Jun 2014 19:01:01 -0700 |
Michael Pavone |
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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| Mon, 16 Jun 2014 19:13:28 -0700 |
Michael Pavone |
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
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| Sat, 08 Feb 2014 23:37:09 -0800 |
Mike Pavone |
Initial GDB remote debugging support. Lacks some features, but breakpoints and basic inspection of registers and memory work.
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| Mon, 06 Jan 2014 22:54:05 -0800 |
Michael Pavone |
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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| Thu, 31 Oct 2013 00:28:27 -0700 |
Mike Pavone |
Small optimization for H40 mode
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| Tue, 29 Oct 2013 00:03:11 -0700 |
Mike Pavone |
Merge
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| Mon, 07 Oct 2013 10:02:08 -0700 |
Mike Pavone |
Initial implementation of sprite overflow and sprite collision status register flags
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| Sun, 27 Oct 2013 01:29:50 -0700 |
Mike Pavone |
Basic OpenGL rendering is working
opengl
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| Tue, 17 Sep 2013 19:10:00 -0700 |
Mike Pavone |
Set VBLANK flag in status register when display is disabled
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| Tue, 17 Sep 2013 09:45:14 -0700 |
Mike Pavone |
Implement HV counter latch
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| Tue, 17 Sep 2013 00:42:49 -0700 |
Mike Pavone |
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
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| Tue, 17 Sep 2013 00:11:45 -0700 |
Mike Pavone |
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
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| Mon, 16 Sep 2013 09:44:22 -0700 |
Mike Pavone |
Partial fix for DMA copy
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| Sun, 15 Sep 2013 23:49:09 -0700 |
Mike Pavone |
Clear the low 2 bits of CD when a register is written to
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| Sun, 15 Sep 2013 23:40:18 -0700 |
Mike Pavone |
Don't allow register writes to regs above when in Mode 4
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| Sun, 15 Sep 2013 23:33:24 -0700 |
Mike Pavone |
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
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| Sun, 15 Sep 2013 23:00:17 -0700 |
Mike Pavone |
Implement undocumented 8-bit VRAM read
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| Sun, 15 Sep 2013 22:43:01 -0700 |
Mike Pavone |
Fix VSRAM reads
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| Sun, 15 Sep 2013 22:20:43 -0700 |
Mike Pavone |
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
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| Fri, 13 Sep 2013 19:22:46 -0700 |
Mike Pavone |
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
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| Tue, 10 Sep 2013 23:31:08 -0700 |
Mike Pavone |
Added copyright notice to source files and added GPL license text in COPYING
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| Tue, 10 Sep 2013 09:55:12 -0700 |
Mike Pavone |
Fix timing of backdrop rendering when the display is turned off
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| Tue, 10 Sep 2013 00:30:39 -0700 |
Mike Pavone |
Merge
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| Tue, 10 Sep 2013 00:29:46 -0700 |
Mike Pavone |
Implement FIFO latency and improve DMA accuracy
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