annotate modules/il.tp @ 310:2308336790d4

WIP compiler module for low-level dialect
author Michael Pavone <pavone@retrodev.com>
date Fri, 01 Aug 2014 18:56:39 -0700
parents 56b2100d9fff
children f987bb2a1911
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1 {
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2 //commutative ops
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3 _add <- 0
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4 _and <- 1
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5 _or <- 2
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6 _xor <- 3
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7 _mul <- 4
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8 //non-commutative ops
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9 _div <- 5
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10 _sub <- 6
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11 _cmp <- 7
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12 _not <- 8
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13 _sl <- 9
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14 _asr <- 10
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15 _lsr <- 11
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16 _rol <- 12
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17 _ror <- 13
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18 _mov <- 14
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19 _call <- 15
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20 _ret <- 16
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21 _skipif <- 17
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22 _save <- 18
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23 _bool <- 19
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24
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25 _names <- #[
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26 "add"
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27 "and"
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28 "or"
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29 "xor"
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30 "mul"
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31 "div"
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32 "sub"
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33 "cmp"
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34 "not"
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35 "sl"
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36 "asr"
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37 "lsr"
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38 "rol"
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39 "ror"
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40 "mov"
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41 "call"
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42 "ret"
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43 "skipIf"
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44 "save"
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45 "bool"
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46 ]
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47
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48 op3:a:b:out:size <- :_opcode :_ina :_inb :_out :_size {
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49 #{
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50 opcode <- { _opcode }
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51 ina <- { _ina }
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52 inb <- { _inb }
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53 commutative? <- { _opcode < _sub }
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54 out <- { _out }
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55 size <- { _size }
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56 numops <- { 3 }
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57 name <- { _names get: _opcode }
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58 string <- { name . " " . (string: _ina) . " " . (string: _inb) . " " . (string: _out) . " " . (string: _size) }
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59 recordUsage:at <- :tracker :address {
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60 if: (not: (_ina isInteger?)) {
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61 _ina recordUsage: tracker at: 0 | address withSize: _size
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62 }
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63 _inb recordUsage: tracker at: 0 | address withSize: _size
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64 _out recordUsage: tracker at: 1 | address withSize: _size
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65 }
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66 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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67 newa <- if: (not: (_ina isInteger?)) {
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68 _ina assign: assignments withSource: regSrc
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69 } else: { _ina }
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70 newb <- _inb assign: assignments withSource: regSrc
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71 newout <- _out assign: assignments withSource: regSrc
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72 op3: _opcode a: newa b: newb out: newout size: _size
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73 }
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74 }
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75 }
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76 op2:in:out:size <- :_opcode :_in :_out :_size {
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77 #{
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78 opcode <- { _opcode }
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79 in <- { _in }
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80 out <- { _out }
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81 size <- { _size }
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82 numops <- { 2 }
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83 name <- { _names get: _opcode }
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84 string <- { name . " " . (string: _in) . " " . (string: _out) . " " . (string: _size) }
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85 recordUsage:at <- :tracker :address {
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86 if: (not: (_in isInteger?)) {
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87 _in recordUsage: tracker at: 0 | address withSize: _size
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88 }
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89 _out recordUsage: tracker at: 1 | address withSize: _size
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90 }
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91 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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92 newin <- if: (not: (_in isInteger?)) {
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93 _in assign: assignments withSource: regSrc
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94 } else: { _in }
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95 newout <- _out assign: assignments withSource: regSrc
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96 op2: _opcode in: newin out: newout size: _size
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97 }
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98 }
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99 }
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100 op1:arg:size <- :_opcode :_arg :_size {
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101 #{
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102 opcode <- { _opcode }
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103 arg <- { _arg }
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104 size <- { _size }
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105 numops <- { 1 }
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106 name <- { _names get: _opcode }
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107 string <- { name . " " . (string: _arg) . " " . (string: _size) }
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108 recordUsage:at <- :tracker :address {
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109 if: (not: (_arg isInteger?)) {
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110 _arg recordUsage: tracker at: address withSize: _size
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111 }
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112 }
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113 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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114 newarg <- if: (not: (_arg isInteger?)) {
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115 _arg assign: assignments withSource: regSrc
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116 } else: { _arg }
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117 op1: _opcode arg: newarg size: _size
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118 }
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119 }
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120 }
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121
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122 _sizenames <- #["b" "w" "l" "q"]
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123 _size <- :_bytes {
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124 #{
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125 bytes <- { _bytes }
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126 string <- {
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127 idx <- if: _bytes = 8 { 3 } else: { _bytes / 2}
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128 _sizenames get: idx
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129 }
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130 = <- :other {
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131 _bytes = (other bytes)
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132 }
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133 <= <- :other {
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134 _bytes <= (other bytes)
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135 }
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136 >= <- :other {
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137 _bytes >= (other bytes)
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138 }
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139 > <- :other {
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140 _bytes > (other bytes)
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141 }
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142 < <- :other {
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143 _bytes < (other bytes)
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144 }
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145 }
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146 }
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147 byte <- _size: 1
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148 word <- _size: 2
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149 long <- _size: 4
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150 quad <- _size: 8
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151
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152 _retr <- #{
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153 isInteger? <- { false }
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154 register? <- { true }
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155 argument? <- { false }
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156 return? <- { true }
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157 string <- { "retr" }
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158 = <- :other {
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159 (not: (other isInteger?)) && (other register?) && (other return?)
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160 }
189
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161 != <- :other {
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162 not: self = other
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163 }
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164 recordUsage:at:withSize <- :tracker :address :size {
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165 //TODO: Figure out what tracking is necessary here
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166 }
194
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167 assign:withSource <- :assignments :regSrc {
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168 regSrc allocRet
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169 }
185
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170 }
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171
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172 _condnames <- #[
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173 "eq"
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174 "neq"
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175 "ge"
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176 "le"
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177 "gr"
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178 "ls"
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179 "uge"
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180 "ule"
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181 "ugr"
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182 "uls"
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183 ]
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184 condition <- :num {
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185 #{
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186 cc <- { num }
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187 string <- { _condnames get: num }
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188 = <- :other { num = (other cc) }
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189 }
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190 }
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191 _eq <- condition: 0
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192 _neq <- condition: 1
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193 _ge <- condition: 2
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194 _le <- condition: 3
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195 _gr <- condition: 4
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196 _ls <- condition: 5
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197 _uge <- condition: 6
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198 _ule <- condition: 7
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199 _ugr <- condition: 8
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200 _uls <- condition: 9
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201
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202 #{
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203 b <- { byte }
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204 w <- { word }
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205 l <- { long }
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206 q <- { quad }
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207
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208 eq <- { _eq }
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209 neq <- { _neq }
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210
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211 //signed conditions
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212 ge <- { _ge }
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213 le <- { _le }
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214 gr <- { _gr }
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215 ls <- { _ls }
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216
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217 //unsigned conditions
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218 uge <- { _uge }
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219 ule <- { _ule }
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220 ugr <- { _ugr }
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221 uls <- { _uls }
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222
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223
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224 reg <- :num {
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225 #{
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226 isInteger? <- { false }
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227 register? <- { true }
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228 argument? <- { false }
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229 return? <- { false }
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230 regnum <- { num }
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231 string <- { "r" . (string: num) }
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232 = <- :other {
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233 (not: (other isInteger?)) && (other register?) && (not: (other argument?)) && (not: (other return?)) && num = (other regnum)
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234 }
189
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235 != <- :other {
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236 not: self = other
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237 }
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238 recordUsage:at:withSize <- :tracker :address :size {
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239 tracker reg: self usedAt: address withSize: size
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240 }
194
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241 assign:withSource <- :assignments :regSrc {
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242 assignments get: self
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243 }
185
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244 }
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245 }
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246 arg <- :num {
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247 #{
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248 isInteger? <- { false }
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249 register? <- { true }
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250 argument? <- { true }
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251 return? <- { false }
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252 argnum <- { num }
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253 string <- { "a" . (string: num) }
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254 = <- :other {
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255 (not: (other isInteger?)) && (other register?) && (other argument?) && num = (other regnum)
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256 }
189
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257 != <- :other {
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258 not: self = other
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259 }
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260 recordUsage:at:withSize <- :tracker :address :size {
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261 tracker arg: self usedAt: address withSize: size
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262 }
194
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263 assign:withSource <- :assignments :regSrc {
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264 regSrc allocArg: num
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265 }
185
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266 }
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267 }
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268 retr <- { _retr }
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269
189
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270 base:offset <- :_base :_offset {
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271 #{
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272 base <- { _base }
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273 offset <- { _offset }
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274 string <- {
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275 start <- if: _offset = 0 { "" } else: { (string: _offset) }
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276 start . "[" . (string: _base) . "]"
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277 }
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278 recordUsage:at:withSize <- :tracker :address :size {
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279 _base recordUsage: tracker at: address withSize: size
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280 }
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281 }
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282 }
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283
185
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284 add <- :ina inb out size {
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285 op3: _add a: ina b: inb out: out size: size
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286 }
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287
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288 sub <- :ina inb out size {
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289 op3: _sub a: ina b: inb out: out size: size
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290 }
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291
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292 cmp <- :ina inb out size {
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293 op3: _cmp a: ina b: inb out: out size: size
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294 }
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295
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296 and <- :ina inb out size {
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297 op3: _and a: ina b: inb out: out size: size
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298 }
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299
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300 or <- :ina inb out size {
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301 op3: _or a: ina b: inb out: out size: size
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302 }
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303
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304 xor <- :ina inb out size {
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305 op3: _xor a: ina b: inb out: out size: size
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306 }
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307
310
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308 mul <- :ina inb out size {
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309 op3: _mul a: ina b: inb out: out size: size
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310 }
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311
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312 div <- :ina inb out size {
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313 op3: _div a: ina b: inb out: out size: size
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314 }
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315
185
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316 bnot <- :in out size {
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317 op2: _not in: in out: out size: size
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318 }
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319
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320 sl <- :shift in out size {
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321 op3: _sl a: shift b: in out: out size: size
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322 }
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323
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324 asr <- :shift in out size {
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325 op3: _asr a: shift b: in out: out size: size
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326 }
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327
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328 lsr <- :shift in out size {
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329 op3: _lsr a: shift b: in out: out size: size
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330 }
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331
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332 rol <- :rot in out size {
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333 op3: _rol a: rot b: in out: out size: size
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334 }
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335
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336 ror <- :rot in out size {
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337 op3: _ror a: rot b: in out: out size: size
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338 }
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339
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340 mov <- :in out size {
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341 op2: _mov in: in out: out size: size
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342 }
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343
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344 call:withArgs <- :_target :_args {
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345 #{
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346 opcode <- { _call }
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347 target <- { _target }
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348 args <- { _args }
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349 numops <- { 0 }
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350 name <- { _names get: _call }
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351 string <- {
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352 argstr <- _args map: :el {
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353 string: el
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354 }
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355 name . " " . (string: _target) . " " . (argstr join: " ")
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356 }
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357 recordUsage:at <- :tracker :address {
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358 if: (not: (_target isString?)) {
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359 //TODO: use size l for 32-bit targets or an abstract pointer size
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360 _target recordUsage: tracker at: address withSize: q
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361 }
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362 foreach: _args :_ arg {
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363 //TODO: have some mechanism for properly expressing sizes of arguments
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364 arg recordUsage: tracker at: address withSize: q
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365 }
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366 }
200
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367 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
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368 newtarget <- if: (_target isString?) { _target } else: {
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369 _target assign: assignments withSource: regSrc
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370 }
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371 newargs <- _args map: :arg {
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372 if: (arg isInteger?) { arg } else: {
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373 arg assign: assignments withSource: regSrc
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374 }
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375 }
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376 newcall <- call: newtarget withArgs: newargs
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377 regSrc returnAll
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378 raddress <- address reverse
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379 foreach: (usage liveArgsAt: raddress) :_ arg {
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380 regSrc allocArg: (arg num)
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381 }
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382 foreach: (usage liveRegsAt: raddress) :_ reg {
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383 regSrc allocSpecific: (assignments get: reg)
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384 }
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385 tosave <- regSrc needSaveForCall
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386 if: (tosave length) > 0 {
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387 save: tosave #[newcall]
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388 } else: {
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389 newcall
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390 }
194
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391 }
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392 }
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393 }
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394
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395 return <- :val size {
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396 op1: _ret arg: val size: size
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397 }
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398 skipIf <- :_cond _toskip {
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399 #{
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400 opcode <- { _skipif }
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401 toskip <- { _toskip }
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402 cond <- { _cond }
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403 numops <- { 0 }
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404 name <- { _names get: _skipif }
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405 string <- {
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406 block <- (_toskip map: :el { string: el }) join: "\n\t"
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407 if: (_toskip length) > 0 {
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408 block <- "\n\t" . block . "\n"
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409 }
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410 name . " " . (string: _cond) . " {" . block . "}"
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411 }
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412 recordUsage:at <- :tracker :address {
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413 foreach: _toskip :idx inst {
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414 inst recordUsage: tracker at: idx | address
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415 }
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416 }
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417 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
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418 newskip <- #[]
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419 foreach: _toskip :idx inst {
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420 newskip append: (inst assignRegs: assignments at: idx | address withSource: regSrc andUsage: usage)
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421 }
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422 skipIf: _cond newskip
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423 }
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424 to2OpInst <- {
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425 skipIf: _cond (to2Op: _toskip)
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426 }
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427 }
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428 }
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429 save <- :regs :_scope{
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430 #{
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431 opcode <- { _save }
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432 numops <- { 0 }
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433 name <- { _names get: _save }
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434 tosave <- { regs }
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435 scope <- { _scope }
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436 string <- {
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437 block <- _scope join: "\n\t"
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438 if: (_scope length) > 0 {
195
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439 block <- "\n\t" . block . "\n"
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440 }
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441 name . " " . (regs join: " ") . " {" . block . "}"
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442 }
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443 to2OpInst <- {
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444 save: regs (to2Op: _scope)
200
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445 }
195
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446 }
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447 }
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448
310
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449 //produces a non-zero value or zero based on condition code flags
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450 bool <- :_cond _out {
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451 #{
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452 opcode <- { _bool }
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453 cond <- { _cond }
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454 out <- { _code }
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455 name <- { _names get: _save }
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456 numops <- { 0 }
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457
2308336790d4 WIP compiler module for low-level dialect
Michael Pavone <pavone@retrodev.com>
parents: 203
diff changeset
458 }
2308336790d4 WIP compiler module for low-level dialect
Michael Pavone <pavone@retrodev.com>
parents: 203
diff changeset
459 }
2308336790d4 WIP compiler module for low-level dialect
Michael Pavone <pavone@retrodev.com>
parents: 203
diff changeset
460
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
461 allocRegs:withSource <- :instarr:regSrc {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
462 _regMap <- dict linear
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
463 _argMap <- dict linear
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
464
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
465 _usageTracker <- :_firstUsage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
466 #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
467 firstUsage <- _firstUsage
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
468 lastUsage <- _firstUsage
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
469 useCount <- 0
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
470 maxSize <- byte
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
471 usedAt:withSize <- :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
472 useCount <- useCount + 1
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
473 lastUsage <- address
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
474 if: size > maxSize {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
475 maxSize <- size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
476 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
477 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
478 string <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
479 "Uses: " . useCount . ", FirstUse: " . (firstUsage join: ":") . ", Last Use: " . (lastUsage join: ":") . ", Max Size: " . maxSize
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
480 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
481 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
482 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
483
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
484 _maxUses <- 0
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
485 liveFrom:to <- :regs :from :to {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
486 live <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
487 foreach: regs :reg usage {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
488 if: ((usage lastUsage) addrGreatEq: from) && ((usage firstUsage) addrLessEq: to) {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
489 live append: reg
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
490 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
491 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
492 live
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
493 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
494 regUsage <- #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
495 reg:usedAt:withSize <- :reg :address :size {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
496 raddress <- address reverse
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
497 usage <- _regMap get: reg elseSet: {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
498 _usageTracker: raddress
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
499 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
500 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
501 if: (usage useCount) > _maxUses {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
502 _maxUses <- usage useCount
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
503 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
504 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
505 arg:usedAt:withSize <- :arg :address :size {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
506 raddress <- address reverse
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
507 usage <- _argMap get: arg elseSet: {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
508 _usageTracker: [0 0]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
509 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
510 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
511 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
512
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
513 liveRegsAt <- :address {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
514 _regMap liveFrom: address to: address
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
515 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
516 liveArgsAt <- :address {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
517 _argMap liveFrom: address to: address
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
518 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
519
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
520 print <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
521 foreach: _regMap :reg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
522 print: (string: reg) . " | " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
523 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
524 foreach: _argMap :arg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
525 print: (string: arg) . " | " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
526 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
527 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
528 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
529 foreach: instarr :idx inst {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
530 inst recordUsage: regUsage at: [idx]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
531 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
532 print: regUsage
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
533
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
534 addrLessEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
535 lesseq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
536 while: { lesseq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
537 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
538 lesseq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
539 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
540 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
541 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
542 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
543 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
544 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
545 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
546 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
547 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
548 lesseq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
549 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
550
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
551 addrGreatEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
552 greateq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
553 while: { greateq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
554 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
555 greateq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
556 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
557 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
558 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
559 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
560 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
561 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
562 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
563 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
564 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
565 greateq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
566 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
567
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
568 _assignments <- dict linear
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
569 curuses <- _maxUses
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
570 while: { curuses > 0 && (_assignments length) < (_regMap length) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
571 foreach: _regMap :reg usage {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
572 if: (usage useCount) = curuses {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
573 liveArgs <- _argMap liveFrom: (usage firstUsage) to: (usage lastUsage)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
574 foreach: liveArgs :_ arg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
575 regSrc allocArg: (arg num)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
576 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
577
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
578 liveRegs <- _regMap liveFrom: (usage firstUsage) to: (usage lastUsage)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
579 print: (string: reg) . " | Live: " . (liveRegs join: ", ") . ", Live Args: " . (liveArgs join: ", ") . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
580 foreach: liveRegs :_ reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
581 if: (_assignments contains?: reg) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
582 regSrc allocSpecific: (_assignments get: reg)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
583 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
584 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
585 _assignments set: reg (regSrc alloc: (usage maxSize))
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
586
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
587 regSrc returnAll
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
588 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
589 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
590 curuses <- curuses - 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
591 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
592 print: "\n\nAssignments:\n\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
593 foreach: _assignments :reg assign {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
594 print: (string: reg) . " = " . assign . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
595 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
596
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
597 withassign <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
598 foreach: instarr :idx inst {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
599 withassign append: (inst assignRegs: _assignments at: [idx] withSource: regSrc andUsage: regUsage)
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
600 }
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
601 psave <- regSrc needSaveProlog
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
602 if: (psave length) > 0 {
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
603 withassign <- #[save: psave withassign]
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
604 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
605 withassign
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
606 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
607
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
608 //used to convert IL to a format suitable for a 2-operand architecture
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
609 //should be run after register allocation (I think....)
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
610 to2Op <- :instarr {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
611 instarr fold: #[] with: :newarr inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
612 if: (inst numops) = 3 {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
613 if: (inst inb) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
614 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
615 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
616 if: (inst commutative?) && (inst ina) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
617 newarr append: (op2: (inst opcode) in: (inst inb) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
618 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
619 newarr append: (mov: (inst inb) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
620 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
621 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
622 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
623 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
624 if: (inst numops) = 2 && (inst opcode) != _mov {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
625 if: (inst in) != (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
626 newarr append: (mov: (inst in) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
627 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
628 newarr append: (op1: (inst opcode) val: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
629 } else: {
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
630 if: (inst opcode) = _skipif || (inst opcode) = _save {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
631 newarr append: (inst to2OpInst)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
632 } else: {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
633 newarr append: inst
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
634 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
635 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
636 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
637 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
638 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
639
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
640 toBackend <- :program :backend {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
641 prepped <- program map: :fun {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
642 backend adjustIL: fun
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
643 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
644 labels <- prepped map: :_ {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
645 backend label
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
646 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
647 outprog <- #[]
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
648 foreach: prepped :name instarr {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
649 outprog append: (labels get: name)
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
650 foreach: instarr :_ inst {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
651 backend convertIL: inst to: outprog withLabels: labels
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
652 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
653 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
654 outprog
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
655 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
656
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
657 main <- {
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
658 prog <- dict linear
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
659
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
660 fib <- #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
661 sub: 2 (arg: 0) (reg: 0) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
662 skipIf: ge #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
663 return: 1 q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
664 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
665 call: "fib" withArgs: #[reg: 0]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
666 mov: retr (reg: 1) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
667 add: 1 (reg: 0) (reg: 2) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
668 call: "fib" withArgs: #[reg: 2]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
669 add: retr (reg: 1) (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
670 return: (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
671 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
672 print: "Original:\n\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
673 foreach: fib :idx inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
674 print: (string: inst) . "\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
675 }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
676 prog set: "fib" fib
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
677
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
678 mprog <- prog toBackend: x86
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
679 ba <- bytearray executableFromBytes: mprog
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
680 res <- ba runWithArg: 30u64
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
681 print: (string: res) . "\n"
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
682 0
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
683 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
684 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
685 }