repos/blastem: segacd.c annotate

annotate segacd.c @ 2097:0407d812cb4a

Fix off-by-one in sega mapper heuristic

author	Michael Pavone <pavone@retrodev.com>
date	Mon, 07 Feb 2022 22:47:11 -0800
parents	ca6fc8c8dc60
children	b92c998c6742

rev	line source
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1 #include <stdlib.h>
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	2 #include <string.h>
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	3 #include "cd_graphics.h"
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	4 #include "genesis.h"
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	5 #include "util.h"
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	6
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	7 #define SCD_MCLKS 50000000
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	8 #define SCD_PERIPH_RESET_CLKS (SCD_MCLKS / 10)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	9 #define TIMER_TICK_CLKS 1536
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	10
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	11 enum {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	12 GA_SUB_CPU_CTRL,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	13 GA_MEM_MODE,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	14 GA_CDC_CTRL,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	15 GA_CDC_REG_DATA,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	16 GA_CDC_HOST_DATA,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	17 GA_CDC_DMA_ADDR,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	18 GA_STOP_WATCH,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	19 GA_COMM_FLAG,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	20 GA_COMM_CMD0,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	21 GA_COMM_CMD1,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	22 GA_COMM_CMD2,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	23 GA_COMM_CMD3,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	24 GA_COMM_CMD4,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	25 GA_COMM_CMD5,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	26 GA_COMM_CMD6,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	27 GA_COMM_CMD7,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	28 GA_COMM_STATUS0,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	29 GA_COMM_STATUS1,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	30 GA_COMM_STATUS2,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	31 GA_COMM_STATUS3,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	32 GA_COMM_STATUS4,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	33 GA_COMM_STATUS5,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	34 GA_COMM_STATUS6,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	35 GA_COMM_STATUS7,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	36 GA_TIMER,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	37 GA_INT_MASK,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	38 GA_CDD_FADER,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	39 GA_CDD_CTRL,
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	40 GA_CDD_STATUS0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	41 GA_CDD_STATUS1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	42 GA_CDD_STATUS2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	43 GA_CDD_STATUS3,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	44 GA_CDD_STATUS4,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	45 GA_CDD_CMD0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	46 GA_CDD_CMD1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	47 GA_CDD_CMD2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	48 GA_CDD_CMD3,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	49 GA_CDD_CMD4,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	50 GA_FONT_COLOR,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	51 GA_FONT_BITS,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	52 GA_FONT_DATA0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	53 GA_FONT_DATA1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	54 GA_FONT_DATA2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	55 GA_FONT_DATA3,
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	56
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	57 GA_HINT_VECTOR = GA_CDC_REG_DATA
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	58 };
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	59 //GA_SUB_CPU_CTRL
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	60 #define BIT_IEN2 0x8000
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	61 #define BIT_IFL2 0x0100
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	62 #define BIT_LEDG 0x0200
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	63 #define BIT_LEDR 0x0100
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	64 #define BIT_SBRQ 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	65 #define BIT_SRES 0x0001
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	66 #define BIT_PRES 0x0001
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	67 //GA_MEM_MODE
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	68 #define MASK_PROG_BANK 0x00C0
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	69 #define BIT_OVERWRITE 0x0010
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	70 #define BIT_UNDERWRITE 0x0008
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	71 #define MASK_PRIORITY (BIT_OVERWRITE\|BIT_UNDERWRITE)
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	72 #define BIT_MEM_MODE 0x0004
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	73 #define BIT_DMNA 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	74 #define BIT_RET 0x0001
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	75
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	76 //GA_CDC_CTRL
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	77 #define BIT_EDT 0x8000
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	78 #define BIT_DSR 0x4000
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	79
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	80 //GA_CDD_CTRL
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	81 #define BIT_MUTE 0x0100
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	82
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	83 enum {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	84 DST_MAIN_CPU = 2,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	85 DST_SUB_CPU,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	86 DST_PCM_RAM,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	87 DST_PROG_RAM,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	88 DST_WORD_RAM = 7
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	89 };
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	90
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	91 //GA_INT_MASK
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	92 #define BIT_MASK_IEN1 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	93 #define BIT_MASK_IEN2 0x0004
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	94 #define BIT_MASK_IEN3 0x0008
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	95 #define BIT_MASK_IEN4 0x0010
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	96 #define BIT_MASK_IEN5 0x0020
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	97 #define BIT_MASK_IEN6 0x0040
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	98
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	99 //GA_CDD_CTRL
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	100 #define BIT_HOCK 0x0004
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	101
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	102 static void prog_ram_wp_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	103 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	104 m68k_context *m68k = vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	105 segacd_context *cd = m68k->system;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	106 //if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 9) + 8)))) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	107 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	108 cd->prog_ram[address >> 1] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	109 m68k_invalidate_code_range(m68k, address, address + 2);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	110 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	111 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	112 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	113
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	114 static void prog_ram_wp_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	115 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	116 m68k_context *m68k = vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	117 segacd_context *cd = m68k->system;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	118 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	119 ((uint8_t *)cd->prog_ram)[address ^ 1] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	120 m68k_invalidate_code_range(m68k, address, address + 1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	121 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	122 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	123 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	124
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	125 static uint16_t word_ram_2M_read16(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	126 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	127 m68k_context *m68k = vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	128 //TODO: fixme for interleaving
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	129 uint16_t* bank = m68k->mem_pointers[1];
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	130 uint16_t raw = bank[address >> 2];
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	131 if (address & 2) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	132 return (raw & 0xF) \| (raw << 4 & 0xF00);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	133 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	134 return (raw >> 4 & 0xF00) \| (raw >> 8 & 0xF);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	135 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	136 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	137
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	138 static uint8_t word_ram_2M_read8(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	139 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	140 uint16_t word = word_ram_2M_read16(address, vcontext);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	141 if (address & 1) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	142 return word;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	143 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	144 return word >> 8;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	145 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	146
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	147 static void word_ram_2M_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	148 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	149 m68k_context *m68k = vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	150 segacd_context *cd = m68k->system;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	151 value &= 0xF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	152 uint16_t priority = cd->gate_array[GA_MEM_MODE] & MASK_PRIORITY;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	153
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	154 if (priority == BIT_OVERWRITE && !value) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	155 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	156 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	157 if (priority == BIT_UNDERWRITE) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	158 if (!value) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	159 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	160 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	161 uint8_t old = word_ram_2M_read8(address, vcontext);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	162 if (old) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	163 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	164 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	165 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	166 uint16_t* bank = m68k->mem_pointers[1];
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	167 uint16_t raw = bank[address >> 2];
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	168 uint16_t shift = ((address & 3) * 4);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	169 raw &= ~(0xF000 >> shift);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	170 raw \|= value << (12 - shift);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	171 bank[address >> 2] = raw;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	172 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	173 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	174
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	175
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	176 static void word_ram_2M_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	177 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	178 word_ram_2M_write8(address, vcontext, value >> 8);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	179 return word_ram_2M_write8(address + 1, vcontext, value);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	180 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	181
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	182 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	183 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	184 return 0;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	185 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	186
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	187 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	188 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	189 return 0;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	190 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	191
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	192 static void word_ram_1M_write16(uint32_t address, void vcontext, uint16_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	193 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	194 return vcontext;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	195 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	196
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	197 static void word_ram_1M_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	198 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	199 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	200 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	201
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	202
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	203 static uint16_t unmapped_prog_read16(uint32_t address, void *vcontext)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	204 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	205 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	206 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	207
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	208 static uint8_t unmapped_prog_read8(uint32_t address, void *vcontext)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	209 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	210 return 0xFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	211 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	212
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	213 static void unmapped_prog_write16(uint32_t address, void vcontext, uint16_t value)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	214 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	215 return vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	216 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	217
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	218 static void unmapped_prog_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	219 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	220 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	221 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	222
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	223 static uint16_t unmapped_word_read16(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	224 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	225 return 0xFFFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	226 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	227
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	228 static uint8_t unmapped_word_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	229 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	230 return 0xFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	231 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	232
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	233 static void unmapped_word_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	234 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	235 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	236 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	237
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	238 static void unmapped_word_write8(uint32_t address, void vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	239 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	240 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	241 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	242
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	243 static uint16_t cell_image_read16(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	244 {
2087 3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	245 uint32_t word_of_cell = address & 2;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	246 if (address < 0x10000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	247 //64x32 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	248 uint32_t line_of_column = address & 0x3FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	249 uint32_t column = address & 0xFC00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	250 address = (line_of_column << 6) \| (column >> 8) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	251 } else if (address < 0x18000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	252 //64x16 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	253 uint32_t line_of_column = address & 0x1FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	254 uint32_t column = address & 0x7E00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	255 address = 0x10000 \| (line_of_column << 6) \| (column >> 7) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	256 } else if (address < 0x1C000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	257 //64x8 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	258 uint32_t line_of_column = address & 0x00FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	259 uint32_t column = address & 0x3F00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	260 address = 0x18000 \| (line_of_column << 6) \| (column >> 6) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	261 } else {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	262 //64x4 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	263 uint32_t line_of_column = address & 0x007C;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	264 uint32_t column = address & 0x1F80;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	265 address &= 0x1E000;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	266 address \|= (line_of_column << 6) \| (column >> 5) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	267 }
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	268 m68k_context *m68k = vcontext;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	269 genesis_context *gen = m68k->system;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	270 segacd_context *cd = gen->expansion;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	271 return m68k->mem_pointers[cd->memptr_start_index + 1][address>>1];
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	272 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	273
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	274 static uint8_t cell_image_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	275 {
2087 3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	276 uint16_t word = cell_image_read16(address & 0xFFFFFE, vcontext);
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	277 if (address & 1) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	278 return word;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	279 }
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	280 return word >> 8;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	281 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	282
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	283 static void cell_image_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	284 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	285 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	286 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	287
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	288 static void cell_image_write8(uint32_t address, void vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	289 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	290 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	291 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	292
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	293 static uint8_t pcm_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	294 {
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	295 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	296 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	297 if (address & 1) {
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	298 rf5c164_run(&cd->pcm, m68k->current_cycle);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	299 return rf5c164_read(&cd->pcm, address >> 1);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	300 } else {
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	301 return 0xFF;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	302 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	303 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	304
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	305 static uint16_t pcm_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	306 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	307 return 0xFF00 \| pcm_read8(address+1, vcontext);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	308 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	309
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	310 static void pcm_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	311 {
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	312 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	313 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	314 if (address & 1) {
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	315 rf5c164_run(&cd->pcm, m68k->current_cycle);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	316 rf5c164_write(&cd->pcm, address >> 1, value);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	317 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	318 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	319 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	320
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	321 static void pcm_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	322 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	323 return pcm_write8(address+1, vcontext, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	324 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	325
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	326
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	327 static void timers_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	328 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	329 if (cycle <= cd->stopwatch_cycle) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	330 return;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	331 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	332 uint32_t ticks = (cycle - cd->stopwatch_cycle) / TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	333 cd->stopwatch_cycle += ticks * TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	334 cd->gate_array[GA_STOP_WATCH] += ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	335 cd->gate_array[GA_STOP_WATCH] &= 0xFFF;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	336 if (ticks && !cd->timer_value) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	337 --ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	338 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	339 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	340 if (ticks && cd->timer_value) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	341 while (ticks >= (cd->timer_value + 1)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	342 ticks -= cd->timer_value + 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	343 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	344 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	345 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	346 cd->timer_value -= ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	347 if (!cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	348 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	349 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	350 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	351 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	352
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	353 static void cdd_run(segacd_context *cd, uint32_t cycle)
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	354 {
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	355 cdd_mcu_run(&cd->cdd, cycle, cd->gate_array + GA_CDD_CTRL, &cd->cdc, &cd->fader);
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	356 lc8951_run(&cd->cdc, cycle);
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	357 }
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	358
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	359 static uint32_t next_timer_int(segacd_context *cd)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	360 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	361 if (cd->timer_pending) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	362 return cd->stopwatch_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	363 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	364 if (cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	365 return cd->stopwatch_cycle + TIMER_TICK_CLKS * cd->timer_value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	366 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	367 if (cd->gate_array[GA_TIMER]) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	368 return cd->stopwatch_cycle + TIMER_TICK_CLKS * (cd->gate_array[GA_TIMER] + 1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	369 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	370 return CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	371 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	372
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	373 static void calculate_target_cycle(m68k_context * context)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	374 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	375 segacd_context *cd = context->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	376 context->int_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	377 uint8_t mask = context->status & 0x7;
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	378 uint32_t cdc_cycle = CYCLE_NEVER;
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	379 if (mask < 5) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	380 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN5) {
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	381 cdc_cycle = lc8951_next_interrupt(&cd->cdc);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	382 //CDC interrupts only generated on falling edge of !INT signal
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	383 if (cd->cdc_int_ack) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	384 if (cdc_cycle > cd->cdc.cycle) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	385 cd->cdc_int_ack = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	386 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	387 cdc_cycle = CYCLE_NEVER;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	388 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	389 }
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	390 if (cdc_cycle < context->int_cycle) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	391 context->int_cycle = cdc_cycle;
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	392 context->int_num = 5;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	393 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	394 }
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	395 if (mask < 4) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	396 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN4) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	397 uint32_t cdd_cycle = cd->cdd.int_pending ? context->current_cycle : cd->cdd.next_int_cycle;
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	398 if (cdd_cycle < context->int_cycle) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	399 context->int_cycle = cdd_cycle;
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	400 context->int_num = 4;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	401 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	402 }
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	403 if (mask < 3) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	404 uint32_t next_timer;
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	405 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN3) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	406 uint32_t next_timer_cycle = next_timer_int(cd);
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	407 if (next_timer_cycle < context->int_cycle) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	408 context->int_cycle = next_timer_cycle;
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	409 context->int_num = 3;
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	410 }
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	411 }
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	412 if (mask < 2) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	413 if (cd->int2_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) {
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	414 context->int_cycle = cd->int2_cycle;
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	415 context->int_num = 2;
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	416 }
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	417 if (mask < 1) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	418 if (cd->graphics_int_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN1)) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	419 context->int_cycle = cd->graphics_int_cycle;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	420 context->int_num = 1;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	421 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	422 }
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	423 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	424 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	425 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	426 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	427 if (context->int_cycle > context->current_cycle && context->int_pending == INT_PENDING_SR_CHANGE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	428 context->int_pending = INT_PENDING_NONE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	429 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	430 if (context->current_cycle >= context->sync_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	431 context->should_return = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	432 context->target_cycle = context->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	433 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	434 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	435 if (context->status & M68K_STATUS_TRACE \|\| context->trace_pending) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	436 context->target_cycle = context->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	437 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	438 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	439 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	440 if (context->target_cycle == cdc_cycle && context->int_num == 5) {
ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	441 uint32_t before = context->target_cycle - 2 * cd->cdc.clock_step;
ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	442 if (before > context->current_cycle) {
ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	443 context->target_cycle = context->sync_cycle = before;
ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	444 }
ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	445 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	446 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	447
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	448 static uint16_t sub_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	449 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	450 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	451 segacd_context *cd = m68k->system;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	452 uint32_t reg = address >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	453 switch (reg)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	454 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	455 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	456 uint16_t value = cd->gate_array[reg] & 0xFFFE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	457 if (cd->periph_reset_cycle == CYCLE_NEVER \|\| (m68k->current_cycle - cd->periph_reset_cycle) > SCD_PERIPH_RESET_CLKS) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	458 value \|= BIT_PRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	459 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	460 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	461 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	462 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	463 return cd->gate_array[reg] & 0xFF1F;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	464 case GA_CDC_CTRL:
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	465 cdd_run(cd, m68k->current_cycle);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	466 return cd->gate_array[reg] \| cd->cdc.ar;
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	467 case GA_CDC_REG_DATA:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	468 cdd_run(cd, m68k->current_cycle);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	469 return lc8951_reg_read(&cd->cdc);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	470 case GA_CDC_HOST_DATA: {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	471 cdd_run(cd, m68k->current_cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	472 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	473 if (dst == DST_SUB_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	474 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	475 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	476 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	477 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	478 calculate_target_cycle(cd->m68k);
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	479
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	480 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	481 return cd->gate_array[reg];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	482 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	483 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	484 case GA_TIMER:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	485 timers_run(cd, m68k->current_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	486 return cd->gate_array[reg];
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	487 case GA_CDD_STATUS0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	488 case GA_CDD_STATUS1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	489 case GA_CDD_STATUS2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	490 case GA_CDD_STATUS3:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	491 case GA_CDD_STATUS4:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	492 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	493 return cd->gate_array[reg];
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	494 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	495 case GA_FONT_DATA0:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	496 case GA_FONT_DATA1:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	497 case GA_FONT_DATA2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	498 case GA_FONT_DATA3: {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	499 uint16_t shift = 4 * (3 - (reg - GA_FONT_DATA0));
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	500 uint16_t value = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	501 uint16_t fg = cd->gate_array[GA_FONT_COLOR] >> 4;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	502 uint16_t bg = cd->gate_array[GA_FONT_COLOR] & 0xF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	503 for (int i = 0; i < 4; i++) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	504 uint16_t pixel = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	505 if (cd->gate_array[GA_FONT_BITS] & 1 << (shift + i)) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	506 pixel = fg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	507 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	508 pixel = bg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	509 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	510 value \|= pixel << (i * 4);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	511 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	512 return value;
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	513 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	514 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	515 //these two have bits that change based on graphics operations
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	516 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	517 return cd->gate_array[reg];
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	518 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	519 //write only
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	520 return 0xFFFF;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	521 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	522 default:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	523 return cd->gate_array[reg];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	524 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	525 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	526
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	527 static uint8_t sub_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	528 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	529 uint16_t val = sub_gate_read16(address, vcontext);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	530 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	531 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	532
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	533 static void sub_gate_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	534 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	535 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	536 segacd_context *cd = m68k->system;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	537 uint32_t reg = address >> 1;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	538 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	539 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	540 case GA_SUB_CPU_CTRL:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	541 cd->gate_array[reg] &= 0xF0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	542 cd->gate_array[reg] \|= value & (BIT_LEDG\|BIT_LEDR);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	543 if (value & BIT_PRES) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	544 cd->periph_reset_cycle = m68k->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	545 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	546 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	547 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	548 uint16_t changed = value ^ cd->gate_array[reg];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	549 genesis_context *gen = cd->genesis;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	550 if (changed & BIT_MEM_MODE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	551 //FIXME: ram banks are supposed to be interleaved when in 2M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	552 cd->gate_array[reg] &= ~BIT_DMNA;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	553 if (value & BIT_MEM_MODE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	554 //switch to 1M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	555 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = (value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	556 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	557 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	558 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	559 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	560 //switch to 2M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	561 if (value & BIT_RET) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	562 //Main CPU will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	563 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	564 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	565 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	566 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	567 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	568 //sub cpu will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	569 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	570 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	571 m68k->mem_pointers[0] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	572 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	573 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	574 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	575 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	576 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	577 } else if (changed & BIT_RET) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	578 if (value & BIT_MEM_MODE) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	579 cd->gate_array[reg] &= ~BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	580 //swapping banks in 1M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	581 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = (value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	582 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	583 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	584 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	585 } else if (value & BIT_RET) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	586 cd->gate_array[reg] &= ~BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	587 //giving word ram to main CPU in 2M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	588 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	589 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	590 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	591 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	592 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	593 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	594 value \|= BIT_RET;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	595 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	596 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	597 cd->gate_array[reg] &= 0xFFC2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	598 cd->gate_array[reg] \|= value & (BIT_RET\|BIT_MEM_MODE\|MASK_PRIORITY);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	599 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	600 }
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	601 case GA_CDC_CTRL:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	602 cdd_run(cd, m68k->current_cycle);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	603 lc8951_ar_write(&cd->cdc, value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	604 //cd->gate_array[reg] &= 0xC000;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	605 //apparently this clears EDT, should it also clear DSR?
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	606 cd->gate_array[reg] = value & 0x0700;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	607 cd->cdc_dst_low = 0;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	608 break;
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	609 case GA_CDC_REG_DATA:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	610 cdd_run(cd, m68k->current_cycle);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	611 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	612 lc8951_reg_write(&cd->cdc, value);
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	613 calculate_target_cycle(m68k);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	614 break;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	615 case GA_CDC_DMA_ADDR:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	616 cdd_run(cd, m68k->current_cycle);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	617 cd->gate_array[reg] = value;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	618 cd->cdc_dst_low = 0;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	619 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	620 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	621 //docs say you should only write zero to reset
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	622 //mcd-verificator comments suggest any value will reset
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	623 timers_run(cd, m68k->current_cycle);
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	624 cd->gate_array[reg] = 0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	625 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	626 case GA_COMM_FLAG:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	627 cd->gate_array[reg] &= 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	628 cd->gate_array[reg] \|= value & 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	629 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	630 case GA_COMM_STATUS0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	631 case GA_COMM_STATUS1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	632 case GA_COMM_STATUS2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	633 case GA_COMM_STATUS3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	634 case GA_COMM_STATUS4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	635 case GA_COMM_STATUS5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	636 case GA_COMM_STATUS6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	637 case GA_COMM_STATUS7:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	638 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	639 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	640 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	641 case GA_TIMER:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	642 timers_run(cd, m68k->current_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	643 cd->gate_array[reg] = value & 0xFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	644 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	645 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	646 case GA_INT_MASK:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	647 cd->gate_array[reg] = value & (BIT_MASK_IEN6\|BIT_MASK_IEN5\|BIT_MASK_IEN4\|BIT_MASK_IEN3\|BIT_MASK_IEN2\|BIT_MASK_IEN1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	648 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	649 break;
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	650 case GA_CDD_FADER:
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	651 cdd_run(cd, m68k->current_cycle);
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	652 value &= 0x7FFF;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	653 cdd_fader_attenuation_write(&cd->fader, value);
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	654 cd->gate_array[reg] &= 0x8000;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	655 cd->gate_array[reg] \|= value;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	656 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	657 case GA_CDD_CTRL: {
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	658 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	659 uint16_t changed = cd->gate_array[reg] ^ value;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	660 if (changed & BIT_HOCK) {
2073 c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response Michael Pavone <pavone@retrodev.com> parents: 2069 diff changeset	661 cd->gate_array[reg] &= ~BIT_HOCK;
c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response Michael Pavone <pavone@retrodev.com> parents: 2069 diff changeset	662 cd->gate_array[reg] \|= value & BIT_HOCK;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	663 if (value & BIT_HOCK) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	664 cdd_hock_enabled(&cd->cdd);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	665 } else {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	666 cdd_hock_disabled(&cd->cdd);
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	667 cd->gate_array[reg] \|= BIT_MUTE;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	668 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	669 calculate_target_cycle(m68k);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	670 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	671 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	672 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	673 case GA_CDD_CMD0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	674 case GA_CDD_CMD1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	675 case GA_CDD_CMD2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	676 case GA_CDD_CMD3:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	677 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	678 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	679 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	680 case GA_CDD_CMD4:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	681 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	682 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	683 cdd_mcu_start_cmd_recv(&cd->cdd, cd->gate_array + GA_CDD_CTRL);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	684 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	685 case GA_FONT_COLOR:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	686 cd->gate_array[reg] = value & 0xFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	687 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	688 case GA_FONT_BITS:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	689 cd->gate_array[reg] = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	690 break;
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	691 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	692 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	693 cd->gate_array[reg] &= BIT_GRON;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	694 cd->gate_array[reg] \|= value & (BIT_SMS\|BIT_STS\|BIT_RPT);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	695 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	696 case GA_STAMP_MAP_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	697 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	698 cd->gate_array[reg] = value & 0xFFE0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	699 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	700 case GA_IMAGE_BUFFER_VCELLS:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	701 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	702 cd->gate_array[reg] = value & 0x1F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	703 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	704 case GA_IMAGE_BUFFER_START:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	705 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	706 cd->gate_array[reg] = value & 0xFFF8;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	707 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	708 case GA_IMAGE_BUFFER_OFFSET:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	709 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	710 cd->gate_array[reg] = value & 0x3F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	711 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	712 case GA_IMAGE_BUFFER_HDOTS:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	713 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	714 cd->gate_array[reg] = value & 0x1FF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	715 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	716 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	717 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	718 cd->gate_array[reg] = value & 0xFF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	719 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	720 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	721 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	722 cd->gate_array[reg] = value & 0xFFFE;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	723 cd_graphics_start(cd);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	724 break;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	725 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	726 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	727 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	728 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	729 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	730
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	731 static void sub_gate_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	732 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	733 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	734 segacd_context *cd = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	735 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	736 uint16_t value16;
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	737 switch (address >> 1)
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	738 {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	739 case GA_CDC_HOST_DATA:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	740 case GA_CDC_DMA_ADDR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	741 case GA_STOP_WATCH:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	742 case GA_COMM_FLAG:
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	743 case GA_TIMER:
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	744 case GA_CDD_FADER:
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	745 case GA_FONT_COLOR:
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	746 //these registers treat all writes as word-wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	747 value16 = value \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	748 break;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	749 case GA_CDC_CTRL:
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	750 if (address & 1) {
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	751 lc8951_ar_write(&cd->cdc, value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	752 return vcontext;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	753 } else {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	754 value16 = cd->cdc.ar \| (value << 8);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	755 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	756 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	757 case GA_CDD_CMD4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	758 if (!address) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	759 //byte write to $FF804A should not trigger transfer
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	760 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	761 cd->gate_array[reg] &= 0x0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	762 cd->gate_array[reg] \|= (value << 8 & 0x0F00);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	763 return vcontext;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	764 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	765 //intentional fallthrough for $FF804B
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	766 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	767 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	768 value16 = cd->gate_array[reg] & 0xFF00 \| value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	769 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	770 value16 = cd->gate_array[reg] & 0xFF \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	771 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	772 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	773 return sub_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	774 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	775
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	776 static uint8_t handle_cdc_byte(void *vsys, uint8_t value)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	777 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	778 segacd_context *cd = vsys;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	779 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	780 //host reg is already full, pause transfer
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	781 return 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	782 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	783 if (cd->cdc.cycle == cd->cdc.transfer_end) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	784 cd->gate_array[GA_CDC_CTRL] \|= BIT_EDT;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	785 printf("EDT set at %u\n", cd->cdc.cycle);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	786 }
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	787 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	788 if (!(cd->cdc_dst_low & 1)) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	789 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	790 cd->gate_array[GA_CDC_HOST_DATA] \|= value << 8;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	791 cd->cdc_dst_low++;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	792 if (dest != DST_PCM_RAM) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	793 //PCM RAM writes a byte at a time
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	794 return 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	795 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	796 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	797 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF00;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	798 cd->gate_array[GA_CDC_HOST_DATA] \|= value;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	799 }
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	800
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	801 uint32_t dma_addr = cd->gate_array[GA_CDC_DMA_ADDR] << 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	802 dma_addr \|= cd->cdc_dst_low;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	803 switch (dest)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	804 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	805 case DST_MAIN_CPU:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	806 case DST_SUB_CPU:
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	807 cd->cdc_dst_low = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	808 cd->gate_array[GA_CDC_CTRL] \|= BIT_DSR;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	809 printf("DSR set at %u, (transfer_end %u, dbcl %X, dbch %X)\n", cd->cdc.cycle, cd->cdc.transfer_end, cd->cdc.regs[2], cd->cdc.regs[3]);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	810 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	811 case DST_PCM_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	812 dma_addr &= (1 << 13) - 1;
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	813 rf5c164_run(&cd->pcm, cd->cdc.cycle);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	814 rf5c164_write(&cd->pcm, 0x1000 \| (dma_addr >> 1), value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	815 dma_addr += 2;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	816 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	817 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	818 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	819 case DST_PROG_RAM:
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	820 cd->prog_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	821 m68k_invalidate_code_range(cd->m68k, dma_addr - 1, dma_addr + 1);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	822 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	823 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	824 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	825 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	826 case DST_WORD_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	827 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	828 //1M mode, write to bank assigned to Sub CPU
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	829 dma_addr &= (1 << 17) - 1;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	830 cd->m68k->mem_pointers[1][dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	831 m68k_invalidate_code_range(cd->m68k, 0x0C0000 + dma_addr - 1, 0x0C0000 + dma_addr + 1);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	832 } else {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	833 //2M mode, check if Sub CPU has access
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	834 if (!(cd->gate_array[GA_MEM_MODE] & BIT_RET)) {
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	835 cd_graphics_run(cd, cd->cdc.cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	836 dma_addr &= (1 << 18) - 1;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	837 cd->word_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	838 m68k_invalidate_code_range(cd->m68k, 0x080000 + dma_addr, 0x080000 + dma_addr + 1);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	839 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	840 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	841 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	842 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	843 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	844 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	845 default:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	846 printf("Invalid CDC transfer destination %d\n", dest);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	847 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	848 return 1;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	849 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	850
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	851 static uint8_t can_main_access_prog(segacd_context *cd)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	852 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	853 //TODO: use actual busack
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	854 return cd->busreq \|\| !cd->reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	855 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	856
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	857 static void scd_peripherals_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	858 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	859 timers_run(cd, cycle);
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	860 cdd_run(cd, cycle);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	861 cd_graphics_run(cd, cycle);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	862 rf5c164_run(&cd->pcm, cycle);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	863 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	864
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	865 static m68k_context sync_components(m68k_context context, uint32_t address)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	866 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	867 segacd_context *cd = context->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	868 scd_peripherals_run(cd, context->current_cycle);
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	869 if (context->int_ack) {
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	870 printf("int ack %d\n", context->int_ack);
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	871 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	872 switch (context->int_ack)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	873 {
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	874 case 1:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	875 cd->graphics_int_cycle = CYCLE_NEVER;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	876 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	877 case 2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	878 cd->int2_cycle = CYCLE_NEVER;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	879 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	880 case 3:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	881 cd->timer_pending = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	882 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	883 case 4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	884 cd->cdd.int_pending = 0;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	885 break;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	886 case 5:
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	887 cd->cdc_int_ack = 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	888 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	889 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	890 context->int_ack = 0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	891 calculate_target_cycle(context);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	892 return context;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	893 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	894
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	895 void scd_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	896 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	897 uint8_t m68k_run = !can_main_access_prog(cd);
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	898 while (cycle > cd->m68k->current_cycle) {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	899 if (m68k_run) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	900 uint32_t start = cd->m68k->current_cycle;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	901 cd->m68k->sync_cycle = cycle;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	902 if (cd->need_reset) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	903 cd->need_reset = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	904 m68k_reset(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	905 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	906 calculate_target_cycle(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	907 resume_68k(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	908 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	909 } else {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	910 cd->m68k->current_cycle = cycle;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	911 }
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	912 scd_peripherals_run(cd, cd->m68k->current_cycle);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	913 }
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	914
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	915 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	916
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	917 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	918 {
2055 c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	919 return ((uint64_t)cycle) * ((uint64_t)SCD_MCLKS) / ((uint64_t)gen->normal_clock);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	920 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	921
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	922 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	923 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	924 deduction = gen_cycle_to_scd(deduction, cd->genesis);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	925 cd->m68k->current_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	926 cd->stopwatch_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	927 if (deduction >= cd->int2_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	928 cd->int2_cycle = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	929 } else if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	930 cd->int2_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	931 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	932 if (deduction >= cd->periph_reset_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	933 cd->periph_reset_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	934 } else if (cd->periph_reset_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	935 cd->periph_reset_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	936 }
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	937 cdd_mcu_adjust_cycle(&cd->cdd, deduction);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	938 lc8951_adjust_cycles(&cd->cdc, deduction);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	939 cd->graphics_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	940 if (cd->graphics_int_cycle != CYCLE_NEVER) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	941 if (cd->graphics_int_cycle > deduction) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	942 cd->graphics_int_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	943 } else {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	944 cd->graphics_int_cycle = 0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	945 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	946 }
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	947 cd->pcm.cycle -= deduction;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	948 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	949
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	950 static uint16_t main_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	951 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	952 m68k_context *m68k = vcontext;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	953 genesis_context *gen = m68k->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	954 segacd_context *cd = gen->expansion;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	955 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	956 scd_run(cd, scd_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	957 uint32_t offset = (address & 0x1FF) >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	958 switch (offset)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	959 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	960 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	961 uint16_t value = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	962 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	963 value \|= BIT_IEN2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	964 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	965 if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	966 value \|= BIT_IFL2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	967 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	968 if (can_main_access_prog(cd)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	969 value \|= BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	970 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	971 if (cd->reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	972 value \|= BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	973 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	974 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	975 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	976 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	977 //Main CPU can't read priority mode bits
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	978 return cd->gate_array[offset] & 0xFFE7;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	979 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	980 return cd->rom_mut[0x72/2];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	981 case GA_CDC_HOST_DATA: {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	982 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	983 if (dst == DST_MAIN_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	984 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	985 printf("DSR cleared at %u (%u)\n", scd_cycle, cd->cdc.cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	986 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	987 lc8951_resume_transfer(&cd->cdc, scd_cycle);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	988 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	989 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	990 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	991 calculate_target_cycle(cd->m68k);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	992 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	993 return cd->gate_array[offset];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	994 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	995 case GA_CDC_DMA_ADDR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	996 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	997 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	998 default:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	999 if (offset < GA_TIMER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1000 return cd->gate_array[offset];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1001 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1002 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1003 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1004 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1005 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1006
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1007 static uint8_t main_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1008 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1009 uint16_t val = main_gate_read16(address & 0xFE, vcontext);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1010 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1011 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1012
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1013 static void dump_prog_ram(segacd_context *cd)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1014 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1015 static int dump_count;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1016 char fname[256];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1017 sprintf(fname, "prog_ram_%d.bin", dump_count++);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1018 FILE *f = fopen(fname, "wb");
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1019 if (f) {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1020 uint32_t last = 256*1024-1;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1021 for(; last > 0; --last)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1022 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1023 if (cd->prog_ram[last]) {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1024 break;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1025 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1026 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1027 for (uint32_t i = 0; i <= last; i++)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1028 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1029 uint8_t pair[2];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1030 pair[0] = cd->prog_ram[i] >> 8;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1031 pair[1] = cd->prog_ram[i];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1032 fwrite(pair, 1, sizeof(pair), f);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1033 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1034
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1035 fclose(f);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1036 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1037 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1038
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1039 static void main_gate_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1040 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1041 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1042 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1043 segacd_context *cd = gen->expansion;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1044 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1045 scd_run(cd, scd_cycle);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1046 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1047 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1048 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1049 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1050 uint8_t old_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1051 cd->busreq = value & BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1052 uint8_t old_reset = cd->reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1053 cd->reset = value & BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1054 if (cd->reset && !old_reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1055 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1056 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1057 if (value & BIT_IFL2) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1058 cd->int2_cycle = scd_cycle;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1059 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1060 /*cd->gate_array[reg] &= 0x7FFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1061 cd->gate_array[reg] \|= value & 0x8000;*/
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1062 uint8_t new_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1063 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1064 if (new_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1065 if (!old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1066 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1067 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1068 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1069 } else if (old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1070 m68k->mem_pointers[cd->memptr_start_index] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1071 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1072 m68k_invalidate_code_range(cd->m68k, bank * 0x20000, (bank + 1) * 0x20000);
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1073 if (!new_access) {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1074 dump_prog_ram(cd);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1075 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1076 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1077 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1078 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1079 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1080 uint16_t changed = cd->gate_array[reg] ^ value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1081 //Main CPU can't write priority mode bits, MODE or RET
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1082 cd->gate_array[reg] &= 0x001F;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1083 cd->gate_array[reg] \|= value & 0xFFC0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1084 if ((cd->gate_array[reg] & BIT_MEM_MODE)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1085 //1M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1086 if (!(value & BIT_DMNA)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1087 cd->gate_array[reg] \|= BIT_DMNA;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1088 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1089 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1090 //2M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1091 if (changed & value & BIT_DMNA) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1092 cd->gate_array[reg] \|= BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1093 m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1094 m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1095 cd->m68k->mem_pointers[0] = cd->word_ram;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1096 cd->gate_array[reg] &= ~BIT_RET;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1097
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1098 m68k_invalidate_code_range(m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1099 m68k_invalidate_code_range(cd->m68k, 0x080000, 0x0C0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1100 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1101 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1102 if (changed & MASK_PROG_BANK && can_main_access_prog(cd)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1103 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
2055 c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	1104 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1105 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1106 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1107 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1108 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1109 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1110 cd->rom_mut[0x72/2] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1111 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1112 case GA_COMM_FLAG:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1113 //Main CPU can only write the upper byte;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1114 cd->gate_array[reg] &= 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1115 cd->gate_array[reg] \|= value & 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1116 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1117 case GA_COMM_CMD0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1118 case GA_COMM_CMD1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1119 case GA_COMM_CMD2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1120 case GA_COMM_CMD3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1121 case GA_COMM_CMD4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1122 case GA_COMM_CMD5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1123 case GA_COMM_CMD6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1124 case GA_COMM_CMD7:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1125 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1126 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1127 break;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1128 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1129 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1130 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1131 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1132 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1133
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1134 static void main_gate_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1135 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1136 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1137 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1138 segacd_context *cd = gen->expansion;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1139 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1140 uint16_t value16;
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1141 switch (reg >> 1)
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1142 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1143 case GA_SUB_CPU_CTRL:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1144 if (address & 1) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1145 value16 = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1146 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1147 value16 = value << 8;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1148 if (cd->reset) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1149 value16 \|= BIT_SRES;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1150 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1151 if (cd->busreq) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1152 value16 \|= BIT_SBRQ;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1153 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1154 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1155 break;
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1156 case GA_HINT_VECTOR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1157 case GA_COMM_FLAG:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1158 //writes to these regs are always treated as word wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1159 value16 = value \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1160 break;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1161 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1162 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1163 value16 = cd->gate_array[reg] & 0xFF00 \| value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1164 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1165 value16 = cd->gate_array[reg] & 0xFF \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1166 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1167 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1168 return main_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1169 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1170
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1171 segacd_context alloc_configure_segacd(system_media media, uint32_t opts, uint8_t force_region, rom_info *info)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1172 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1173 static memmap_chunk sub_cpu_map[] = {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1174 {0x000000, 0x01FEFF, 0xFFFFFF, .flags=MMAP_READ \| MMAP_CODE, .write_16 = prog_ram_wp_write16, .write_8 = prog_ram_wp_write8},
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1175 {0x01FF00, 0x07FFFF, 0xFFFFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE},
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1176 {0x080000, 0x0BFFFF, 0x03FFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE \| MMAP_PTR_IDX \| MMAP_FUNC_NULL, .ptr_index = 0,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1177 .read_16 = word_ram_2M_read16, .write_16 = word_ram_2M_write16, .read_8 = word_ram_2M_read8, .write_8 = word_ram_2M_write8},
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1178 {0x0C0000, 0x0DFFFF, 0x01FFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE \| MMAP_PTR_IDX \| MMAP_FUNC_NULL, .ptr_index = 1,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1179 .read_16 = word_ram_1M_read16, .write_16 = word_ram_1M_write16, .read_8 = word_ram_1M_read8, .write_8 = word_ram_1M_write8},
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1180 {0xFE0000, 0xFEFFFF, 0x003FFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_ONLY_ODD},
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1181 {0xFF0000, 0xFF7FFF, 0x003FFF, .read_16 = pcm_read16, .write_16 = pcm_write16, .read_8 = pcm_read8, .write_8 = pcm_write8},
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1182 {0xFF8000, 0xFF81FF, 0x0001FF, .read_16 = sub_gate_read16, .write_16 = sub_gate_write16, .read_8 = sub_gate_read8, .write_8 = sub_gate_write8}
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1183 };
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1184
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1185 segacd_context *cd = calloc(sizeof(segacd_context), 1);
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1186 uint32_t firmware_size;
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1187 cd->rom = (uint16_t *)read_bundled_file("cdbios.bin", &firmware_size);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1188 uint32_t adjusted_size = nearest_pow2(firmware_size);
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1189 if (adjusted_size != firmware_size) {
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1190 cd->rom = realloc(cd->rom, adjusted_size);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1191 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1192 cd->rom_mut = malloc(adjusted_size);
1503 a763523dadf4 Added code for initializing a combined Genesis + Sega CD system when a Sega CD ISO is loaded Michael Pavone <pavone@retrodev.com> parents: 1502 diff changeset	1193 byteswap_rom(adjusted_size, cd->rom);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1194 memcpy(cd->rom_mut, cd->rom, adjusted_size);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1195 cd->rom_mut[0x72/2] = 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1196
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1197 //memset(info, 0, sizeof(*info));
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1198 //tern_node *db = get_rom_db();
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1199 //*info = configure_rom(db, media->buffer, media->size, media->chain ? media->chain->buffer : NULL, media->chain ? media->chain->size : 0, NULL, 0);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1200
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1201 cd->prog_ram = calloc(512*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1202 cd->word_ram = calloc(256*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1203 cd->pcm_ram = calloc(64*1024, 1);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1204 //TODO: Load state from file
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1205 cd->bram = calloc(8*1024, 1);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1206
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1207
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1208 sub_cpu_map[0].buffer = sub_cpu_map[1].buffer = cd->prog_ram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1209 sub_cpu_map[4].buffer = cd->bram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1210 m68k_options *mopts = malloc(sizeof(m68k_options));
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1211 init_m68k_opts(mopts, sub_cpu_map, sizeof(sub_cpu_map) / sizeof(*sub_cpu_map), 4, sync_components);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1212 cd->m68k = init_68k_context(mopts, NULL);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1213 cd->m68k->system = cd;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1214 cd->int2_cycle = CYCLE_NEVER;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1215 cd->busreq = 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1216 cd->busack = 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1217 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1218 cd->reset = 1; //active low, so reset is not active on start
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1219 cd->memptr_start_index = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1220 cd->gate_array[1] = 1;
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	1221 cd->gate_array[GA_CDD_CTRL] = BIT_MUTE; //Data/mute flag is set on start
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1222 lc8951_init(&cd->cdc, handle_cdc_byte, cd);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1223 if (media->chain && media->type != MEDIA_CDROM) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1224 media = media->chain;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1225 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1226 cdd_mcu_init(&cd->cdd, media);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1227 cd_graphics_init(cd);
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	1228 cdd_fader_init(&cd->fader);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	1229 rf5c164_init(&cd->pcm, SCD_MCLKS, 4);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1230 return cd;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1231 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1232
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1233 memmap_chunk segacd_main_cpu_map(segacd_context cd, uint8_t cart_boot, uint32_t *num_chunks)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1234 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1235 static memmap_chunk main_cpu_map[] = {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1236 {0x000000, 0x01FFFF, 0x01FFFF, .flags=MMAP_READ},
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1237 {0x020000, 0x03FFFF, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 0,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1238 .read_16 = unmapped_prog_read16, .write_16 = unmapped_prog_write16, .read_8 = unmapped_prog_read8, .write_8 = unmapped_prog_write8},
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1239 {0x040000, 0x05FFFF, 0x01FFFF, .flags=MMAP_READ}, //first ROM alias
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1240 //TODO: additional ROM/prog RAM aliases
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1241 {0x200000, 0x21FFFF, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1242 .read_16 = unmapped_word_read16, .write_16 = unmapped_word_write16, .read_8 = unmapped_word_read8, .write_8 = unmapped_word_write8},
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1243 {0x220000, 0x23FFFF, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1244 .read_16 = cell_image_read16, .write_16 = cell_image_write16, .read_8 = cell_image_read8, .write_8 = cell_image_write8},
1504 95b3a1a8b26c Add mapping for gate array registers in main cpu map Michael Pavone <pavone@retrodev.com> parents: 1503 diff changeset	1245 {0xA12000, 0xA12FFF, 0xFFFFFF, .read_16 = main_gate_read16, .write_16 = main_gate_write16, .read_8 = main_gate_read8, .write_8 = main_gate_write8}
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1246 };
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1247 for (int i = 0; i < sizeof(main_cpu_map) / sizeof(*main_cpu_map); i++)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1248 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1249 if (main_cpu_map[i].start < 0x800000) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1250 if (cart_boot) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1251 main_cpu_map[i].start \|= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1252 main_cpu_map[i].end \|= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1253 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1254 main_cpu_map[i].start &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1255 main_cpu_map[i].end &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1256 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1257 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1258 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1259 //TODO: support BRAM cart
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1260 main_cpu_map[0].buffer = cd->rom_mut;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1261 main_cpu_map[2].buffer = cd->rom;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1262 main_cpu_map[1].buffer = cd->prog_ram;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1263 main_cpu_map[3].buffer = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1264 main_cpu_map[4].buffer = cd->word_ram + 0x10000;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1265 num_chunks = sizeof(main_cpu_map) / sizeof(main_cpu_map);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1266 return main_cpu_map;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1267 }

Mercurial > repos > blastem

annotate segacd.c @ 2097:0407d812cb4a