Mercurial > repos > blastem
annotate backend_x86.c @ 1466:f2ee46d08b01
Push correct PC onto stack on divide by zero for pc-relative case
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 13 Sep 2017 21:13:11 -0700 |
parents | 5d41d0574863 |
children | 2a5649a767e7 |
rev | line source |
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567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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1 #include "backend.h" |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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2 #include "gen_x86.h" |
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3 #include <string.h> |
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Michael Pavone <pavone@retrodev.com>
parents:
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4 |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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5 void cycles(cpu_options *opts, uint32_t num) |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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6 { |
1047
6b07af1515b5
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Michael Pavone <pavone@retrodev.com>
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7 if (opts->limit < 0) { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
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8 sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); |
6b07af1515b5
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Michael Pavone <pavone@retrodev.com>
parents:
987
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9 } else { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
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parents:
987
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10 add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
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11 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
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12 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
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13 |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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14 void check_cycles_int(cpu_options *opts, uint32_t address) |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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parents:
diff
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15 { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
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16 code_info *code = &opts->code; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
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17 uint8_t cc; |
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parents:
987
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18 if (opts->limit < 0) { |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
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19 cmp_ir(code, 1, opts->cycles, SZ_D); |
4bc27caa6e20
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20 cc = CC_NS; |
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parents:
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21 } else { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
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22 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
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23 cc = CC_A; |
1047
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Michael Pavone <pavone@retrodev.com>
parents:
987
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24 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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25 code_ptr jmp_off = code->cur+1; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
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26 jcc(code, cc, jmp_off+1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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parents:
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27 mov_ir(code, address, opts->scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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28 call(code, opts->handle_cycle_limit_int); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
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29 *jmp_off = code->cur - (jmp_off+1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
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30 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
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31 |
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32 void retranslate_calc(cpu_options *opts) |
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33 { |
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parents:
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34 code_info *code = &opts->code; |
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35 code_info tmp = *code; |
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parents:
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36 uint8_t cc; |
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parents:
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37 if (opts->limit < 0) { |
5d41d0574863
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parents:
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38 cmp_ir(code, 1, opts->cycles, SZ_D); |
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parents:
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39 cc = CC_NS; |
5d41d0574863
Preserve original address when retranslating instructions instead of switching to the lowest alias
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parents:
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40 } else { |
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Preserve original address when retranslating instructions instead of switching to the lowest alias
Michael Pavone <pavone@retrodev.com>
parents:
1145
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41 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
5d41d0574863
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parents:
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42 cc = CC_A; |
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parents:
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43 } |
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Preserve original address when retranslating instructions instead of switching to the lowest alias
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parents:
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44 jcc(code, cc, code->cur+2); |
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45 opts->move_pc_off = code->cur - tmp.cur; |
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46 mov_ir(code, 0x1234, opts->scratch1, SZ_D); |
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47 opts->move_pc_size = code->cur - tmp.cur - opts->move_pc_off; |
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parents:
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48 *code = tmp; |
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49 } |
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50 |
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51 void patch_for_retranslate(cpu_options *opts, code_ptr native_address, code_ptr handler) |
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52 { |
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parents:
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53 if (!is_mov_ir(native_address)) { |
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54 //instruction is not already patched for either retranslation or a breakpoint |
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55 //copy original mov_ir instruction containing PC to beginning of native code area |
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56 memmove(native_address, native_address + opts->move_pc_off, opts->move_pc_size); |
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57 } |
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58 //jump to the retranslation handler |
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59 code_info tmp = { |
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60 .cur = native_address + opts->move_pc_size, |
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61 .last = native_address + 256, |
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62 .stack_off = 0 |
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63 }; |
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64 jmp(&tmp, handler); |
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65 } |
5d41d0574863
Preserve original address when retranslating instructions instead of switching to the lowest alias
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parents:
1145
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66 |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
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67 void check_cycles(cpu_options * opts) |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
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68 { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
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69 code_info *code = &opts->code; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
70 uint8_t cc; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
71 if (opts->limit < 0) { |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
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72 cmp_ir(code, 1, opts->cycles, SZ_D); |
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
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73 cc = CC_NS; |
1047
6b07af1515b5
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parents:
987
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74 } else { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
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75 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
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76 cc = CC_A; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
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parents:
987
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77 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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78 check_alloc_code(code, MAX_INST_LEN*2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
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79 code_ptr jmp_off = code->cur+1; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
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80 jcc(code, cc, jmp_off+1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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81 call(code, opts->handle_cycle_limit); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
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82 *jmp_off = code->cur - (jmp_off+1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
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83 } |
589
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Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
84 |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
85 void log_address(cpu_options *opts, uint32_t address, char * format) |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
86 { |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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diff
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|
87 code_info *code = &opts->code; |
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Sync fixes and logging to fix more sync issues
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diff
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|
88 call(code, opts->save_context); |
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Sync fixes and logging to fix more sync issues
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diff
changeset
|
89 push_r(code, opts->context_reg); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
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diff
changeset
|
90 mov_rr(code, opts->cycles, RDX, SZ_D); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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diff
changeset
|
91 mov_ir(code, (int64_t)format, RDI, SZ_PTR); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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692
diff
changeset
|
92 mov_ir(code, address, RSI, SZ_D); |
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Sync fixes and logging to fix more sync issues
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diff
changeset
|
93 call_args_abi(code, (code_ptr)printf, 3, RDI, RSI, RDX); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
692
diff
changeset
|
94 pop_r(code, opts->context_reg); |
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Sync fixes and logging to fix more sync issues
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diff
changeset
|
95 call(code, opts->load_context); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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692
diff
changeset
|
96 } |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
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parents:
692
diff
changeset
|
97 |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
98 void check_code_prologue(code_info *code) |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
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parents:
595
diff
changeset
|
99 { |
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Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
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parents:
595
diff
changeset
|
100 check_alloc_code(code, MAX_INST_LEN*4); |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
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parents:
595
diff
changeset
|
101 } |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
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parents:
595
diff
changeset
|
102 |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
103 code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk const * memmap, uint32_t num_chunks, ftype fun_type, code_ptr *after_inc) |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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|
104 { |
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|
105 code_info *code = &opts->code; |
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Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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|
106 code_ptr start = code->cur; |
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Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
107 check_cycles(opts); |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
108 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
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|
109 uint8_t adr_reg = is_write ? opts->scratch2 : opts->scratch1; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
110 uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
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parents:
894
diff
changeset
|
111 if (size != SZ_B && opts->align_error_mask) { |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
112 test_ir(code, opts->align_error_mask, adr_reg, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
113 jcc(code, CC_NZ, is_write ? opts->handle_align_error_write : opts->handle_align_error_read); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
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parents:
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diff
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|
114 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
115 cycles(opts, opts->bus_cycles); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
116 if (after_inc) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
117 *after_inc = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
|
118 } |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
119 |
750
59b499f6b24f
Fix handling of address mask in gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
120 if (opts->address_size == SZ_D && opts->address_mask != 0xFFFFFFFF) { |
59b499f6b24f
Fix handling of address mask in gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
121 and_ir(code, opts->address_mask, adr_reg, SZ_D); |
1116
fe8c79f82c22
More cleanup in preparation for SMS/Mark III support
Michael Pavone <pavone@retrodev.com>
parents:
1109
diff
changeset
|
122 } else if (opts->address_size == SZ_W && opts->address_mask != 0xFFFF) { |
fe8c79f82c22
More cleanup in preparation for SMS/Mark III support
Michael Pavone <pavone@retrodev.com>
parents:
1109
diff
changeset
|
123 and_ir(code, opts->address_mask, adr_reg, SZ_W); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
124 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
125 code_ptr lb_jcc = NULL, ub_jcc = NULL; |
2dde38c1744f
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parents:
567
diff
changeset
|
126 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
127 uint32_t ram_flags_off = opts->ram_flags_off; |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
128 uint32_t min_address = 0; |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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parents:
1084
diff
changeset
|
129 uint32_t max_address = opts->max_address; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
130 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
2dde38c1744f
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567
diff
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|
131 { |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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parents:
1084
diff
changeset
|
132 if (memmap[chunk].start > min_address) { |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
133 cmp_ir(code, memmap[chunk].start, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
134 lb_jcc = code->cur + 1; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
135 jcc(code, CC_C, code->cur + 2); |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
136 } else { |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
137 min_address = memmap[chunk].end; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
138 } |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
139 if (memmap[chunk].end < max_address) { |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
140 cmp_ir(code, memmap[chunk].end, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
141 ub_jcc = code->cur + 1; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
142 jcc(code, CC_NC, code->cur + 2); |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
143 } else { |
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
144 max_address = memmap[chunk].start; |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
145 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
146 |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
147 if (memmap[chunk].mask != opts->address_mask) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
148 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
149 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
150 void * cfun; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
151 switch (fun_type) |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
152 { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
153 case READ_16: |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
154 cfun = memmap[chunk].read_16; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
155 break; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
156 case READ_8: |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
157 cfun = memmap[chunk].read_8; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
158 break; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
159 case WRITE_16: |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
160 cfun = memmap[chunk].write_16; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
161 break; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
162 case WRITE_8: |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
163 cfun = memmap[chunk].write_8; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
164 break; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
165 default: |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
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diff
changeset
|
166 cfun = NULL; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
167 } |
604
39d7d463ed5b
Get Z80 banked access sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
601
diff
changeset
|
168 if(memmap[chunk].flags & access_flag) { |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
169 if (memmap[chunk].flags & MMAP_PTR_IDX) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
170 if (memmap[chunk].flags & MMAP_FUNC_NULL) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
171 cmp_irdisp(code, 0, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, SZ_PTR); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
changeset
|
172 code_ptr not_null = code->cur + 1; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
173 jcc(code, CC_NZ, code->cur + 2); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
174 call(code, opts->save_context); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
175 if (is_write) { |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
176 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1); |
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
177 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
589
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178 } else { |
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179 push_r(code, opts->context_reg); |
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180 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg); |
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181 pop_r(code, opts->context_reg); |
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182 mov_rr(code, RAX, opts->scratch1, size); |
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183 } |
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184 jmp(code, opts->load_context); |
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185 |
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186 *not_null = code->cur - (not_null + 1); |
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187 } |
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188 if ((opts->byte_swap || memmap[chunk].flags & MMAP_BYTESWAP) && size == SZ_B) { |
589
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189 xor_ir(code, 1, adr_reg, opts->address_size); |
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190 } |
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191 if (opts->address_size != SZ_D) { |
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192 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); |
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193 } |
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194 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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195 push_r(code, adr_reg); |
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196 } |
589
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197 add_rdispr(code, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_PTR); |
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198 if (is_write) { |
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199 mov_rrind(code, opts->scratch1, opts->scratch2, size); |
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200 if (memmap[chunk].flags & MMAP_CODE) { |
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201 pop_r(code, adr_reg); |
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202 } |
589
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203 } else { |
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204 mov_rindr(code, opts->scratch1, opts->scratch1, size); |
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205 } |
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206 } else { |
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207 uint8_t tmp_size = size; |
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208 if (size == SZ_B) { |
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209 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
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210 bt_ir(code, 0, adr_reg, opts->address_size); |
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211 code_ptr good_addr = code->cur + 1; |
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212 jcc(code, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, code->cur + 2); |
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213 if (!is_write) { |
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214 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
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215 } |
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216 retn(code); |
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217 *good_addr = code->cur - (good_addr + 1); |
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218 shr_ir(code, 1, adr_reg, opts->address_size); |
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219 } else if (opts->byte_swap || memmap[chunk].flags & MMAP_BYTESWAP) { |
589
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220 xor_ir(code, 1, adr_reg, opts->address_size); |
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221 } |
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222 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
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223 tmp_size = SZ_B; |
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224 shr_ir(code, 1, adr_reg, opts->address_size); |
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225 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
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226 shr_ir(code, 8, opts->scratch1, SZ_W); |
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227 } |
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228 } |
595
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229 if (opts->address_size != SZ_D) { |
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230 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); |
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231 } |
589
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232 if ((intptr_t)memmap[chunk].buffer <= 0x7FFFFFFF && (intptr_t)memmap[chunk].buffer >= -2147483648) { |
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233 if (is_write) { |
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234 mov_rrdisp(code, opts->scratch1, opts->scratch2, (intptr_t)memmap[chunk].buffer, tmp_size); |
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235 } else { |
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236 mov_rdispr(code, opts->scratch1, (intptr_t)memmap[chunk].buffer, opts->scratch1, tmp_size); |
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237 } |
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238 } else { |
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239 if (is_write) { |
760
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240 push_r(code, opts->scratch2); |
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241 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); |
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242 add_rdispr(code, RSP, 0, opts->scratch2, SZ_PTR); |
589
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243 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size); |
760
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244 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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245 pop_r(code, opts->scratch2); |
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246 } else { |
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247 add_ir(code, sizeof(void*), RSP, SZ_D); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
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248 code->stack_off -= sizeof(void *); |
760
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249 } |
589
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250 } else { |
756
e1dc98f7ed9f
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251 push_r(code, opts->scratch2); |
589
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252 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); |
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253 mov_rindexr(code, opts->scratch2, opts->scratch1, 1, opts->scratch1, tmp_size); |
756
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254 pop_r(code, opts->scratch2); |
589
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255 } |
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256 } |
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257 if (size != tmp_size && !is_write) { |
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258 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
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259 shl_ir(code, 8, opts->scratch1, SZ_W); |
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260 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
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261 } else { |
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262 or_ir(code, 0xFF00, opts->scratch1, SZ_W); |
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263 } |
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264 } |
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265 } |
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266 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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267 mov_rr(code, opts->scratch2, opts->scratch1, opts->address_size); |
620
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268 shr_ir(code, opts->ram_flags_shift, opts->scratch1, opts->address_size); |
690
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269 bt_rrdisp(code, opts->scratch1, opts->context_reg, ram_flags_off, opts->address_size); |
589
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270 code_ptr not_code = code->cur + 1; |
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271 jcc(code, CC_NC, code->cur + 2); |
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272 if (memmap[chunk].mask != opts->address_mask) { |
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273 or_ir(code, memmap[chunk].start, opts->scratch2, opts->address_size); |
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274 } |
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275 call(code, opts->save_context); |
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276 call_args(code, opts->handle_code_write, 2, opts->scratch2, opts->context_reg); |
589
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277 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
1086
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278 jmp(code, opts->load_context); |
589
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279 *not_code = code->cur - (not_code+1); |
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280 } |
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281 retn(code); |
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282 } else if (cfun) { |
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283 call(code, opts->save_context); |
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284 if (is_write) { |
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285 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1); |
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286 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
589
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287 } else { |
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288 push_r(code, opts->context_reg); |
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289 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg); |
589
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290 pop_r(code, opts->context_reg); |
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291 mov_rr(code, RAX, opts->scratch1, size); |
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292 } |
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293 jmp(code, opts->load_context); |
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294 } else { |
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295 //Not sure the best course of action here |
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296 if (!is_write) { |
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297 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size); |
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298 } |
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299 retn(code); |
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300 } |
1145
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301 if (memmap[chunk].flags & MMAP_CODE) { |
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302 if (memmap[chunk].mask == opts->address_mask) { |
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303 ram_flags_off += (memmap[chunk].end - memmap[chunk].start) / (1 << opts->ram_flags_shift) / 8; ; |
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304 } else { |
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305 ram_flags_off += (memmap[chunk].mask + 1) / (1 << opts->ram_flags_shift) / 8;; |
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306 } |
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307 } |
589
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308 if (lb_jcc) { |
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309 *lb_jcc = code->cur - (lb_jcc+1); |
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310 lb_jcc = NULL; |
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311 } |
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312 if (ub_jcc) { |
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313 *ub_jcc = code->cur - (ub_jcc+1); |
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314 ub_jcc = NULL; |
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315 } |
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316 } |
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317 if (!is_write) { |
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318 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size); |
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319 } |
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320 retn(code); |
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321 return start; |
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322 } |