repos/blastem: 68kinst.c annotate

annotate 68kinst.c @ 995:2bc27415565b

Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.

author	Michael Pavone <pavone@retrodev.com>
date	Sat, 30 Apr 2016 08:37:55 -0700
parents	261995d06897
children	054472ea077a

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 412 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 412 diff changeset	2 Copyright 2013 Michael Pavone
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 412 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 412 diff changeset	5 */
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "68kinst.h"
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	7 #include <string.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	8 #include <stdio.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	9
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	10 uint32_t sign_extend16(uint32_t val)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	11 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	12 return (val & 0x8000) ? val \| 0xFFFF0000 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	13 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	14
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	15 uint32_t sign_extend8(uint32_t val)
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	17 return (val & 0x80) ? val \| 0xFFFFFF00 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	18 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	19
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	20 uint16_t m68k_decode_op_ex(uint16_t cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	21 {
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	22 uint16_t ext, tmp;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 dst->addr_mode = mode;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 switch(mode)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 case MODE_REG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 case MODE_AREG:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	28 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	29 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	30 case MODE_AREG_PREDEC:
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 dst->params.regs.pri = reg;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	33 case MODE_AREG_DISPLACE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	34 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	35 dst->params.regs.pri = reg;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	36 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	37 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	38 case MODE_AREG_INDEX_MEM:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	39 dst->params.regs.pri = reg;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	40 ext = *(++cur);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	41 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	42 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	43 dst->params.regs.scale = ext >> 9 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	44 if (ext & 0x100)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	45 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	46 dst->params.regs.disp_sizes = ext >> 4 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	47 switch (dst->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	48 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	49 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	50 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	51 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	52 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	53 dst->params.regs.displacement = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	54 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	55 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	56 dst->params.regs.displacement = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	57 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	58 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	59 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	60 dst->params.regs.displacement = tmp << 16 \| *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	61 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	62 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	63 if (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	64 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	65 //memory indirect
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	66 switch (ext & 0xC4)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	67 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	68 case 0x00:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	69 dst->addr_mode = MODE_AREG_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	70 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	71 case 0x04:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	72 dst->addr_mode = MODE_AREG_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	73 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	74 case 0x40:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	75 dst->addr_mode = MODE_AREG_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	76 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	77 case 0x80:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	78 dst->addr_mode = MODE_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	79 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	80 case 0x84:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	81 dst->addr_mode = MODE_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	82 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	83 case 0xC0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	84 dst->addr_mode = MODE_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	85 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	86 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	87 dst->params.regs.disp_sizes \|= ext << 4 & 0x30;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	88 switch (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	89 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	90 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	91 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	92 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	93 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	94 dst->params.regs.outer_disp = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	95 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	96 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	97 dst->params.regs.outer_disp = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	98 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	99 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	100 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	101 dst->params.regs.outer_disp = tmp << 16 \| *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	102 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	103 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	104 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	105 switch (ext >> 6 & 3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	106 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	107 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	108 dst->addr_mode = MODE_AREG_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	109 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	110 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	111 dst->addr_mode = MODE_AREG_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	112 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	113 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	114 dst->addr_mode = MODE_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	115 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	116 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	117 dst->addr_mode = MODE_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	118 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	119 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	120 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	121 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	122 #endif
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	123 dst->addr_mode = MODE_AREG_INDEX_DISP8;
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	124 dst->params.regs.displacement = sign_extend8(ext&0xFF);
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	125 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	126 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	127 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	128 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	129 case MODE_PC_INDIRECT_ABS_IMMED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	130 switch(reg)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	131 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	132 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	133 dst->addr_mode = MODE_ABSOLUTE_SHORT;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	134 ext = *(++cur);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	135 dst->params.immed = sign_extend16(ext);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	136 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	137 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	138 dst->addr_mode = MODE_ABSOLUTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	139 ext = *(++cur);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	140 dst->params.immed = ext << 16 \| *(++cur);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	141 break;
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	142 case 3:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	143 ext = *(++cur);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	144 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	145 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	146 dst->params.regs.scale = ext >> 9 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	147 if (ext & 0x100)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	148 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	149 dst->params.regs.disp_sizes = ext >> 4 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	150 switch (dst->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	151 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	152 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	153 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	154 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	155 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	156 dst->params.regs.displacement = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	157 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	158 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	159 dst->params.regs.displacement = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	160 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	161 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	162 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	163 dst->params.regs.displacement = tmp << 16 \| *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	164 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	165 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	166 if (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	167 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	168 //memory indirect
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	169 switch (ext & 0xC4)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	170 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	171 case 0x00:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	172 dst->addr_mode = MODE_PC_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	173 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	174 case 0x04:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	175 dst->addr_mode = MODE_PC_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	176 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	177 case 0x40:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	178 dst->addr_mode = MODE_PC_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	179 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	180 case 0x80:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	181 dst->addr_mode = MODE_ZPC_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	182 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	183 case 0x84:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	184 dst->addr_mode = MODE_ZPC_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	185 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	186 case 0xC0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	187 dst->addr_mode = MODE_ZPC_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	188 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	189 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	190 dst->params.regs.disp_sizes \|= ext << 4 & 0x30;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	191 switch (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	192 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	193 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	194 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	195 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	196 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	197 dst->params.regs.outer_disp = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	198 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	199 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	200 dst->params.regs.outer_disp = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	201 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	202 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	203 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	204 dst->params.regs.outer_disp = tmp << 16 \| *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	205 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	206 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	207 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	208 switch (ext >> 6 & 3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	209 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	210 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	211 dst->addr_mode = MODE_PC_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	212 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	213 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	214 dst->addr_mode = MODE_PC_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	215 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	216 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	217 dst->addr_mode = MODE_ZPC_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	218 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	219 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	220 dst->addr_mode = MODE_ZPC_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	221 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	222 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	223 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	224 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	225 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	226 dst->addr_mode = MODE_PC_INDEX_DISP8;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	227 dst->params.regs.displacement = sign_extend8(ext&0xFF);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	228 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	229 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	230 #endif
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 94 diff changeset	231 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	232 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	233 dst->addr_mode = MODE_PC_DISPLACE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	234 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	235 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	236 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	237 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	238 dst->addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	239 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	240 switch (size)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	241 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	242 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	243 dst->params.immed = ext & 0xFF;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	244 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	245 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	246 dst->params.immed = ext;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	247 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	248 case OPSIZE_LONG:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	249 dst->params.immed = ext << 16 \| *(++cur);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	250 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	251 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	252 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	253 default:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	254 return NULL;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	255 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	256 break;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	258 return cur;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	259 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	260
823 b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	261 uint8_t m68k_valid_immed_dst(m68k_op_info *dst)
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	262 {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	263 if (dst->addr_mode == MODE_AREG \|\| dst->addr_mode == MODE_IMMEDIATE) {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	264 return 0;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	265 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	266 return 1;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	267 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	268
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	269 uint8_t m68k_valid_immed_limited_dst(m68k_op_info *dst)
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	270 {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	271 if (dst->addr_mode == MODE_AREG \|\| dst->addr_mode > MODE_ABSOLUTE) {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	272 return 0;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	273 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	274 return 1;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	275 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	276
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	277 uint16_t m68k_decode_op(uint16_t cur, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	278 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	279 uint8_t mode = (*cur >> 3) & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	280 uint8_t reg = *cur & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	281 return m68k_decode_op_ex(cur, mode, reg, size, dst);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	282 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	283
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	284 void m68k_decode_cond(uint16_t op, m68kinst * decoded)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	285 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	286 decoded->extra.cond = (op >> 0x8) & 0xF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	287 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	288
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	289 uint8_t m68k_reg_quick_field(uint16_t op)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	290 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	291 return (op >> 9) & 0x7;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	293
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	294 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address)
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	296 uint16_t *start = istream;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 uint8_t optype = *istream >> 12;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 uint8_t size;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	299 uint8_t reg;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	300 uint8_t opmode;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	301 uint32_t immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	302 decoded->op = M68K_INVALID;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	303 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	304 decoded->variant = VAR_NORMAL;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	305 decoded->address = address;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	306 switch(optype)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	307 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 case BIT_MOVEP_IMMED:
163 5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	309 if ((*istream & 0x138) == 0x108) {
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	310 //MOVEP
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	311 decoded->op = M68K_MOVEP;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	312 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	313 if (*istream & 0x80) {
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	314 //memory dest
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	315 decoded->src.addr_mode = MODE_REG;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	316 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	317 decoded->dst.addr_mode = MODE_AREG_DISPLACE;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	318 decoded->dst.params.regs.pri = *istream & 0x7;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	319 decoded->dst.params.regs.displacement = *(++istream);
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	320 } else {
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	321 //memory source
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	322 decoded->dst.addr_mode = MODE_REG;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	323 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	324 decoded->src.addr_mode = MODE_AREG_DISPLACE;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	325 decoded->src.params.regs.pri = *istream & 0x7;
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	326 decoded->src.params.regs.displacement = *(++istream);
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	327 }
5559616e6bd8 Fix decoding of movep Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	328 } else if (*istream & 0x100) {
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	329 //BTST, BCHG, BCLR, BSET
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	330 switch ((*istream >> 6) & 0x3)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	331 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	332 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	333 decoded->op = M68K_BTST;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	334 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	335 case 1:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	336 decoded->op = M68K_BCHG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	337 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	338 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	339 decoded->op = M68K_BCLR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	340 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	341 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	342 decoded->op = M68K_BSET;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	343 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	344 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	345 decoded->src.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	346 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	347 decoded->extra.size = OPSIZE_BYTE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	348 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	349 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	350 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	351 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	352 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	353 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	354 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	355 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	356 } else if ((*istream & 0xF00) == 0x800) {
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	357 //BTST, BCHG, BCLR, BSET
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	358 switch ((*istream >> 6) & 0x3)
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	359 {
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	360 case 0:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	361 decoded->op = M68K_BTST;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	362 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	363 case 1:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	364 decoded->op = M68K_BCHG;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	365 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	366 case 2:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	367 decoded->op = M68K_BCLR;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	368 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	369 case 3:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	370 decoded->op = M68K_BSET;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	371 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	372 }
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	373 opmode = (*istream >> 3) & 0x7;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	374 reg = *istream & 0x7;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	375 decoded->src.addr_mode = MODE_IMMEDIATE_WORD;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	376 decoded->src.params.immed = *(++istream) & 0xFF;
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	377 decoded->extra.size = OPSIZE_BYTE;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	378 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	379 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	380 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	381 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	382 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	383 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	384 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	385 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	386 } else if ((*istream & 0xC0) == 0xC0) {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	387 #ifdef M68020
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	388 //CMP2, CHK2, CAS, CAS2, RTM, CALLM
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	389 #endif
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	390 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	391 switch ((*istream >> 9) & 0x7)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	392 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	393 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	394 if ((*istream & 0xFF) == 0x3C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	395 decoded->op = M68K_ORI_CCR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	396 decoded->extra.size = OPSIZE_BYTE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	397 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	398 decoded->src.params.immed = *(++istream) & 0xFF;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	399 } else if((*istream & 0xFF) == 0x7C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	400 decoded->op = M68K_ORI_SR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	401 decoded->extra.size = OPSIZE_WORD;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	402 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	403 decoded->src.params.immed = *(++istream);
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	404 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	405 decoded->op = M68K_OR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	406 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	407 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	408 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	409 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	410 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	411 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	412 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	413 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	414 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	415 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	416 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	417 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	418 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	419 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	420 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	421 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	422 break;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	423 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	424 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823 b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	425 if (!istream \|\| !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	426 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	427 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	428 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	429 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	430 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	431 case 1:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	432 //ANDI, ANDI to CCR, ANDI to SR
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	433 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	434 decoded->op = M68K_ANDI_CCR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	435 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	436 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	437 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	438 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	439 decoded->op = M68K_ANDI_SR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	440 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	441 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	442 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	443 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	444 decoded->op = M68K_AND;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	445 decoded->variant = VAR_IMMEDIATE;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	446 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	447 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	448 reg = *istream & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	449 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	450 switch (size)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	451 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	452 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	453 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	454 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	455 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	456 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	457 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	458 case OPSIZE_LONG:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	459 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	460 decoded->src.params.immed = immed << 16 \| *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	461 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	462 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	463 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823 b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	464 if (!istream \|\| !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	465 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	466 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	467 }
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	468 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	469 break;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	470 case 2:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	471 decoded->op = M68K_SUB;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	472 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	473 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	474 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	475 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	476 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	477 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	478 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	479 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	480 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	481 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	482 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	483 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	484 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	485 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	486 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	487 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	488 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	489 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	490 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823 b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	491 if (!istream \|\| !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	492 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	493 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	494 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	495 break;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	496 case 3:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	497 decoded->op = M68K_ADD;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	498 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	499 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	500 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	501 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	502 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	503 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	504 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	505 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	506 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	507 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	508 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	509 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	510 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	511 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	512 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	513 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	514 break;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	515 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	516 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823 b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	517 if (!istream \|\| !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	518 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	519 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	520 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	521 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	522 case 4:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	523 //BTST, BCHG, BCLR, BSET
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	524 switch ((*istream >> 6) & 0x3)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	525 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	526 case 0:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	527 decoded->op = M68K_BTST;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	528 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	529 case 1:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	530 decoded->op = M68K_BCHG;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	531 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	532 case 2:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	533 decoded->op = M68K_BCLR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	534 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	535 case 3:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	536 decoded->op = M68K_BSET;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	537 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	538 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	539 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	540 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	541 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	542 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	543 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	544 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	545 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	546 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	547 case 5:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	548 //EORI, EORI to CCR, EORI to SR
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	549 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	550 decoded->op = M68K_EORI_CCR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	551 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	552 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	553 decoded->src.params.immed = *(++istream) & 0xFF;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	554 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	555 decoded->op = M68K_EORI_SR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	556 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	557 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	558 decoded->src.params.immed = *(++istream);
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	559 } else {
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	560 decoded->op = M68K_EOR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	561 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	562 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	563 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	564 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	565 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	566 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	567 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	568 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	569 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	570 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	571 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	572 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	573 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	574 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	575 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	576 decoded->src.params.immed = immed << 16 \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	577 break;
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	578 }
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	579 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823 b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	580 if (!istream \|\| !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	581 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	582 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	583 }
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	584 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	585 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	586 case 6:
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	587 decoded->op = M68K_CMP;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	588 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	589 decoded->extra.size = (*istream >> 6) & 0x3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	590 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	591 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	592 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	593 switch (decoded->extra.size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	594 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	595 case OPSIZE_BYTE:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	596 decoded->src.params.immed = *(++istream) & 0xFF;
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	597 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	598 case OPSIZE_WORD:
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	599 decoded->src.params.immed = *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	600 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	601 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	602 immed = *(++istream);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	603 decoded->src.params.immed = (immed << 16) \| *(++istream);
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	604 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 5 diff changeset	605 }
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	606 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
823 b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	607 if (!istream \|\| !m68k_valid_immed_dst(&(decoded->dst))) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	608 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	609 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	610 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	611 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	612 case 7:
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	613 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	614 decoded->op = M68K_MOVES;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	615 decoded->extra.size = *istream >> 6 & 0x3;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	616 immed = *(++istream);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	617 reg = immed >> 12 & 0x7;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	618 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	619 if (immed & 0x800) {
642 08d0e3e7d0d8 Fix interpretation of moves direction field Michael Pavone <pavone@retrodev.com> parents: 641 diff changeset	620 decoded->src.addr_mode = opmode;
08d0e3e7d0d8 Fix interpretation of moves direction field Michael Pavone <pavone@retrodev.com> parents: 641 diff changeset	621 decoded->src.params.regs.pri = reg;
08d0e3e7d0d8 Fix interpretation of moves direction field Michael Pavone <pavone@retrodev.com> parents: 641 diff changeset	622 m68k_decode_op_ex(istream, start >> 3 & 0x7, start & 0x7, decoded->extra.size, &(decoded->dst));
08d0e3e7d0d8 Fix interpretation of moves direction field Michael Pavone <pavone@retrodev.com> parents: 641 diff changeset	623 } else {
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	624 m68k_decode_op_ex(istream, start >> 3 & 0x7, start & 0x7, decoded->extra.size, &(decoded->src));
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	625 decoded->dst.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	626 decoded->dst.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	627 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	628 #endif
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	629 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	630 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	631 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	632 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	633 case MOVE_BYTE:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	634 case MOVE_LONG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	635 case MOVE_WORD:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	636 decoded->op = M68K_MOVE;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	637 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	638 opmode = (*istream >> 6) & 0x7;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	639 reg = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	640 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	641 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	642 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	643 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	644 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	645 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
197 7c227a8ec53d Add instruction address logging to translator and support for reading an address log to the disassembler Mike Pavone <pavone@retrodev.com> parents: 184 diff changeset	646 if (!istream \|\| decoded->dst.addr_mode == MODE_IMMEDIATE) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	647 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	648 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	649 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	650 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	651 case MISC:
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	652
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	653 if ((*istream & 0x1C0) == 0x1C0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	654 decoded->op = M68K_LEA;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	655 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	656 decoded->dst.addr_mode = MODE_AREG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	657 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	658 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	659 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	660 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	661 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	662 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	663 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	664 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	665 decoded->op = M68K_CHK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	666 if ((*istream & 0x180) == 0x180) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	667 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	668 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	669 //only on M68020+
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	670 #ifdef M68020
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	671 decoded->extra.size = OPSIZE_LONG;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	672 #else
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	673 decoded->op = M68K_INVALID;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	674 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	675 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	676 }
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	677 decoded->dst.addr_mode = MODE_REG;
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	678 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	679 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	680 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	681 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	682 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	683 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	684 } else {
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	685 opmode = (*istream >> 3) & 0x7;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	686 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	687 //TODO: Check for invalid modes that are dependent on direction
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	688 decoded->op = M68K_MOVEM;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	689 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	690 reg = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	691 if(*istream & 0x400) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	692 decoded->dst.addr_mode = MODE_REG;
68 1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	693 decoded->dst.params.immed = *(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	694 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	695 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	696 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	697 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	698 }
412 00d5a2b532f4 Fix movem with pc displacement or pc indexed source Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	699 if (decoded->src.addr_mode == MODE_PC_DISPLACE \|\| decoded->src.addr_mode == MODE_PC_INDEX_DISP8) {
00d5a2b532f4 Fix movem with pc displacement or pc indexed source Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	700 //adjust displacement to account for extra instruction word
00d5a2b532f4 Fix movem with pc displacement or pc indexed source Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	701 decoded->src.params.regs.displacement += 2;
00d5a2b532f4 Fix movem with pc displacement or pc indexed source Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	702 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	703 } else {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	704 decoded->src.addr_mode = MODE_REG;
68 1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	705 decoded->src.params.immed = *(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	706 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	707 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	708 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	709 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	710 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	711 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	712 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	713 optype = (*istream >> 9) & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	714 size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	715 switch(optype)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	716 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	717 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	718 //Move from SR or NEGX
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	719 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	720 decoded->op = M68K_MOVE_FROM_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	721 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	722 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	723 decoded->op = M68K_NEGX;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	724 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	725 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	726 istream= m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	727 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	728 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	729 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	730 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	731 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	732 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	733 //MOVE from CCR or CLR
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	734 if (size == OPSIZE_INVALID) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	735 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	736 decoded->op = M68K_MOVE_FROM_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	737 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	738 #else
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	739 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	740 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	741 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	742 decoded->op = M68K_CLR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	743 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	744 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	745 istream= m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	746 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	747 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	748 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	749 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	750 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	751 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	752 //MOVE to CCR or NEG
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	753 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	754 decoded->op = M68K_MOVE_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	755 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	756 istream= m68k_decode_op(istream, size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	757 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	758 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	759 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	760 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	761 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	762 decoded->op = M68K_NEG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	763 istream= m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	764 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	765 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	766 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	767 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	768 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	769 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	770 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	771 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	772 //MOVE to SR or NOT
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	773 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	774 decoded->op = M68K_MOVE_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	775 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	776 istream= m68k_decode_op(istream, size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	777 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	778 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	779 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	780 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	781 } else {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	782 decoded->op = M68K_NOT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	783 istream= m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	784 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	785 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	786 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	787 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	788 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	789 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	790 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	791 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	792 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	793 switch((*istream >> 3) & 0x3F)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	794 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	795 case 1:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	796 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	797 decoded->op = M68K_LINK;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	798 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	799 reg = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	800 immed = *(++istream) << 16;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	801 immed \|= *(++istream);
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	802 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	803 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	804 case 8:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	805 decoded->op = M68K_SWAP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	806 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	807 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	808 decoded->extra.size = OPSIZE_WORD;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	809 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	810 case 9:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	811 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	812 decoded->op = M68K_BKPT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	813 decoded->src.addr_mode = MODE_IMMEDIATE;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	814 decoded->extra.size = OPSIZE_UNSIZED;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	815 decoded->src.params.immed = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	816 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	817 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	818 case 0x10:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	819 decoded->op = M68K_EXT;
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	820 decoded->dst.addr_mode = MODE_REG;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	821 decoded->dst.params.regs.pri = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	822 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	823 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	824 case 0x18:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	825 decoded->op = M68K_EXT;
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	826 decoded->dst.addr_mode = MODE_REG;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	827 decoded->dst.params.regs.pri = *istream & 0x7;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	828 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	829 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	830 case 0x38:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	831 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	832 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	833 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	834 default:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	835 if (!(*istream & 0x1C0)) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	836 decoded->op = M68K_NBCD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	837 decoded->extra.size = OPSIZE_BYTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	838 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	839 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	840 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	841 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	842 }
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	843 } else if((*istream & 0x1C0) == 0x40) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	844 decoded->op = M68K_PEA;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	845 decoded->extra.size = OPSIZE_LONG;
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 111 diff changeset	846 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	847 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	848 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	849 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	850 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	851 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	852 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	853 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	854 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	855 //BGND, ILLEGAL, TAS, TST
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	856 optype = *istream & 0xFF;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	857 if (optype == 0xFA) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	858 //BGND - CPU32 only
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	859 } else if (optype == 0xFC) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	860 decoded->op = M68K_ILLEGAL;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	861 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	862 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	863 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	864 decoded->op = M68K_TAS;
835 b4cf6573a3f8 Decode operand for TAS Michael Pavone <pavone@retrodev.com> parents: 823 diff changeset	865 decoded->extra.size = OPSIZE_BYTE;
b4cf6573a3f8 Decode operand for TAS Michael Pavone <pavone@retrodev.com> parents: 823 diff changeset	866 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
b4cf6573a3f8 Decode operand for TAS Michael Pavone <pavone@retrodev.com> parents: 823 diff changeset	867 if (!istream) {
b4cf6573a3f8 Decode operand for TAS Michael Pavone <pavone@retrodev.com> parents: 823 diff changeset	868 decoded->op = M68K_INVALID;
b4cf6573a3f8 Decode operand for TAS Michael Pavone <pavone@retrodev.com> parents: 823 diff changeset	869 break;
b4cf6573a3f8 Decode operand for TAS Michael Pavone <pavone@retrodev.com> parents: 823 diff changeset	870 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	871 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	872 decoded->op = M68K_TST;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	873 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	874 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	875 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	876 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	877 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	878 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	879 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	880 }
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	881 break;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	882 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	883 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	884 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	885 //TODO: Implement these for 68020+ support
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	886 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	887 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	888 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	889 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	890 if (*istream & 0x80) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	891 //JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	892 if (*istream & 0x40) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	893 decoded->op = M68K_JMP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	894 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	895 decoded->op = M68K_JSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	896 }
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	897 decoded->extra.size = OPSIZE_UNSIZED;
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	898 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	899 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	900 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	901 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	902 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	903 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	904 //it would appear bit 6 needs to be set for it to be a valid instruction here
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	905 switch((*istream >> 3) & 0x7)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	906 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	907 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	908 case 1:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	909 //TRAP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	910 decoded->op = M68K_TRAP;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	911 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	912 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	913 decoded->src.params.immed = *istream & 0xF;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	914 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	915 case 2:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	916 //LINK.w
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	917 decoded->op = M68K_LINK;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	918 decoded->extra.size = OPSIZE_WORD;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	919 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	920 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	921 decoded->dst.addr_mode = MODE_IMMEDIATE;
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 91 diff changeset	922 decoded->dst.params.immed = sign_extend16(*(++istream));
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	923 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	924 case 3:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	925 //UNLK
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	926 decoded->op = M68K_UNLK;
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	927 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	928 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	929 decoded->dst.params.regs.pri = *istream & 0x7;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	930 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	931 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	932 case 5:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	933 //MOVE USP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	934 decoded->op = M68K_MOVE_USP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	935 if (*istream & 0x8) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	936 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	937 decoded->dst.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	938 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	939 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	940 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	941 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	942 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	943 case 6:
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	944 decoded->extra.size = OPSIZE_UNSIZED;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	945 switch(*istream & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	946 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	947 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	948 decoded->op = M68K_RESET;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	949 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	950 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	951 decoded->op = M68K_NOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	952 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	953 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	954 decoded->op = M68K_STOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	955 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	956 decoded->src.params.immed =*(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	957 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	958 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	959 decoded->op = M68K_RTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	960 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	961 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	962 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	963 decoded->op = M68K_RTD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	964 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	965 decoded->src.params.immed =*(++istream);
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	966 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	967 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	968 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	969 decoded->op = M68K_RTS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	970 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	971 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	972 decoded->op = M68K_TRAPV;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	973 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	974 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	975 decoded->op = M68K_RTR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	976 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	977 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	978 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	979 case 7:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	980 //MOVEC
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	981 #ifdef M68010
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	982 decoded->op = M68K_MOVEC;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	983 immed = *(++istream);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	984 reg = immed >> 12 & 0x7;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	985 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG;
641 66857bd2df0b Fix decoding of movec Michael Pavone <pavone@retrodev.com> parents: 638 diff changeset	986 immed &= 0xFFF;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	987 if (immed & 0x800) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	988 if (immed > MAX_HIGH_CR) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	989 decoded->op = M68K_INVALID;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	990 break;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	991 } else {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	992 immed = immed - 0x800 + CR_USP;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	993 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	994 } else {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	995 if (immed > MAX_LOW_CR) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	996 decoded->op = M68K_INVALID;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	997 break;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	998 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	999 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1000 if (*start & 1) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1001 decoded->src.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1002 decoded->src.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1003 decoded->dst.params.immed = immed;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1004 } else {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1005 decoded->dst.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1006 decoded->dst.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1007 decoded->src.params.immed = immed;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1008 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1009 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1010 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1011 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1012 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1013 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1014 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1015 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1016 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1017 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1018 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1019 case QUICK_ARITH_LOOP:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1020 size = (*istream >> 6) & 3;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1021 if (size == 0x3) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1022 //DBcc, TRAPcc or Scc
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1023 m68k_decode_cond(*istream, decoded);
111 8b50d2c975b2 Fix decoding of Scc Mike Pavone <pavone@retrodev.com> parents: 101 diff changeset	1024 if (((*istream >> 3) & 0x7) == 1) {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1025 decoded->op = M68K_DBCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1026 decoded->src.addr_mode = MODE_IMMEDIATE;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1027 decoded->dst.addr_mode = MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1028 decoded->dst.params.regs.pri = *istream & 0x7;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1029 decoded->src.params.immed = sign_extend16(*(++istream));
111 8b50d2c975b2 Fix decoding of Scc Mike Pavone <pavone@retrodev.com> parents: 101 diff changeset	1030 } else if(((istream >> 3) & 0x7) == 1 && (istream & 0x7) > 1 && (*istream & 0x7) < 5) {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1031 #ifdef M68020
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1032 decoded->op = M68K_TRAPCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1033 decoded->src.addr_mode = MODE_IMMEDIATE;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1034 //TODO: Figure out what to do with OPMODE and optional extention words
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1035 #endif
111 8b50d2c975b2 Fix decoding of Scc Mike Pavone <pavone@retrodev.com> parents: 101 diff changeset	1036 } else {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1037 decoded->op = M68K_SCC;
111 8b50d2c975b2 Fix decoding of Scc Mike Pavone <pavone@retrodev.com> parents: 101 diff changeset	1038 decoded->extra.cond = (*istream >> 8) & 0xF;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1039 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1040 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1041 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1042 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1043 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1044 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1045 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1046 //ADDQ, SUBQ
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1047 decoded->variant = VAR_QUICK;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1048 decoded->extra.size = size;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1049 decoded->src.addr_mode = MODE_IMMEDIATE;
91 8c446fc19cc0 Fix decoding bug in addq/subq Mike Pavone <pavone@retrodev.com> parents: 90 diff changeset	1050 immed = m68k_reg_quick_field(*istream);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1051 if (!immed) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1052 immed = 8;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1053 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1054 decoded->src.params.immed = immed;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1055 if (*istream & 0x100) {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1056 decoded->op = M68K_SUB;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1057 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1058 decoded->op = M68K_ADD;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1059 }
94 a668a35a3463 Fix decoding bug for addq/subq Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1060 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1061 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1062 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1063 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1064 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1065 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1066 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1067 case BRANCH:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1068 m68k_decode_cond(*istream, decoded);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1069 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1070 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1071 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1072 if (immed == 0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1073 decoded->variant = VAR_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1074 immed = *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1075 immed = sign_extend16(immed);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 140 diff changeset	1076 #ifdef M68020
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1077 } else if (immed == 0xFF) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1078 decoded->variant = VAR_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1079 immed = *(++istream) << 16;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1080 immed \|= *(++istream);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 140 diff changeset	1081 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1082 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1083 decoded->variant = VAR_BYTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1084 immed = sign_extend8(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1085 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1086 decoded->src.params.immed = immed;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1087 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1088 case MOVEQ:
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	1089 if (*istream & 0x100) {
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	1090 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1091 break;
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 197 diff changeset	1092 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1093 decoded->op = M68K_MOVE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1094 decoded->variant = VAR_QUICK;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1095 decoded->extra.size = OPSIZE_LONG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1096 decoded->src.addr_mode = MODE_IMMEDIATE;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	1097 decoded->src.params.immed = sign_extend8(*istream & 0xFF);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1098 decoded->dst.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1099 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1100 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1101 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1102 case OR_DIV_SBCD:
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1103 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea>
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1104 opmode = (*istream >> 6) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1105 size = opmode & 0x3;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1106 if (size == OPSIZE_INVALID \|\| (opmode & 0x4 && !(*istream & 0x30))) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1107 switch(opmode)
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1108 {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1109 case 3:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1110 decoded->op = M68K_DIVU;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1111 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1112 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1113 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1114 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
183 2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid Mike Pavone <pavone@retrodev.com> parents: 181 diff changeset	1115 if (!istream \|\| decoded->src.addr_mode == MODE_AREG) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1116 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1117 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1118 }
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1119 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1120 case 4:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1121 decoded->op = M68K_SBCD;
613 09d5adf8d1ca Fix opsize for sbcd in 68K instruction decoder. This fixes the timer bug in Strider 2 Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1122 decoded->extra.size = OPSIZE_BYTE;
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1123 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1124 decoded->src.params.regs.pri = *istream & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1125 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1126 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1127 case 5:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1128 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1129 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1130 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1131 case 6:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1132 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1133 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1134 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1135 case 7:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1136 decoded->op = M68K_DIVS;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1137 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1138 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1139 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1140 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
183 2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid Mike Pavone <pavone@retrodev.com> parents: 181 diff changeset	1141 if (!istream \|\| decoded->src.addr_mode == MODE_AREG) {
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1142 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1143 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1144 }
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1145 break;
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1146 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1147 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1148 decoded->op = M68K_OR;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1149 decoded->extra.size = size;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1150 if (opmode & 0x4) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1151 decoded->src.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1152 decoded->src.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1153 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1154 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1155 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1156 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1157 }
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1158 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1159 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1160 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1161 istream = m68k_decode_op(istream, size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1162 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1163 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1164 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1165 }
11 d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1166 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	1167 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1168 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1169 case SUB_SUBX:
101 d7789186ba5e Some fixes to add/addx sub/subx decoding Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	1170 size = (*istream >> 6) & 0x3;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1171 decoded->op = M68K_SUB;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1172 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1173 //<ea> destination, SUBA.l or SUBX
101 d7789186ba5e Some fixes to add/addx sub/subx decoding Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	1174 if (*istream & 0x30 \|\| size == OPSIZE_INVALID) {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1175 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1176 //SUBA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1177 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1178 decoded->dst.addr_mode = MODE_AREG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1179 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1180 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1181 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1182 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1183 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1184 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1185 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1186 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1187 decoded->src.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1188 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1189 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1190 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1191 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1192 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1193 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1194 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1195 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1196 //SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1197 decoded->op = M68K_SUBX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1198 decoded->extra.size = size;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1199 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1200 decoded->src.params.regs.pri = *istream & 0x7;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1201 if (*istream & 0x8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1202 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1203 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1204 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1205 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1206 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1207 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1208 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1209 //SUBA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1210 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1211 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1212 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1213 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1214 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1215 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1216 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1217 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1218 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1219 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1220 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1221 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1222 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1223 break;
992 261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	1224 case A_LINE:
261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	1225 decoded->op = M68K_A_LINE_TRAP;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1226 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1227 case CMP_XOR:
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1228 size = (*istream >> 6) & 0x3;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1229 decoded->op = M68K_CMP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1230 if (*istream & 0x100) {
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1231 //CMPM or CMPA.l or EOR
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1232 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1233 decoded->extra.size = OPSIZE_LONG;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1234 decoded->dst.addr_mode = MODE_AREG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1235 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
136 e64554246d11 Fix some bugs in decoding cmp Mike Pavone <pavone@retrodev.com> parents: 134 diff changeset	1236 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1237 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1238 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1239 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1240 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1241 } else {
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1242 reg = m68k_reg_quick_field(*istream);
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1243 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1244 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1245 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1246 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1247 }
181 3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	1248 decoded->extra.size = size;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	1249 if (decoded->dst.addr_mode == MODE_AREG) {
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1250 //CMPM
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1251 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1252 decoded->src.params.regs.pri = decoded->dst.params.regs.pri;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1253 decoded->dst.params.regs.pri = reg;
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1254 } else {
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1255 //EOR
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1256 decoded->op = M68K_EOR;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1257 decoded->src.addr_mode = MODE_REG;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1258 decoded->src.params.regs.pri = reg;
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1259 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1260 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1261 } else {
120 3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1262 //CMP or CMPA.w
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1263 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1264 decoded->extra.size = OPSIZE_WORD;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1265 decoded->dst.addr_mode = MODE_AREG;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1266 } else {
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1267 decoded->extra.size = size;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1268 decoded->dst.addr_mode = MODE_REG;
3648abc45aec Fix decoding of CMPA Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	1269 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1270 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
136 e64554246d11 Fix some bugs in decoding cmp Mike Pavone <pavone@retrodev.com> parents: 134 diff changeset	1271 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1272 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1273 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1274 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1275 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1276 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1277 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1278 case AND_MUL_ABCD_EXG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1279 //page 575 for summary
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1280 //EXG opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1281 //01000 -data regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1282 //01001 -addr regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1283 //10001 -one of each
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1284 //AND opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1285 //operand order bit + 2 size bits (00 - 10)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1286 //no address register direct addressing
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1287 //data register direct not allowed when <ea> is the source (operand order bit of 1)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1288 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1289 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1290 decoded->op = M68K_MULS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1291 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1292 decoded->dst.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1293 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1294 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1295 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1296 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1297 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1298 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1299 } else if(!(*istream & 0xF0)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1300 decoded->op = M68K_ABCD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1301 decoded->extra.size = OPSIZE_BYTE;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1302 decoded->src.params.regs.pri = *istream & 0x7;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1303 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1304 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1305 } else if(!(*istream & 0x30)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1306 decoded->op = M68K_EXG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1307 decoded->extra.size = OPSIZE_LONG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1308 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1309 decoded->dst.params.regs.pri = *istream & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1310 if (*istream & 0x8) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1311 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1312 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1313 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1314 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1315 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1316 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1317 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1318 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1319 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1320 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1321 decoded->op = M68K_AND;
90 645fe435cb48 Fix decoding of and Mike Pavone <pavone@retrodev.com> parents: 79 diff changeset	1322 decoded->extra.size = (*istream >> 6) & 0x3;
60 6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1323 decoded->src.addr_mode = MODE_REG;
6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1324 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1325 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1326 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1327 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1328 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1329 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1330 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1331 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1332 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1333 decoded->op = M68K_MULU;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1334 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	1335 decoded->dst.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1336 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1337 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1338 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1339 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1340 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1341 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1342 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1343 decoded->op = M68K_AND;
90 645fe435cb48 Fix decoding of and Mike Pavone <pavone@retrodev.com> parents: 79 diff changeset	1344 decoded->extra.size = (*istream >> 6) & 0x3;
60 6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1345 decoded->dst.addr_mode = MODE_REG;
6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1346 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
6ffea8607730 Fix operand order for AND instructions Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	1347 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1348 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1349 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1350 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1351 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1352 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1353 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1354 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1355 case ADD_ADDX:
101 d7789186ba5e Some fixes to add/addx sub/subx decoding Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	1356 size = (*istream >> 6) & 0x3;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1357 decoded->op = M68K_ADD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1358 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1359 //<ea> destination, ADDA.l or ADDX
101 d7789186ba5e Some fixes to add/addx sub/subx decoding Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	1360 if (*istream & 0x30 \|\| size == OPSIZE_INVALID) {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1361 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1362 //ADDA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1363 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1364 decoded->dst.addr_mode = MODE_AREG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1365 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1366 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1367 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1368 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1369 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1370 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1371 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1372 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1373 decoded->src.addr_mode = MODE_REG;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1374 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1375 istream = m68k_decode_op(istream, size, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1376 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1377 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1378 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1379 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1380 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1381 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1382 //ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1383 decoded->op = M68K_ADDX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1384 decoded->extra.size = size;
184 ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1385 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1386 decoded->src.params.regs.pri = *istream & 0x7;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1387 if (*istream & 0x8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1388 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1389 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger Mike Pavone <pavone@retrodev.com> parents: 183 diff changeset	1390 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1391 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1392 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1393 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1394 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1395 //ADDA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1396 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1397 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1398 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1399 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1400 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1401 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1402 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1403 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1404 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1405 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1406 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1407 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1408 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1409 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1410 case SHIFT_ROTATE:
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1411 if ((*istream & 0x8C0) == 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1412 switch((*istream >> 8) & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1413 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1414 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1415 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1416 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1417 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1418 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1419 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1420 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1421 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1422 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1423 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1424 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1425 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1426 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1427 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1428 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1429 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1430 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1431 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1432 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1433 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1434 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1435 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1436 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1437 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1438 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1439 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1440 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst));
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1441 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1442 decoded->op = M68K_INVALID;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1443 break;
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 163 diff changeset	1444 }
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1445 } else if((*istream & 0xC0) != 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1446 switch(((istream >> 2) & 0x6) \| ((istream >> 8) & 1))
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1447 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1448 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1449 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1450 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1451 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1452 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1453 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1454 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1455 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1456 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1457 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1458 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1459 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1460 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1461 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1462 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1463 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1464 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1465 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1466 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1467 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1468 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1469 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1470 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1471 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1472 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1473 decoded->extra.size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1474 immed = (*istream >> 9) & 0x7;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 50 diff changeset	1475 if (*istream & 0x20) {
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1476 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1477 decoded->src.params.regs.pri = immed;
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1478 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1479 decoded->src.addr_mode = MODE_IMMEDIATE;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1480 if (!immed) {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1481 immed = 8;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1482 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1483 decoded->src.params.immed = immed;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1484 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1485 decoded->dst.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1486 decoded->dst.params.regs.pri = *istream & 0x7;
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1487
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1488 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1489 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1490 //TODO: Implement bitfield instructions for M68020+ support
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1491 switch (*istream >> 8 & 7)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1492 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1493 case 0:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1494 decoded->op = M68K_BFTST; //<ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1495 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1496 case 1:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1497 decoded->op = M68K_BFEXTU; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1498 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1499 case 2:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1500 decoded->op = M68K_BFCHG; //<ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1501 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1502 case 3:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1503 decoded->op = M68K_BFEXTS; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1504 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1505 case 4:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1506 decoded->op = M68K_BFCLR; //<ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1507 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1508 case 5:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1509 decoded->op = M68K_BFFFO; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1510 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1511 case 6:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1512 decoded->op = M68K_BFSET; //<ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1513 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1514 case 7:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1515 decoded->op = M68K_BFINS; //Dn, <ea>
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1516 break;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1517 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1518 opmode = *istream >> 3 & 0x7;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1519 reg = *istream & 0x7;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1520 m68k_op_info ea, other;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1521 if (decoded->op == M68K_BFEXTU \|\| decoded->op == M68K_BFEXTS \|\| decoded->op == M68K_BFFFO)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1522 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1523 ea = &(decoded->src);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1524 other = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1525 } else {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1526 ea = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1527 other = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1528 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1529 if (*istream & 0x100)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1530 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1531 immed = *(istream++);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1532 other->addr_mode = MODE_REG;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1533 other->params.regs.pri = immed >> 12 & 0x7;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1534 } else {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1535 immed = *(istream++);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1536 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1537 decoded->extra.size = OPSIZE_UNSIZED;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1538 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, ea);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1539 ea->addr_mode \|= M68K_FLAG_BITFIELD;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1540 ea->bitfield = immed & 0xFFF;
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1541 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	1542 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1543 break;
992 261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	1544 case F_LINE:
261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	1545 //TODO: Decode FPU instructions for members of the 68K family with an FPU
261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	1546 decoded->op = M68K_F_LINE_TRAP;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1547 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1548 }
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1549 if (decoded->op == M68K_INVALID) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1550 decoded->src.params.immed = *start;
981 902c53d9c16f Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 835 diff changeset	1551 decoded->bytes = 2;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1552 return start + 1;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1553 }
981 902c53d9c16f Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 835 diff changeset	1554 decoded->bytes = 2 * (istream + 1 - start);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1555 return istream+1;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1556 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1557
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1558 uint32_t m68k_branch_target(m68kinst * inst, uint32_t dregs, uint32_t aregs)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1559 {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1560 if(inst->op == M68K_BCC \|\| inst->op == M68K_BSR \|\| inst->op == M68K_DBCC) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1561 return inst->address + 2 + inst->src.params.immed;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1562 } else if(inst->op == M68K_JMP \|\| inst->op == M68K_JSR) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1563 uint32_t ret = 0;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1564 switch(inst->src.addr_mode)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1565 {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1566 case MODE_AREG_INDIRECT:
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1567 ret = aregs[inst->src.params.regs.pri];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1568 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1569 case MODE_AREG_INDEX_DISP8: {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1570 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1571 ret = aregs[inst->src.params.regs.pri];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1572 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1573 if (inst->src.params.regs.sec & 1) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1574 //32-bit index register
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1575 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1576 } else {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1577 //16-bit index register
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1578 if (regfile[sec_reg] & 0x8000) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1579 ret += (0xFFFF0000 \| regfile[sec_reg]);
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1580 } else {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1581 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1582 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1583 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1584 ret += inst->src.params.regs.displacement;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1585 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1586 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1587 case MODE_PC_DISPLACE:
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1588 ret = inst->src.params.regs.displacement + inst->address + 2;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1589 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1590 case MODE_PC_INDEX_DISP8: {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1591 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1592 ret = inst->address + 2;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1593 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1594 if (inst->src.params.regs.sec & 1) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1595 //32-bit index register
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1596 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1597 } else {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1598 //16-bit index register
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1599 if (regfile[sec_reg] & 0x8000) {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1600 ret += (0xFFFF0000 \| regfile[sec_reg]);
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1601 } else {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1602 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1603 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1604 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1605 ret += inst->src.params.regs.displacement;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1606 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1607 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1608 case MODE_ABSOLUTE:
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1609 case MODE_ABSOLUTE_SHORT:
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1610 ret = inst->src.params.immed;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1611 break;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1612 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1613 return ret;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1614 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1615 return 0;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1616 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1617
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1618 uint8_t m68k_is_branch(m68kinst * inst)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1619 {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1620 return (inst->op == M68K_BCC && inst->extra.cond != COND_FALSE)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1621 \|\| (inst->op == M68K_DBCC && inst->extra.cond != COND_TRUE)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1622 \|\| inst->op == M68K_BSR \|\| inst->op == M68K_JMP \|\| inst->op == M68K_JSR;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1623 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1624
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1625 uint8_t m68k_is_noncall_branch(m68kinst * inst)
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1626 {
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1627 return m68k_is_branch(inst) && inst->op != M68K_BSR && inst->op != M68K_JSR;
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1628 }
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1629
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	1630
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1631 char * mnemonics[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1632 "abcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1633 "add",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1634 "addx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1635 "and",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1636 "andi",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1637 "andi",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1638 "asl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1639 "asr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1640 "bcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1641 "bchg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1642 "bclr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1643 "bset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1644 "bsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1645 "btst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1646 "chk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1647 "clr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1648 "cmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1649 "dbcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1650 "divs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1651 "divu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1652 "eor",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1653 "eori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1654 "eori",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1655 "exg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1656 "ext",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1657 "illegal",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1658 "jmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1659 "jsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1660 "lea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1661 "link",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1662 "lsl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1663 "lsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1664 "move",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1665 "move",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1666 "move",//from_sr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1667 "move",//sr
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1668 "move",//usp
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1669 "movem",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1670 "movep",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1671 "muls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1672 "mulu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1673 "nbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1674 "neg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1675 "negx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1676 "nop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1677 "not",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1678 "or",
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1679 "ori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1680 "ori",//sr
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1681 "pea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1682 "reset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1683 "rol",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1684 "ror",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1685 "roxl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1686 "roxr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1687 "rte",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1688 "rtr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1689 "rts",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1690 "sbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1691 "scc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1692 "stop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1693 "sub",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1694 "subx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1695 "swap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1696 "tas",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1697 "trap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1698 "trapv",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1699 "tst",
12 db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions. Mike Pavone <pavone@retrodev.com> parents: 11 diff changeset	1700 "unlk",
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1701 "invalid",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1702 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1703 "bkpt",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1704 "move", //from ccr
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1705 "movec",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1706 "moves",
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1707 "rtd",
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1708 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1709 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1710 "bfchg",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1711 "bfclr",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1712 "bfexts",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1713 "bfextu",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1714 "bfffo",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1715 "bfins",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1716 "bfset",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1717 "bftst",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1718 "callm",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1719 "cas",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1720 "cas2",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1721 "chk2",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1722 "cmp2",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1723 "cpbcc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1724 "cpdbcc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1725 "cpgen",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1726 "cprestore",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1727 "cpsave",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1728 "cpscc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1729 "cptrapcc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1730 "divsl",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1731 "divul",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1732 "extb",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1733 "pack",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1734 "rtm",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1735 "trapcc",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1736 "unpk"
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1737 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1738 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1739
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1740 char * cond_mnem[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1741 "ra",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1742 "f",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1743 "hi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1744 "ls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1745 "cc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1746 "cs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1747 "ne",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1748 "eq",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1749 "vc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1750 "vs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1751 "pl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1752 "mi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1753 "ge",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1754 "lt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1755 "gt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1756 "le"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1757 };
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1758 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1759 char * cr_mnem[] = {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1760 "SFC",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1761 "DFC",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1762 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1763 "CACR",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1764 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1765 "USP",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1766 "VBR",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1767 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1768 "CAAR",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1769 "MSP",
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1770 "ISP"
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1771 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1772 };
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	1773 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1774
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	1775 int m68k_disasm_op(m68k_op_info decoded, char dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1776 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1777 char * c = need_comma ? "," : "";
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1778 int ret = 0;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1779 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1780 uint8_t addr_mode = decoded->addr_mode & (~M68K_FLAG_BITFIELD);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1781 #else
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1782 uint8_t addr_mode = decoded->addr_mode;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1783 #endif
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1784 switch(addr_mode)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1785 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1786 case MODE_REG:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1787 ret = sprintf(dst, "%s d%d", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1788 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1789 case MODE_AREG:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1790 ret = sprintf(dst, "%s a%d", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1791 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1792 case MODE_AREG_INDIRECT:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1793 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1794 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1795 case MODE_AREG_POSTINC:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1796 ret = sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1797 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	1798 case MODE_AREG_PREDEC:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1799 ret = sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1800 break;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	1801 case MODE_AREG_DISPLACE:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1802 ret = sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1803 break;
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	1804 case MODE_AREG_INDEX_DISP8:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1805 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1806 if (decoded->params.regs.scale)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1807 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1808 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1809 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1810 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1811 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1812 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1813 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1814 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1815 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1816 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1817 case MODE_AREG_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1818 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1819 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1820 ret = sprintf(dst, "%s (%d.%c, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1821 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1822 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1823 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1824 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1825 ret = sprintf(dst, "%s (a%d, %c%d.%c*%d)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1826 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1827 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1828 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1829 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1830 case MODE_AREG_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1831 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1832 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1833 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1834 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1835 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d])", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1836 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1837 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1838 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1839 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1840 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1841 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1842 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1843 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1844 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1845 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1846 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1847 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1848 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1849 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1850 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1851 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1852 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1853 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1854 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1855 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1856 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1857 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1858 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1859 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1860 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1861 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1862 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1863 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1864 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1865 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1866 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1867 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1868 case MODE_AREG_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1869 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1870 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1871 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1872 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1873 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1874 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1875 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1876 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1877 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1878 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1879 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1880 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1881 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1882 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1883 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1884 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1885 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1886 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1887 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1888 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1889 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1890 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1891 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1892 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1893 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1894 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1895 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1896 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1897 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1898 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1899 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1900 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1901 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1902 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1903 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1904 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1905 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1906 case MODE_AREG_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1907 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1908 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1909 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1910 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1911 ret = sprintf(dst, "%s ([a%d])", c, decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1912 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1913 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1914 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1915 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1916 ret = sprintf(dst, "%s ([%d.%c, a%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1917 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1918 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1919 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1920 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1921 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1922 ret = sprintf(dst, "%s ([a%d], %d.%c)", c, decoded->params.regs.pri, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1923 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1924 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1925 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1926 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1927 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1928 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1929 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1930 ret = sprintf(dst, "%s ([%d.%c, a%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1931 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1932 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1933 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1934 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	1935 break;
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1936 case MODE_AREG_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1937 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1938 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1939 ret = sprintf(dst, "%s (%d.%c, a%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1940 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1941 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1942 //this is a lossy representation of the encoded instruction
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1943 //not sure if there's a better way to print it though
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1944 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1945 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1946 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1947 case MODE_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1948 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1949 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1950 ret = sprintf(dst, "%s (%d.%c, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1951 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1952 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1953 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1954 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1955 ret = sprintf(dst, "%s (%c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1956 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1957 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1958 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1959 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1960 case MODE_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1961 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1962 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1963 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1964 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1965 ret = sprintf(dst, "%s ([%c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1966 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1967 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1968 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1969 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1970 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1971 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1972 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1973 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1974 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1975 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1976 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1977 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1978 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1979 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1980 ret = sprintf(dst, "%s ([%c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1981 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1982 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1983 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1984 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1985 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1986 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1987 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1988 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1989 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1990 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1991 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1992 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1993 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1994 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1995 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1996 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1997 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1998 case MODE_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	1999 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2000 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2001 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2002 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2003 ret = sprintf(dst, "%s ([], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2004 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2005 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2006 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2007 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2008 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2009 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2010 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2011 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2012 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2013 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2014 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2015 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2016 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2017 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2018 ret = sprintf(dst, "%s ([], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2019 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2020 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2021 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2022 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2023 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2024 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2025 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2026 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2027 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2028 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2029 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2030 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2031 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2032 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2033 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2034 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2035 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2036 case MODE_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2037 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2038 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2039 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2040 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2041 ret = sprintf(dst, "%s ([])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2042 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2043 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2044 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2045 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2046 ret = sprintf(dst, "%s ([%d.%c])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2047 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2048 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2049 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2050 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2051 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2052 ret = sprintf(dst, "%s ([], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2053 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2054 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2055 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2056 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2057 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2058 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2059 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2060 ret = sprintf(dst, "%s ([%d.%c], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2061 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2062 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2063 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2064 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2065 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2066 case MODE_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2067 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2068 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2069 ret = sprintf(dst, "%s (%d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2070 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2071 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2072 ret = sprintf(dst, "%s ()", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2073 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2074 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2075 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2076 case MODE_IMMEDIATE:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 60 diff changeset	2077 case MODE_IMMEDIATE_WORD:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2078 ret = sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2079 break;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2080 case MODE_ABSOLUTE_SHORT:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2081 if (labels) {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2082 ret = sprintf(dst, "%s ", c);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2083 ret += label_fun(dst+ret, decoded->params.immed, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2084 strcat(dst+ret, ".w");
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2085 ret = ret + 2;
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2086 } else {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2087 ret = sprintf(dst, "%s $%X.w", c, decoded->params.immed);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2088 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2089 break;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2090 case MODE_ABSOLUTE:
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2091 if (labels) {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2092 ret = sprintf(dst, "%s ", c);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2093 ret += label_fun(dst+ret, decoded->params.immed, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2094 strcat(dst+ret, ".l");
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2095 ret = ret + 2;
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2096 } else {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2097 ret = sprintf(dst, "%s $%X", c, decoded->params.immed);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2098 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2099 break;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2100 case MODE_PC_DISPLACE:
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2101 if (labels) {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2102 ret = sprintf(dst, "%s ", c);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2103 ret += label_fun(dst+ret, address + 2 + decoded->params.regs.displacement, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2104 strcat(dst+ret, "(pc)");
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2105 ret = ret + 4;
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2106 } else {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2107 ret = sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2108 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2109 break;
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 69 diff changeset	2110 case MODE_PC_INDEX_DISP8:
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2111 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2112 if (decoded->params.regs.scale)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2113 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2114 ret = sprintf(dst, "%s (%d, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2115 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2116 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2117 ret = sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2118 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2119 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2120 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2121 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2122 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2123 case MODE_PC_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2124 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2125 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2126 ret = sprintf(dst, "%s (%d.%c, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2127 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2128 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2129 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2130 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2131 ret = sprintf(dst, "%s (pc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2132 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2133 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2134 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2135 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2136 case MODE_PC_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2137 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2138 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2139 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2140 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2141 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2142 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2143 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2144 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2145 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2146 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2147 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2148 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2149 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2150 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2151 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2152 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2153 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2154 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2155 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2156 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2157 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2158 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2159 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2160 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2161 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2162 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2163 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2164 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2165 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2166 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2167 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2168 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2169 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2170 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2171 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2172 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2173 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2174 case MODE_PC_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2175 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2176 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2177 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2178 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2179 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2180 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2181 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2182 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2183 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2184 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2185 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2186 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2187 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2188 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2189 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2190 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2191 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2192 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2193 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2194 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2195 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2196 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2197 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2198 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2199 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2200 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2201 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2202 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2203 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2204 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2205 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2206 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2207 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2208 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2209 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2210 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2211 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2212 case MODE_PC_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2213 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2214 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2215 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2216 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2217 ret = sprintf(dst, "%s ([pc])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2218 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2219 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2220 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2221 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2222 ret = sprintf(dst, "%s ([%d.%c, pc])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2223 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2224 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2225 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2226 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2227 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2228 ret = sprintf(dst, "%s ([pc], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2229 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2230 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2231 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2232 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2233 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2234 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2235 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2236 ret = sprintf(dst, "%s ([%d.%c, pc], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2237 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2238 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2239 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2240 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2241 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2242 case MODE_PC_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2243 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2244 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2245 ret = sprintf(dst, "%s (%d.%c, pc)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2246 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2247 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2248 ret = sprintf(dst, "%s (pc)", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2249 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2250 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2251 case MODE_ZPC_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2252 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2253 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2254 ret = sprintf(dst, "%s (%d.%c, zpc, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2255 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2256 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2257 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2258 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2259 ret = sprintf(dst, "%s (zpc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2260 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2261 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2262 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2263 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2264 case MODE_ZPC_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2265 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2266 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2267 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2268 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2269 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2270 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2271 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2272 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2273 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2274 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2275 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2276 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2277 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2278 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2279 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2280 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2281 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2282 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2283 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2284 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2285 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2286 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2287 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2288 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2289 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2290 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2291 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2292 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2293 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2294 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2295 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2296 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2297 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2298 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2299 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2300 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2301 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2302 case MODE_ZPC_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2303 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2304 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2305 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2306 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2307 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2308 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2309 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2310 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2311 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2312 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2313 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2314 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2315 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2316 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2317 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2318 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2319 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2320 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2321 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2322 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2323 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2324 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2325 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2326 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2327 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2328 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2329 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2330 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2331 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2332 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2333 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2334 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2335 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2336 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2337 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2338 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2339 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2340 case MODE_ZPC_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2341 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2342 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2343 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2344 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2345 ret = sprintf(dst, "%s ([zpc])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2346 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2347 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2348 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2349 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2350 ret = sprintf(dst, "%s ([%d.%c, zpc])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2351 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2352 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2353 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2354 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2355 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2356 ret = sprintf(dst, "%s ([zpc], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2357 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2358 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2359 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2360 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2361 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2362 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2363 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2364 ret = sprintf(dst, "%s ([%d.%c, zpc], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2365 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2366 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2367 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2368 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2369 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2370 case MODE_ZPC_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2371 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2372 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2373 ret = sprintf(dst, "%s (%d.%c, zpc)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2374 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2375 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2376 ret = sprintf(dst, "%s (zpc)", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2377 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2378 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	2379 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2380 default:
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2381 ret = 0;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	2382 }
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2383 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2384 if (decoded->addr_mode & M68K_FLAG_BITFIELD)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2385 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2386 switch (decoded->bitfield & 0x820)
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2387 {
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2388 case 0:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2389 return ret + sprintf(dst+ret, " {$%X:%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2390 case 0x20:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2391 return ret + sprintf(dst+ret, " {$%X:d%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x7);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2392 case 0x800:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2393 return ret + sprintf(dst+ret, " {d%d:%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2394 case 0x820:
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2395 return ret + sprintf(dst+ret, " {d%d:d%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x7);
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2396 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2397 }
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2398 #endif
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	2399 return ret;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	2400 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2401
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2402 int m68k_disasm_movem_op(m68k_op_info decoded, m68k_op_info other, char dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void data)
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2403 {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2404 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2405 char rtype, last_rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2406 int oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2407 if (decoded->addr_mode == MODE_REG) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2408 if (other->addr_mode == MODE_AREG_PREDEC) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2409 bit = 15;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2410 dir = -1;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2411 } else {
69 36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination Mike Pavone <pavone@retrodev.com> parents: 68 diff changeset	2412 dir = 1;
36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination Mike Pavone <pavone@retrodev.com> parents: 68 diff changeset	2413 bit = 0;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2414 }
68 1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2415 if (need_comma) {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2416 strcat(dst, ", ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2417 oplen = 2;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2418 } else {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2419 strcat(dst, " ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2420 oplen = 1;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2421 }
1c9a4052a2c0 Fix decoding and disassembly of MOVEM Mike Pavone <pavone@retrodev.com> parents: 62 diff changeset	2422 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 13 diff changeset	2423 if (decoded->params.immed & (1 << bit)) {
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2424 if (reg > 7) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2425 rtype = "a";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2426 regnum = reg - 8;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2427 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2428 rtype = "d";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2429 regnum = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2430 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2431 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2432 last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2433 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2434 } else if(last >= 0) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2435 if (first != last) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2436 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2437 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2438 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2439 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2440 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2441 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2442 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2443 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2444 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2445 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2446 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2447 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2448 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2449 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2450 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2451 if (last >= 0 && last != first) {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2452 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2453 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2454 return oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2455 } else {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2456 return m68k_disasm_op(decoded, dst, need_comma, labels, address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2457 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2458 }
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2459
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2460 int m68k_default_label_fun(char * dst, uint32_t address, void * data)
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2461 {
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2462 return sprintf(dst, "ADR_%X", address);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2463 }
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2464
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2465 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels, format_label_fun label_fun, void * data)
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2466 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2467 int ret,op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2468 uint8_t size;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2469 char * special_op = "CCR";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2470 switch (decoded->op)
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2471 {
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2472 case M68K_BCC:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2473 case M68K_DBCC:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2474 case M68K_SCC:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2475 ret = strlen(mnemonics[decoded->op]) - 2;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2476 memcpy(dst, mnemonics[decoded->op], ret);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2477 dst[ret] = 0;
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2478 strcpy(dst+ret, cond_mnem[decoded->extra.cond]);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2479 ret = strlen(dst);
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2480 if (decoded->op != M68K_SCC) {
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2481 if (labels) {
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2482 if (decoded->op == M68K_DBCC) {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2483 ret += sprintf(dst+ret, " d%d, ", decoded->dst.params.regs.pri);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2484 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2485 } else {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2486 dst[ret++] = ' ';
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2487 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2488 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2489 } else {
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2490 if (decoded->op == M68K_DBCC) {
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2491 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2492 } else {
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2493 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2494 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2495 }
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2496 return ret;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2497 }
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2498 break;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2499 case M68K_BSR:
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2500 if (labels) {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2501 ret = sprintf(dst, "bsr%s ", decoded->variant == VAR_BYTE ? ".s" : "");
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2502 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2503 } else {
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2504 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2505 }
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2506 return ret;
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2507 case M68K_MOVE_FROM_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2508 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2509 ret += sprintf(dst + ret, " SR");
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2510 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2511 return ret;
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2512 case M68K_ANDI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2513 case M68K_EORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2514 case M68K_MOVE_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2515 case M68K_ORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2516 special_op = "SR";
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2517 case M68K_ANDI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2518 case M68K_EORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2519 case M68K_MOVE_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2520 case M68K_ORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2521 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2522 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2523 ret += sprintf(dst + ret, ", %s", special_op);
168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2524 return ret;
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2525 case M68K_MOVE_USP:
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2526 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2527 if (decoded->src.addr_mode != MODE_UNUSED) {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2528 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2529 ret += sprintf(dst + ret, ", USP");
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2530 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2531 ret += sprintf(dst + ret, "USP, ");
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2532 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
50 4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2533 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2534 return ret;
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2535 case M68K_INVALID:
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2536 ret = sprintf(dst, "dc.w $%X", decoded->src.params.immed);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2537 return ret;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2538 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2539 case M68K_MOVEC:
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2540 ret = sprintf(dst, "%s ", mnemonics[decoded->op]);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2541 if (decoded->src.addr_mode == MODE_UNUSED) {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2542 ret += sprintf(dst + ret, "%s, ", cr_mnem[decoded->src.params.immed]);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2543 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2544 } else {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2545 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2546 ret += sprintf(dst + ret, ", %s", cr_mnem[decoded->dst.params.immed]);
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2547 }
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2548 return ret;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	2549 #endif
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2550 default:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2551 size = decoded->extra.size;
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2552 ret = sprintf(dst, "%s%s%s",
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2553 mnemonics[decoded->op],
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2554 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""),
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2555 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : "")));
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2556 }
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2557 if (decoded->op == M68K_MOVEM) {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2558 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2559 ret += op1len;
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2560 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2561 } else {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2562 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2563 ret += op1len;
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2564 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address, label_fun, data);
13 168b1a873895 Improve disassembly. FIx some decoding bugs. Mike Pavone <pavone@retrodev.com> parents: 12 diff changeset	2565 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2566 return ret;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2567 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2568
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2569 int m68k_disasm(m68kinst * decoded, char * dst)
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2570 {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2571 return m68k_disasm_ex(decoded, dst, 0, NULL, NULL);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2572 }
ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2573
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2574 int m68k_disasm_labels(m68kinst * decoded, char * dst, format_label_fun label_fun, void * data)
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2575 {
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2576 if (!label_fun)
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2577 {
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2578 label_fun = m68k_default_label_fun;
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2579 }
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	2580 return m68k_disasm_ex(decoded, dst, 1, label_fun, data);
134 ab50421b1b7a Improve disassembler Mike Pavone <pavone@retrodev.com> parents: 120 diff changeset	2581 }

Mercurial > repos > blastem

annotate 68kinst.c @ 995:2bc27415565b