repos/blastem: runtime.S annotate

annotate runtime.S @ 320:67b6d351df0e

Fix check for code writes

author	Mike Pavone <pavone@retrodev.com>
date	Sat, 11 May 2013 01:57:41 -0700
parents	e5e8b48ad157
children	146c87616b05

rev	line source
17 de0085d4ea40 Add asssembly runtime code stub Mike Pavone <pavone@retrodev.com> parents: diff changeset	1
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	2 .global handle_cycle_limit
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	3 .global do_sync
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	4 handle_cycle_limit:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	5 cmp 84(%rsi), %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	6 jb skip_sync
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	7 do_sync:
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	8 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	9 mov %rsi, %rdi
198 209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	10 xor %esi, %esi
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	11 call sync_components
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	12 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	13 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	14 skip_sync:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	15 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	16
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	17 .global handle_cycle_limit_int
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	18 handle_cycle_limit_int:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	19 cmp 88(%rsi), %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	20 jb skip_int
251 4a7ac10ac2d9 Fix target cycle count after 68K interrupt Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	21 mov 84(%rsi), %ebp
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	22 /* swap USP and SSP if not already in supervisor mode */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	23 bt $5, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	24 jc already_supervisor
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	25 mov 72(%rsi), %edi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	26 mov %r15d, 72(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	27 mov %edi, %r15d
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	28 already_supervisor:
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	29 /* save PC */
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	30 sub $4, %r15d
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	31 mov %r15d, %edi
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	32 call m68k_write_long_lowfirst
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	33 /* save status register on stack */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	34 sub $2, %r15d
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	35 mov %r15d, %edi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	36 call get_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	37 call m68k_write_word
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	38 /* update status register */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	39 andb $0xF8, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	40 mov 92(%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	41 or $0x20, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	42 or %cl, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	43 /* calculate interrupt vector address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	44 mov 92(%rsi), %ecx
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 251 diff changeset	45 mov %cx, 6(%rsi) /* interrupt acknowlege */
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	46 shl $2, %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	47 add $0x60, %ecx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	48 call m68k_read_long_scratch1
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	49 call m68k_native_addr_and_sync
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	50 add $24, %eax
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	51 /* discard function return address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	52 pop %rdi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	53 jmp *%rcx
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	54 ret
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	55 skip_int:
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	56 cmp 84(%rsi), %eax
198 209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	57 jb skip_sync_int
209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	58 call m68k_save_context
209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	59 mov %rsi, %rdi
209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	60 mov %ecx, %esi
209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	61 call sync_components
209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	62 mov %rax, %rsi
209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	63 call m68k_load_context
209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	64 skip_sync_int:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	65 ret
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	66
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	67 .global m68k_trap
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	68 m68k_trap:
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	69 push %rdi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	70 push %rcx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	71 /* swap USP and SSP if not already in supervisor mode */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	72 bt $5, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	73 jc already_supervisor_trap
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	74 mov 72(%rsi), %edi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	75 mov %r15d, 72(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	76 mov %edi, %r15d
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	77 already_supervisor_trap:
175 7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	78 /* save PC */
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	79 sub $4, %r15d
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	80 mov %r15d, %edi
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	81 pop %rcx
7504200cac86 Fix order of SR and PC saved in an exception stack frame Mike Pavone <pavone@retrodev.com> parents: 160 diff changeset	82 call m68k_write_long_lowfirst
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	83 /* save status register on stack */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	84 sub $2, %r15d
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	85 mov %r15d, %edi
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	86 call get_sr
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	87 call m68k_write_word
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	88 /* update status register */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	89 andb $0xF8, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	90 mov 92(%rsi), %cl
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	91 or $0x20, %cl
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	92 or %cl, 5(%rsi)
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	93 /* calculate interrupt vector address */
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	94 pop %rcx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	95 shl $2, %ecx
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	96 call m68k_read_long_scratch1
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	97 call m68k_native_addr_and_sync
226 28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 209 diff changeset	98 add $18, %eax
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	99 jmp *%rcx
176 e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	100
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	101 invalid_msg:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	102 .asciz "Invalid instruction at %X\n"
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	103
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	104 .global m68k_invalid
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	105 m68k_invalid:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	106 lea invalid_msg(%rip), %rdi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	107 mov %ecx, %esi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	108 xor %rax, %rax
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	109 call printf
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	110 mov $1, %rdi
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it Mike Pavone <pavone@retrodev.com> parents: 175 diff changeset	111 call exit
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	112
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	113 .global bcd_add
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	114 bcd_add:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	115 xchg %rax, %rdi
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	116
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	117 mov %cl, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	118 mov %al, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	119 and $0xF, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	120 and $0xF, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	121 and $0xF0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	122 and $0xF0, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	123 add %ah, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	124 cmp $10, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	125 jb no_adjust
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	126 add $6, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	127 no_adjust:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	128 add %ch, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	129 add %al, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	130 mov $0, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	131 jc def_adjust
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	132 cmp $0xA0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	133 jb no_adjust_h
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	134 def_adjust:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	135 add $0x60, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	136 mov $1, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	137 no_adjust_h:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	138
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	139 mov %rdi, %rax
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	140 ret
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	141
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	142 .global bcd_sub
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	143 bcd_sub:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	144 xchg %rax, %rdi
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	145
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	146 mov %cl, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	147 mov %al, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	148 and $0xF, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	149 and $0xF, %ah
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	150 and $0xF0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	151 and $0xF0, %al
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	152 sub %ah, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	153 cmp $10, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	154 jb no_adjusts
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	155 sub $6, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	156 no_adjusts:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	157 add %ch, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	158 sub %al, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	159 mov $0, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	160 jc def_adjusts
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	161 cmp $0xA0, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	162 jb no_adjust_hs
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	163 def_adjusts:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	164 sub $0x60, %cl
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	165 mov $1, %ch
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	166 no_adjust_hs:
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	167
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	168 mov %rdi, %rax
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	169 ret
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 149 diff changeset	170
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	171 int_dbg_msg:
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	172 .asciz "Executing Interrupt!"
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	173 print_int_dbg:
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	174 call m68k_save_context
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	175 push %rsi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	176 lea int_dbg_msg(%rip), %rdi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	177 call puts
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	178 pop %rsi
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	179 call m68k_load_context
60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	180 ret
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	181
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	182 .global get_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	183 get_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	184 mov 5(%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	185 shl $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	186 mov (%rsi), %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	187 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	188 or %bl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	189 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	190 or %dl, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	191 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	192 or %bh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	193 shl $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	194 or %dh, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	195 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	196
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	197 .global set_sr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	198 set_sr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	199 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	200 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	201 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	202 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	203 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	204 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	205 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	206 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	207 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	208 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	209 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	210 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	211 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	212 mov %cl, (%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	213 shr $8, %cx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	214 mov %cl, 5(%rsi)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	215 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	216
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	217 .global set_ccr
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	218 set_ccr:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	219 mov %cl, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	220 and $1, %dh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	221 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	222 mov %cl, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	223 and $1, %bh
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	224 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	225 mov %cl, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	226 and $1, %dl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	227 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	228 mov %cl, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	229 and $1, %bl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	230 shr $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	231 and $1, %cl
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	232 mov %cl, (%rsi)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	233 ret
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	234
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	235 do_vdp_port_write:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	236 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	237 mov %rcx, %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	238 call vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	239 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	240 call m68k_load_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	241 ret
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	242
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	243 do_vdp_port_read:
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	244 mov %ecx, %edi
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	245 call m68k_save_context
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	246 call vdp_port_read
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	247 mov %rax, %rsi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	248 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	249 mov 136(%rsi), %cx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	250 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	251
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	252 do_io_write:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	253 call m68k_save_context
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	254 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	255 mov %ecx, %edx
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	256 call io_write
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	257 mov %rax, %rsi
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	258 call m68k_load_context
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	259 ret
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	260 do_io_read:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	261 mov %ecx, %edi
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	262 and $0x1FFFF, %edi
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	263 call m68k_save_context
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	264 call io_read
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	265 mov %rax, %rsi
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	266 call m68k_load_context
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	267 mov 136(%rsi), %cl
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	268 ret
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	269
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	270 do_io_write_w:
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	271 call m68k_save_context
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	272 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	273 mov %ecx, %edx
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	274 call io_write_w
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	275 mov %rax, %rsi
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	276 call m68k_load_context
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	277 ret
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	278 do_io_read_w:
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	279 mov %ecx, %edi
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	280 and $0x1FFFF, %edi
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	281 call m68k_save_context
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	282 call io_read_w
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	283 mov %rax, %rsi
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	284 call m68k_load_context
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	285 mov 136(%rsi), %cx
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	286 ret
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	287
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	288 bad_access_msg:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	289 .asciz "Program tried to access illegal 68K address %X\n"
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	290
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	291 .global m68k_write_word
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	292 .global try_fifo_write
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	293 m68k_write_word:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	294 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	295 and $0xFFFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	296 cmp $0x400000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	297 jbe cart_w
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	298 cmp $0xE00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	299 jae workram_w
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	300 cmp $0xC00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	301 jae vdp_psg_w
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	302 cmp $0xA00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	303 jb not_io_w
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	304 cmp $0xA12000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	305 jae not_io_w
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	306 jmp do_io_write_w
1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	307 not_io_w:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	308 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	309 workram_w:
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	310 and $0xFFFF, %edi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	311 mov %cx, (%r9, %rdi)
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	312 mov %edi, %ecx
320 67b6d351df0e Fix check for code writes Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	313 shr $11, %ecx
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	314 bt %ecx, 160(%rsi)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	315 jnc not_code
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	316 call m68k_save_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	317 call m68k_handle_code_write
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	318 mov %rax, %rsi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	319 call m68k_load_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	320 not_code:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	321 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	322 cart_w:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	323 mov %cx, (%r8, %rdi)
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	324 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	325 vdp_psg_w:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	326 test $0x2700E0, %edi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	327 jnz crash
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	328 and $0x1F, %edi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	329 cmp $4, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	330 jb try_fifo_write
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	331 jmp do_vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	332 try_fifo_write:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	333 push %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	334 push %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	335 /* fetch VDP context pointer from 68K context */
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	336 mov 128(%rsi), %rdx
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	337 /* check DMA flag */
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	338 bt $6, 19(%rdx)
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 145 diff changeset	339 jc fifo_fallback
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	340 /* get fifo_cur and compare it to fifo_end */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	341 mov (%rdx), %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	342 cmp %rbx, 8(%rdx)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	343 /* bail out if fifo is full */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	344 je fifo_fallback
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	345 /* populate FIFO entry */
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	346 mov %cx, 6(%rbx) /* value */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	347 mov 16(%rdx), %cx
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	348 mov %cx, 4(%rbx) /* address */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	349 mov 18(%rdx), %cl
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	350 mov %cl, 8(%rbx) /* cd */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	351 movb $0, 9(%rbx) /* partial */
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	352 mov %eax, %ecx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	353 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	354 sub %eax, %ecx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	355 mov %ecx, (%rbx) /* cycle */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	356 /* update fifo_cur and store back in 68K context */
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	357 add $12, %rbx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	358 mov %rbx, (%rdx)
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	359 /* update address register */
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	360 movzbw 35(%rdx), %bx
aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	361 add %bx, 16(%rdx)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	362 /* clear pending flag */
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	363 andb $0xEF, 19(%rdx)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	364 pop %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	365 pop %rdx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	366 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	367 fifo_fallback:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	368 pop %rbx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	369 pop %rdx
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	370 jmp do_vdp_port_write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	371 crash:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	372 mov %edi, %esi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	373 lea bad_access_msg(%rip), %rdi
160 69ac23d42897 Fix crash in printf from "crash" function due to lack of clearing rax Mike Pavone <pavone@retrodev.com> parents: 153 diff changeset	374 xor %rax, %rax
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	375 call printf
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	376 mov $1, %rdi
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	377 call exit
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	378
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	379 .global m68k_write_byte
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	380 m68k_write_byte:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	381 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	382 and $0xFFFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	383 cmp $0x400000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	384 jbe cart_wb
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	385 cmp $0xE00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	386 jae workram_wb
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	387 cmp $0xC00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	388 jae vdp_psg_wb
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	389 cmp $0xA00000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	390 jb not_io_wb
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	391 cmp $0xA12000, %edi
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	392 jae not_io_wb
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	393 jmp do_io_write
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	394 not_io_wb:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	395 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	396 workram_wb:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	397 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	398 xor $1, %edi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	399 and $0xFFFF, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	400 mov %cl, (%r9, %rdi)
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	401 mov %edi, %ecx
320 67b6d351df0e Fix check for code writes Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	402 shr $11, %ecx
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	403 bt %ecx, 160(%rsi)
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	404 jnc not_code_b
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	405 xor $1, %edi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	406 call m68k_save_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	407 call m68k_handle_code_write
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	408 mov %rax, %rsi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	409 call m68k_load_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	410 not_code_b:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	411 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	412 cart_wb:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	413 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	414 xor $1, %edi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	415 mov %cl, (%r8, %rdi)
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	416 ret
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	417 vdp_psg_wb:
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	418 push %rdx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	419 mov %cl, %dl
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	420 and $0xFF, %cx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	421 shl $8, %dx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	422 or %dx, %cx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	423 pop %rdx
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	424 jmp vdp_psg_w
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	425
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	426 .global m68k_write_long_lowfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	427 m68k_write_long_lowfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	428 push %rdi
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	429 push %rcx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	430 add $2, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	431 call m68k_write_word
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	432 pop %rcx
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	433 pop %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	434 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	435 jmp m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	436
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	437 .global m68k_write_long_highfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	438 m68k_write_long_highfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	439 push %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	440 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	441 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	442 call m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	443 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	444 pop %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	445 add $2, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	446 jmp m68k_write_word
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	447
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	448 inccycles:
251 4a7ac10ac2d9 Fix target cycle count after 68K interrupt Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	449 cmp %ebp, %eax
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	450 jnb do_limit
251 4a7ac10ac2d9 Fix target cycle count after 68K interrupt Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	451 add $4, %eax
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	452 ret
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	453 do_limit:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	454 push %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	455 push %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	456 call handle_cycle_limit
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	457 pop %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	458 pop %rcx
251 4a7ac10ac2d9 Fix target cycle count after 68K interrupt Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	459 add $4, %eax
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	460 ret
17 de0085d4ea40 Add asssembly runtime code stub Mike Pavone <pavone@retrodev.com> parents: diff changeset	461
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	462 .global m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	463 m68k_read_word_scratch1:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	464 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	465 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	466 cmp $0x400000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	467 jbe cart
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	468 cmp $0xE00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	469 jae workram
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	470 cmp $0xC00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	471 jae vdp_psg
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	472 cmp $0xA00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	473 jb not_io
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	474 cmp $0xA12000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	475 jae not_io
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	476 call do_io_read_w
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	477 ret
7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	478 not_io:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	479 xor %cx, %cx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	480 dec %cx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	481 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	482 workram:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	483 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	484 mov (%r9, %rcx), %cx
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	485 ret
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	486 vdp_psg:
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	487 test $0x2700E0, %ecx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	488 jnz crash
57 bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 54 diff changeset	489 and $0x1F, %ecx
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	490 jmp do_vdp_port_read
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	491 cart:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	492 mov (%r8, %rcx), %cx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	493 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	494
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	495 .global m68k_read_long_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	496 m68k_read_long_scratch1:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	497 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	498 call m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	499 mov %cx, %di
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	500 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	501 add $2, %ecx
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	502 push %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	503 call m68k_read_word_scratch1
84 2d1ae596db7a Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads. Mike Pavone <pavone@retrodev.com> parents: 83 diff changeset	504 pop %rdi
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	505 and $0xFFFF, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	506 shl $16, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	507 or %edi, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	508 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	509
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	510 .global m68k_read_byte_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	511 m68k_read_byte_scratch1:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	512 call inccycles
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	513 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	514 cmp $0x400000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	515 jbe cart_b
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	516 cmp $0xE00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	517 jae workram_b
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	518 cmp $0xC00000, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	519 jae vdp_psg_b
153 42c031184e8a Implement access to Z80 RAM Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	520 cmp $0xA00000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	521 jb not_io_b
85 1db2a0b655d1 Fix Z80 BUSREQ/RESET implementation. Mike Pavone <pavone@retrodev.com> parents: 84 diff changeset	522 cmp $0xA12000, %ecx
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	523 jae not_io_b
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	524 jmp do_io_read
7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	525 not_io_b:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	526 xor %cl, %cl
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	527 dec %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	528 ret
137 0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	529 vdp_psg_b:
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	530 test $0x2700E0, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	531 jnz crash
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	532 and $0x1F, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	533 bt $0, %ecx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	534 jnc vdp_swap
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	535 jmp do_vdp_port_read
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	536 vdp_swap:
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	537 call do_vdp_port_read
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	538 shr $8, %cx
0e7e1ccc0a81 Implemented HV counter Mike Pavone <pavone@retrodev.com> parents: 127 diff changeset	539 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	540 workram_b:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	541 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	542 xor $1, %ecx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	543 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	544 mov (%r9, %rcx), %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	545 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	546 cart_b:
83 2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	547 /* deal with byte swapping */
2c7267617d71 Implement Z80 reset and bus request registers. Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	548 xor $1, %ecx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	549 mov (%r8, %rcx), %cl
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	550 ret
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	551
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	552 .global m68k_modified_ret_addr
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	553 m68k_modified_ret_addr:
145 15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	554 add $16, %rsp
15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	555 call m68k_native_addr
15b8dce19cf4 Implement m68k_modified_ret_addr Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	556 jmp *%rcx
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	557
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	558 dyn_addr_msg:
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	559 .asciz "Program needs dynamically calculated native address\n"
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	560
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	561 .global m68k_native_addr_and_sync
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	562 m68k_native_addr_and_sync:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	563 call m68k_save_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	564 push %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	565 mov %rsi, %rdi
198 209a37eed3e7 Add support for breaking into the debugger while game is running Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	566 xor %esi, %esi
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	567 call sync_components
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	568 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	569 push %rax
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	570 mov %rax, %rdi
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	571 call get_native_address_trans
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	572 mov %rax, %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	573 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	574 call m68k_load_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	575 ret
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	576
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	577 .global m68k_native_addr
3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 85 diff changeset	578 m68k_native_addr:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	579 call m68k_save_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	580 push %rsi
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	581 mov %rsi, %rdi
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	582 mov %ecx, %esi
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	583 call get_native_address_trans
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	584 mov %rax, %rcx
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	585 pop %rsi
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	586 call m68k_load_context
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	587 ret
193 c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	588
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	589 .global m68k_retrans_stub
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	590 m68k_retrans_stub:
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	591 call m68k_save_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	592 push %rsi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	593 call m68k_retranslate_inst
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	594 pop %rsi
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	595 mov %rax, %rcx
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	596 call m68k_load_context
c66e4636f991 Implement support for self-modifying code Mike Pavone <pavone@retrodev.com> parents: 176 diff changeset	597 jmp *%rcx
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	598
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	599 .global m68k_save_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	600 m68k_save_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	601 mov %bl, 1(%rsi) /* N Flag */
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 198 diff changeset	602 mov %dl, 2(%rsi) /* Z flag */
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 198 diff changeset	603 mov %bh, 3(%rsi) /* V flag */
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	604 mov %dh, 4(%rsi) /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	605 mov %r10d, 8(%rsi) /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	606 mov %r11d, 12(%rsi) /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	607 mov %r12d, 16(%rsi) /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	608 mov %r13d, 40(%rsi) /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	609 mov %r14d, 44(%rsi) /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	610 mov %r15d, 68(%rsi) /* a7 */
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	611 mov %eax, 80(%rsi) /* current cycle count */
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	612 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	613
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	614 .global m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	615 m68k_load_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	616 mov 1(%rsi), %bl /* N Flag */
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 198 diff changeset	617 mov 2(%rsi), %dl /* Z flag */
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 198 diff changeset	618 mov 3(%rsi), %bh /* V flag */
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	619 mov 4(%rsi), %dh /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	620 mov 8(%rsi), %r10d /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	621 mov 12(%rsi), %r11d /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	622 mov 16(%rsi), %r12d /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	623 mov 40(%rsi), %r13d /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	624 mov 44(%rsi), %r14d /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	625 mov 68(%rsi), %r15d /* a7 */
72 7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	626 mov 76(%rsi), %ebp /* target cycle count */
7935cd64d5c8 Implement word wide access to IO area Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	627 mov 80(%rsi), %eax /* current cycle count */
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	628 mov 96(%rsi), %r8d /* cartridge address */
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 72 diff changeset	629 mov 104(%rsi), %r9d /* work ram address */
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	630 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	631
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	632 .global m68k_start_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	633 m68k_start_context:
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	634 push %rbp
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	635 push %r12
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	636 push %r13
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	637 push %r14
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	638 push %r15
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	639
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 17 diff changeset	640 call m68k_load_context
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	641 call *%rdi
209 922b59c09259 Flag fixes for div, negx and not Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	642 call m68k_save_context
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	643
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	644 pop %r15
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	645 pop %r14
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	646 pop %r13
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	647 pop %r12
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	648 pop %rbp
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	649
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	650 ret

Mercurial > repos > blastem

annotate runtime.S @ 320:67b6d351df0e