repos/blastem: z80.cpu annotate

annotate z80.cpu @ 1729:bd13d017f16f

Implemented SET instruction in Z80 core

author	Michael Pavone <pavone@retrodev.com>
date	Sat, 02 Feb 2019 15:42:45 -0800
parents	b0e01e64d76d
children	71f7827ff30a

rev	line source
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 info
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2 prefix z80_
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	3 opcode_size 8
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	4 extra_tables cb ed dded fded ddcb fdcb dd fd
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	5 body z80_run_op
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	6 include z80_util.c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	7 header z80.h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	9 regs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	10 main 8 b c d e h l f a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	11 alt 8 b' c' d' e' h' l' f' a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	12 i 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	13 r 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	14 iff1 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	15 iff2 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	16 imode 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	17 sp 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	18 ix 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	19 iy 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	20 pc 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	21 wz 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	22 nflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	23 last_flag_result 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	24 pvflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	25 chflags 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	26 zflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	27 scratch1 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	28 scratch2 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	29
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	30 flags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	31 register f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	32 S 7 sign last_flag_result.7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	33 Z 6 zero zflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	34 Y 5 bit-5 last_flag_result.5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	35 H 4 half-carry chflags.3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	36 P 2 parity pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	37 V 2 overflow pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	38 X 3 bit-3 last_flag_result.3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	39 N 1 none nflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	40 C 0 carry chflags.7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	41
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	42
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	43 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	44 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	45 add 1 r r
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	46 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	47 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	48 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	49
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	50 z80_run_op
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	51 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	52 dispatch scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	53
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	54 11001011 cb_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	55 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	56 dispatch scratch1 cb
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	57
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	58 11011101 dd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	59 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	60 dispatch scratch1 dd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	61
1712 0a9a88b3d061 Fix ED prefix in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1706 diff changeset	62 11101101 ed_prefix
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	63 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	64 dispatch scratch1 ed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	65
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	66 11111101 fd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	67 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	68 dispatch scratch1 fd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	69
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	70 dd 11001011 ddcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	71 z80_calc_index ix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	72 cycles 2
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	73 mov pc scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	74 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	75 add 1 pc pc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	76 dispatch scratch1 ddcb
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	77
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	78 fd 11001011 fdcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	79 z80_calc_index iy
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	80 cycles 2
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	81 mov pc scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	82 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	83 add 1 pc pc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	84 dispatch scratch1 fdcb
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	85
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	86 z80_check_cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	87 arg cond 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	88 local invert 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	89 switch cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	90 case 0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	91 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	92 lnot zflag invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	93
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	94 case 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	95 meta istrue zflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	96
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	97 case 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	98 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	99 not chflags invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	100 and 0x80 invert invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	101
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	102 case 3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	103 meta istrue invert
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	104 and 0x80 chflags invert
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	105
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	106 case 4
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	107 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	108 lnot pvflag invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	109
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	110 case 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	111 meta istrue pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	112
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	113 case 6
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	114 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	115 not last_flag_result invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	116 and 0x80 invert invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	117
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	118 case 7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	119 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	120 and 0x80 last_flag_result invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	121
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	122 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	123
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	124 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	125 lsl h 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	126 or l scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	127 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	128
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	129 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	130 lsl h 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	131 or l scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	132 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	133
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	134 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	135 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	136 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	137 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	138
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	139 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	140 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	141 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	142 mov scratch1 wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	143 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	144 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	145 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	146 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	147 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	148 or scratch1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	149
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	150 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	151 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	152 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	153 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	154 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	155 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	156 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	157 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	158 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	159
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	160 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	161 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	162 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	163 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	164 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	165 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	166 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	167 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	168 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	169 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	170
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	171 01RRR110 ld_from_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	172 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	173 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	174
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	175 01DDDSSS ld_from_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	176 mov main.S main.D
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	177
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	178 z80_calc_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	179 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	180 mov index wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	181 z80_fetch_immed
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	182 sext 16 scratch1 scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	183 add scratch1 wz wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	184
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	185 z80_fetch_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	186 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	187 z80_calc_index index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	188 mov wz scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	189 cycles 5
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	190 ocall read_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	191
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	192 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	193 mov wz scratch2
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	194 ocall write_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	195
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	196 dd 01RRR110 ld_from_ix
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	197 z80_fetch_index ix
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	198 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	199
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	200 fd 01RRR110 ld_from_iy
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	201 z80_fetch_index iy
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	202 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	203
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	204 00RRR110 ld_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	205 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	206 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	207
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	208 01110RRR ld_to_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	209 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	210 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	211
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	212 dd 01110RRR ld_to_ix
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	213 z80_calc_index ix
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	214 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	215 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	216 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	217
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	218 fd 01110RRR ld_to_iy
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	219 z80_calc_index iy
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	220 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	221 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	222 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	223
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	224 00110110 ld_to_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	225 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	226 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	227
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	228 00001010 ld_a_from_bc
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	229 lsl b 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	230 or c wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	231 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	232 add 1 wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	233 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	234 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	235
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	236 00011010 ld_a_from_de
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	237 lsl d 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	238 or e wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	239 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	240 add 1 wz wz
1724 9a74c2d05672 Fixed a few ld instructions in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	241 ocall read_8
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	242 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	243
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	244 00111010 ld_a_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	245 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	246 mov wz scratch1
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	247 add 1 wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	248 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	249 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	250
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	251 00000010 ld_a_to_bc
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	252 local tmp 8
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	253 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	254 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	255 mov a scratch1
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	256 add c 1 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	257 lsl a 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	258 or tmp wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	259 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	260
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	261 00010010 ld_a_to_de
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	262 local tmp 8
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	263 lsl d 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	264 or e scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	265 mov a scratch1
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	266 add e 1 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	267 lsl a 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	268 or tmp wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	269 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	270
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	271 00110010 ld_a_to_immed
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	272 local tmp 16
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	273 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	274 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	275 mov a scratch1
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	276 add 1 wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	277 ocall write_8
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	278 and 0xFF wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	279 lsl a 8 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	280 or tmp wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	281
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	282 ed 01000111 ld_i_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	283 mov a i
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	284 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	285
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	286 ed 01001111 ld_r_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	287 mov a r
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	288 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	289
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	290 00000001 ld_bc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	291 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	292 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	293 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	294
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	295 00010001 ld_de_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	296 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	297 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	298 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	299
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	300 00100001 ld_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	301 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	302 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	303 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	304
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	305 00110001 ld_sp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	306 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	307 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	308
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	309 dd 00100001 ld_ix_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	310 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	311 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	312
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	313 fd 00100001 ld_iy_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	314 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	315 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	316
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	317 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	318 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	319 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	320 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	321 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	322 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	323 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	324 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	325 mov scratch1 high
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	326 add 1 wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	327
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	328 00101010 ld_hl_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	329 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	330 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	331 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	332
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	333 ed 01001011 ld_bc_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	334 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	335 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	336 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	337
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	338 ed 01011011 ld_de_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	339 meta low e
1724 9a74c2d05672 Fixed a few ld instructions in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	340 meta high d
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	341 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	342
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	343 ed 01101011 ld_hl_from_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	344 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	345 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	346 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	347
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	348 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	349 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	350 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	351 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	352 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	353 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	354 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	355 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	356 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	357 or scratch1 reg reg
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	358 add 1 wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	359
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	360 ed 01111011 ld_sp_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	361 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	362 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	363
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	364 dd 00101010 ld_ix_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	365 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	366 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	367
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	368 fd 00101010 ld_iy_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	369 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	370 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	371
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	372 00100010 ld_hl_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	373 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	374 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	375 mov l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	376 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	377 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	378 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	379 mov h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	380 ocall write_8
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	381 add 1 wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	382
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	383 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	384 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	385 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	386 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	387 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	388 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	389 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	390 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	391 ocall write_8
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	392 add 1 wz wz
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	393
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	394 ed 01000011 ld_bc_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	395 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	396 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	397 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	398
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	399 ed 01010011 ld_de_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	400 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	401 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	402 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	403
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	404 ed 01100011 ld_hl_to_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	405 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	406 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	407 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	408
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	409 ed 01110011 ld_sp_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	410 meta low sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	411 local sph 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	412 lsr sp 8 sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	413 meta high sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	414 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	415
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	416 11111001 ld_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	417 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	418 lsl h 8 sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	419 or l sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	420
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	421 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	422 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	423 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	424 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	425 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	426 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	427 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	428 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	429 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	430 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	431
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	432 11000101 push_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	433 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	434 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	435 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	436
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	437 11010101 push_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	438 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	439 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	440 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	441
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	442 11100101 push_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	443 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	444 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	445 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	446
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	447 11110101 push_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	448 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	449 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	450 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	451
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	452 dd 11100101 push_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	453 local ixh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	454 lsr ix 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	455 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	456 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	457 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	458
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	459 fd 11100101 push_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	460 local iyh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	461 lsr iy 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	462 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	463 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	464 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	465
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	466 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	467 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	468 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	469 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	470 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	471 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	472 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	473 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	474 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	475
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	476 11000001 pop_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	477 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	478 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	479 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	480
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	481 11010001 pop_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	482 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	483 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	484 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	485
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	486 11100001 pop_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	487 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	488 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	489 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	490
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	491 11110001 pop_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	492 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	493 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	494 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	495
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	496 dd 11100001 pop_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	497 local ixh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	498 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	499 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	500 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	501 lsl ixh 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	502 or ixh ix ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	503
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	504 fd 11100001 pop_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	505 local iyh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	506 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	507 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	508 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	509 lsl iyh 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	510 or iyh iy iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	511
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	512 11101011 ex_de_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	513 xchg e l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	514 xchg d h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	515
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	516 00001000 ex_af_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	517 xchg a a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	518 xchg f f'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	519
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	520 11011001 exx
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	521 xchg b b'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	522 xchg c c'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	523 xchg d d'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	524 xchg e e'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	525 xchg h h'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	526 xchg l l'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	527
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	528 11100011 ex_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	529 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	530 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	531 xchg l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	532 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	533 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	534 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	535 add 1 sp wz
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	536 mov wz scratch1
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	537 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	538 xchg h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	539 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	540 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	541 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	542
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	543 10000RRR add_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	544 add a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	545 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	546
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	547 dd 10000100 add_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	548 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	549 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	550 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	551
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	552 dd 10000101 add_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	553 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	554 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	555 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	556
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	557 fd 10000100 add_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	558 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	559 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	560 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	561
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	562 fd 10000101 add_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	563 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	564 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	565 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	566
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	567 10000110 add_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	568 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	569 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	570 update_flags SZYHVXN0C
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	571
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	572 dd 10000110 add_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	573 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	574 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	575 update_flags SZYHVXN0C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	576
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	577 fd 10000110 add_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	578 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	579 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	580 update_flags SZYHVXN0C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	581
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	582 11000110 add_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	583 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	584 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	585 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	586
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	587 z80_add16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	588 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	589 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	590 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	591 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	592 add src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	593 update_flags YHXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	594 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	595 lsr hlt 8 h
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	596
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	597 00001001 add_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	598 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	599 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	600 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	601 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	602 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	603 z80_add16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	604
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	605 00011001 add_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	606 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	607 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	608 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	609 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	610 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	611 z80_add16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	612
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	613 00101001 add_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	614 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	615 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	616 z80_add16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	617
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	618 00111001 add_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	619 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	620 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	621 z80_add16_hl sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	622
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	623 dd 00001001 add_ix_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	624 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	625 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	626 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	627 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	628
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	629 dd 00011001 add_ix_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	630 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	631 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	632 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	633 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	634
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	635 dd 00101001 add_ix_ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	636 add ix ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	637 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	638
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	639 dd 00111001 add_ix_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	640 add sp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	641 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	642
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	643 fd 00001001 add_iy_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	644 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	645 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	646 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	647 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	648
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	649 fd 00011001 add_iy_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	650 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	651 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	652 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	653 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	654
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	655 fd 00101001 add_iy_iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	656 add iy iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	657 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	658
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	659 fd 00111001 add_iy_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	660 add sp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	661 update_flags YHXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	662
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	663 10001RRR adc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	664 adc a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	665 update_flags SZYHVXN0C
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	666
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	667 dd 10001100 adc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	668 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	669 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	670 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	671
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	672 dd 10001101 adc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	673 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	674 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	675 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	676
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	677 fd 10001100 adc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	678 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	679 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	680 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	681
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	682 fd 10001101 adc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	683 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	684 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	685 update_flags SZYHVXN0C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	686
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	687 10001110 adc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	688 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	689 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	690 update_flags SZYHVXN0C
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	691
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	692 dd 10001110 adc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	693 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	694 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	695 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	696
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	697 fd 10001110 adc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	698 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	699 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	700 update_flags SZYHVXN0C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	701
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	702 11001110 adc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	703 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	704 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	705 update_flags SZYHVXN0C
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	706
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	707 z80_adc16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	708 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	709 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	710 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	711 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	712 adc src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	713 update_flags SZYHVXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	714 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	715 lsr hlt 8 h
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	716
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	717 ed 01001010 adc_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	718 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	719 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	720 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	721 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	722 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	723 z80_adc16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	724
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	725 ed 01011010 adc_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	726 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	727 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	728 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	729 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	730 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	731 z80_adc16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	732
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	733 ed 01101010 adc_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	734 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	735 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	736 z80_adc16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	737
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	738
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	739 ed 01111010 adc_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	740 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	741 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1714 diff changeset	742 z80_adc16_hl sp
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	743
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	744 10010RRR sub_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	745 sub main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	746 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	747
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	748 dd 10010100 sub_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	749 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	750 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	751 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	752
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	753 dd 10010101 sub_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	754 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	755 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	756 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	757
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	758 fd 10010100 sub_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	759 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	760 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	761 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	762
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	763 fd 10010101 sub_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	764 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	765 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	766 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	767
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	768 10010110 sub_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	769 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	770 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	771 update_flags SZYHVXN1C
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	772
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	773 dd 10010110 sub_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	774 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	775 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	776 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	777
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	778 fd 10010110 sub_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	779 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	780 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	781 update_flags SZYHVXN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	782
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	783 11010110 sub_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	784 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	785 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	786 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	787
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	788 10011RRR sbc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	789 sbc main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	790 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	791
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	792 dd 10011100 sbc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	793 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	794 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	795 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	796
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	797 dd 10011101 sbc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	798 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	799 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	800 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	801
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	802 fd 10011100 sbc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	803 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	804 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	805 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	806
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	807 fd 10011101 sbc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	808 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	809 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	810 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	811
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	812
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	813 10011110 sbc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	814 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	815 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	816 update_flags SZYHVXN1C
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	817
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	818 dd 10011110 sbc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	819 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	820 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	821 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	822
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	823 fd 10011110 sbc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	824 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	825 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	826 update_flags SZYHVXN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	827
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	828 11011110 sbc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	829 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	830 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	831 update_flags SZYHVXN1C
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	832
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	833 z80_sbc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	834 arg src 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	835 lsl h 8 hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	836 or l hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	837 add 1 hlt wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	838 sbc src hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	839 update_flags SZYHVXN1C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	840 mov hlt l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	841 lsr hlt 8 h
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	842
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	843 ed 01000010 sbc_hl_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	844 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	845 local bcw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	846 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	847 lsl b 8 bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	848 or c bcw bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	849 z80_sbc16_hl bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	850
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	851 ed 01010010 sbc_hl_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	852 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	853 local dew 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	854 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	855 lsl d 8 dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	856 or e dew dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	857 z80_sbc16_hl dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	858
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	859 ed 01100010 sbc_hl_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	860 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	861 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	862 z80_sbc16_hl hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	863
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	864
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	865 ed 01110010 sbc_hl_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	866 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	867 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	868 z80_sbc16_hl sp
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	869
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	870 10100RRR and_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	871 and a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	872 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	873
1720 1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	874 dd 10100100 and_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	875 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	876 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	877 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	878
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	879 dd 10100101 and_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	880 and ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	881 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	882
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	883 fd 10100100 and_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	884 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	885 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	886 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	887
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	888 fd 10100101 and_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	889 and iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	890 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	891
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	892 10100110 and_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	893 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	894 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	895 update_flags SZYH1PXN0C0
1720 1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	896
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	897 dd 10100110 and_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	898 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	899 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	900 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	901
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	902 fd 10100110 and_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	903 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	904 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	905 update_flags SZYH1PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	906
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	907 11100110 and_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	908 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	909 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	910 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	911
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	912 10110RRR or_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	913 or a main.R a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	914 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	915
1720 1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	916 dd 10110100 or_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	917 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	918 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	919 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	920
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	921 dd 10110101 or_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	922 or ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	923 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	924
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	925 fd 10110100 or_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	926 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	927 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	928 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	929
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	930 fd 10110101 or_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	931 or iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	932 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	933
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	934 10110110 or_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	935 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	936 or a scratch1 a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	937 update_flags SZYH0PXN0C0
1720 1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	938
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	939 dd 10110110 or_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	940 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	941 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	942 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	943
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	944 fd 10110110 or_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	945 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	946 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	947 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	948
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	949 11110110 or_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	950 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	951 or a scratch1 a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	952 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	953
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	954 10101RRR xor_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	955 xor a main.R a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	956 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	957
1720 1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	958 dd 10101100 xor_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	959 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	960 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	961 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	962
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	963 dd 10101101 xor_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	964 xor ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	965 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	966
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	967 fd 10101100 xor_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	968 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	969 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	970 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	971
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	972 fd 10101101 xor_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	973 xor iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	974 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	975
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	976 10101110 xor_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	977 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	978 xor a scratch1 a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	979 update_flags SZYH0PXN0C0
1720 1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	980
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	981 dd 10101110 xor_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	982 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	983 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	984 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	985
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	986 fd 10101110 xor_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	987 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	988 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	989 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	990
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	991 11101110 xor_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	992 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	993 xor a scratch1 a
1714 e170a0f75c4f fix half-carry for or and xor in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1712 diff changeset	994 update_flags SZYH0PXN0C0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	995
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	996 10111RRR cp_reg
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	997 mov main.R last_flag_result
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	998 cmp main.R a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	999 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1000
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1001 dd 10111100 cp_ixh
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1002 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1003 lsr ix 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1004 mov tmp last_flag_result
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1005 cmp last_flag_result a
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1006 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1007
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1008 dd 10111101 cp_ixl
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1009 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1010 mov ix tmp
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1011 mov ix last_flag_result
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1012 cmp tmp a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1013 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1014
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1015 fd 10111100 cp_iyh
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1016 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1017 lsr iy 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1018 mov tmp last_flag_result
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1019 cmp tmp a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1020 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1021
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1022 fd 10111101 cp_iyl
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1023 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1024 mov iy tmp
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1025 mov iy last_flag_result
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1026 cmp tmp a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1027 update_flags SZHVN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1028
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1029 10111110 cp_hl
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1030 local tmp 8
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1031 z80_fetch_hl
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1032 mov scratch1 tmp
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1033 mov scratch1 last_flag_result
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1034 cmp tmp a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1035 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1036
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1037 dd 10111110 cp_ixd
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1038 local tmp 8
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1039 z80_fetch_index ix
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1040 mov scratch1 tmp
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1041 mov scratch1 last_flag_result
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1042 cmp tmp a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1043 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1044
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1045 fd 10111110 cp_iyd
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1046 local tmp 8
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1047 z80_fetch_index iy
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1048 mov scratch1 tmp
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1049 mov scratch1 last_flag_result
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1050 cmp tmp a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1051 update_flags SZHVN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1052
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1053 11111110 cp_immed
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1054 local tmp 8
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1055 z80_fetch_immed
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1056 mov scratch1 tmp
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1057 mov scratch1 last_flag_result
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1058 cmp tmp a
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1718 diff changeset	1059 update_flags SZHVN1C
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1060
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1061 00RRR100 inc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1062 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1063 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1064
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1065 dd 00100100 inc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1066 add 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1067 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1068
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1069 dd 00101100 inc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1070 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1071 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1072 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1073 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1074 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1075 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1076
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1077 fd 00100100 inc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1078 add 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1079 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1080
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1081 fd 00101100 inc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1082 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1083 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1084 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1085 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1086 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1087 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1088
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1089 00110100 inc_hl
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1090 local tmp 8
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1091 z80_fetch_hl
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1092 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1093 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1094 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1095 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1096 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1097 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1098 z80_store_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1099
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1100 dd 00110100 inc_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1101 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1102 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1103 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1104 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1105 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1106 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1107 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1108 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1109 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1110 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1111
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1112 fd 00110100 inc_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1113 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1114 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1115 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1116 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1117 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1118 add 1 tmp tmp
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1119 update_flags SZYHVXN0
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1120 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1121 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1122 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1123
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1124 z80_inc_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1125 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1126 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1127 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1128 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1129 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1130 add 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1131 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1132 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1133
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1134 00000011 inc_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1135 z80_inc_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1136
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1137 00010011 inc_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1138 z80_inc_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1139
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1140 00100011 inc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1141 z80_inc_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1142
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1143 00110011 inc_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1144 add 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1145
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1146 dd 00100011 inc_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1147 add 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1148
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1149 fd 00100011 inc_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1150 add 1 iy iy
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1151
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1152 00RRR101 dec_reg
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1153 sub 1 main.R main.R
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1154 update_flags SZYHVXN1
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1155
1718 c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1156 dd 00100101 dec_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1157 sub 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1158 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1159
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1160 dd 00101101 dec_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1161 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1162 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1163 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1164 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1165 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1166 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1167
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1168 fd 00100101 dec_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1169 sub 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1170 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1171
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1172 fd 00101101 dec_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1173 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1174 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1175 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1176 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1177 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1178 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1717 diff changeset	1179
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1180 00110101 dec_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1181 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1182 #TODO: fix size
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1183 sub 1 scratch1 scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1184 update_flags SZYHVXN1
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1185 z80_store_hl
1717 b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1186
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1187 dd 00110101 dec_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1188 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1189 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1190 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1191 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1192 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1193 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1194 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1195 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1196 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1197 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1198
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1199 fd 00110101 dec_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1200 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1201 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1202 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1203 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1204 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1205 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1206 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1207 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1208 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1209 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1210
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1211 z80_dec_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1212 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1213 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1214 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1215 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1216 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1217 sub 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1218 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1219 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1220
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1221 00001011 dec_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1222 z80_dec_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1223
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1224 00011011 dec_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1225 z80_dec_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1226
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1227 00101011 dec16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1228 z80_dec_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1229
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1230 00111011 dec_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1231 sub 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1232
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1233 dd 00101011 dec_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1234 sub 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1235
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1236 fd 00101011 dec_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1237 sub 1 iy iy
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1238
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1239 00101111 cpl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1240 not a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1241 update_flags YH1XN1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1242
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1243 ed 01DDD100 neg
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1244 neg a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1245 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1246
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1247 00111111 ccf
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1248 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1249 and 0x80 chflags chflags
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1250 lsr chflags 4 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1251 or tmp chflags chflags
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1252 xor 0x80 chflags chflags
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1253 update_flags N0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1254
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1255 00110111 scf
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1256 update_flags H0N0C1
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1257
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1258 00000000 nop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1259
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1260 01110110 halt
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1261 sub 1 pc pc
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1262
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1263 11110011 di
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1264 mov 0 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1265 mov 0 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1266 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1267
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1268 11111011 ei
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1269 mov 1 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1270 mov 1 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1271 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1272
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1273 ed 01D00110 im0
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1274 mov 0 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1275
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1276 ed 01D10110 im1
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1277 mov 1 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1278
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1279 ed 01D11110 im2
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1280 mov 2 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1281
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1282 ed 01D01110 im3
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1283 mov 3 imode
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1724 diff changeset	1284
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1285 11000011 jp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1286 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1287 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1288
1726 4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1289 11101001 jp_hl
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1290 lsl h 8 pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1291 or l pc pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1292
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1293 dd 11101001 jp_ix
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1294 mov ix pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1295
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1296 fd 11101001 jp_iy
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1297 mov iy pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1298
1706 c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1299 11CCC010 jp_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1300 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1301 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1302 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1303
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1304 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1305
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1306 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1307
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1308 00011000 jr
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1309 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1310 #TODO: determine if this updates wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1311 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1312 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1313 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1314
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1315 001CC000 jr_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1316 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1317 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1318
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1319 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1320
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1321 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1322 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1323 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1324
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1325 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1326
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1327 00010000 djnz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1328 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1329 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1330 sub 1 b b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1331
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1332 if b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1333
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1334 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1335 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1336 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1337
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1338 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1339
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1340
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1341 11001101 call_uncond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1342 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1343 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1344 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1345 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1346 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1347 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1348 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1349
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1350 11TTT111 rst
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1351 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1352 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1353 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1354 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1355 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1356 lsl T 3 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1357 mov scratch1 pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1358
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1359 11001001 ret
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1360 #TODO: confirm this goes through wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1361 local wzh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1362 meta high wzh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1363 meta low wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1364 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1365 lsl wzh 8 wzh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1366 or wzh wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1367 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1368
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1369 11011011 in_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1370 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1371 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1372 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1373
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1374 ed 01RRR000 in_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1375 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1376 or c scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1377 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1378 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1379
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1380 11010011 out_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1381 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1382 mov scratch1 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1383 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1384 ocall io_write8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1385
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1386 ed 01RRR001 out_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1387 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1388 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1389 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1390 ocall io_write8
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1391
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1392 00000111 rlca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1393 rol a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1394 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1395
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1396 00010111 rla
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1397 rlc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1398 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1399
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1400 00001111 rrca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1401 ror a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1402 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1403
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1404 00011111 rra
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1405 rrc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1406 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1407
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1408 cb 00000RRR rlc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1409 rol main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1410 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1411
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1412 cb 00000110 rlc_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1413 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1414 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1415 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1416 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1417 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1418 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1419 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1420
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1421 z80_rlc_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1422 arg tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1423 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1424 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1425 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1426 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1427 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1428 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1429 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1430 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1431
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1432 ddcb 00000110 rlc_ixd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1433 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1434 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1435
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1436 ddcb 00000RRR rlc_ixd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1437 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1438
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1439 fdcb 00000110 rlc_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1440 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1441 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1442
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1443 fdcb 00000RRR rlc_iyd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1444 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1445
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1446 cb 00010RRR rl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1447 rlc main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1448 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1449
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1450 cb 00010110 rl_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1451 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1452 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1453 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1454 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1455 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1456 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1457 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1458
1722 ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1459 z80_rl_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1460 arg tmp 8
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1461 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1462 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1463 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1464 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1465 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1466 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1467 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1468 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1469
1722 ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1470 ddcb 00010110 rl_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1471 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1472 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1473
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1474 fdcb 00010110 rl_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1475 local tmp 8
1722 ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1476 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1477
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1478
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1479 ddcb 00010RRR rl_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1480 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1481
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1482 fdcb 00010RRR rl_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1483 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1484
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1485 cb 00001RRR rrc
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1486 ror main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1487 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1488
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1489 cb 00001110 rrc_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1490 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1491 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1492 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1493 ror tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1494 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1495 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1496 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1497
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1498 z80_rrc_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1499 arg tmp 8
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1500 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1501 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1502 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1503 mov scratch1 tmp
1722 ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1504 ror tmp 1 tmp
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1505 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1720 diff changeset	1506 mov tmp scratch1
1722 ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1507 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1508
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1509 ddcb 00001110 rrc_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1510 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1511 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1512
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1513 ddcb 00001RRR rrc_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1514 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1515
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1516 fdcb 00001110 rrc_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1517 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1518 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1519
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1520 fdcb 00001RRR rrc_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1521 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1522
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1523 cb 00011RRR rr
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1524 rrc main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1525 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1526
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1527 cb 00011110 rr_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1528 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1529 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1530 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1531 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1532 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1533 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1534 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1535
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1536 z80_rr_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1537 arg tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1538 mov wz scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1539 ocall read_8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1540 cycles 1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1541 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1542 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1543 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1544 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1545 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1546
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1547 ddcb 00011110 rr_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1548 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1549 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1550
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1551 ddcb 00011RRR rr_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1552 z80_rr_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1553
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1554 fdcb 00011110 rr_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1555 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1556 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1557
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	1558 fdcb 00011RRR rr_iyd_reg
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1559 z80_rr_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1560
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1561 cb 00100RRR sla
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1562 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1563 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1564
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1565 cb 00100110 sla_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1566 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1567 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1568 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1569 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1570 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1571 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1572 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1573
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1574 z80_sla_index
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1575 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1576 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1577 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1578 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1579 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1580 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1581 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1582 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1583 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1584
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1585 ddcb 00100110 sla_ixd
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1586 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1587 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1588
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1589 ddcb 00100RRR sla_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1590 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1591
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1592 fdcb 00100110 sla_iyd
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1593 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1594 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1595
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1596 fdcb 00100RRR sla_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1597 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1598
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1599 cb 00101RRR sra
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1600 asr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1601 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1602
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1603 cb 00101110 sra_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1604 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1605 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1606 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1607 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1608 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1609 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1610 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1611
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1612 z80_sra_index
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1613 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1614 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1615 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1616 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1617 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1618 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1619 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1620 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1621 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1622
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1623 ddcb 00101110 sra_ixd
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1624 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1625 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1626
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1627 ddcb 00101RRR sra_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1628 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1629
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1630 fdcb 00101110 sra_iyd
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1631 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1632 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1633
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1634 fdcb 00101RRR sra_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1635 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1636
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1637 cb 00110RRR sll
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1638 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1639 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1640 or 1 main.R main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1641 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1642
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1643 cb 00110110 sll_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1644 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1645 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1646 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1647 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1648 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1649 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1650 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1651 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1652 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1653
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1654 z80_sll_index
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1655 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1656 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1657 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1658 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1659 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1660 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1661 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1662 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1663 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1664 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1665 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1666
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1667 ddcb 00110110 sll_ixd
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1668 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1669 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1670
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1671 ddcb 00110RRR sll_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1672 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1673
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1674 fdcb 00110110 sll_iyd
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1675 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1676 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1677
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1678 fdcb 00110RRR sll_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1679 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1680
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1681 cb 00111RRR srl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1682 lsr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1683 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1684
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1685 cb 00111110 srl_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1686 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1687 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1688 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1689 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1690 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1691 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1692 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1693
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1694 z80_srl_index
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1695 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1696 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1697 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1698 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1699 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1700 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1701 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1702 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1703 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1704
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1705 ddcb 00111110 srl_ixd
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1706 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1707 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1708
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1709 ddcb 00111RRR srl_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1710 z80_srl_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1711
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1712 fdcb 00111110 srl_iyd
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1713 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1714 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1715
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	1716 fdcb 00111RRR srl_iyd_reg
1727 9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1717 z80_srl_index main.R
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1718
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1719 cb 01BBBRRR bit_reg
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1720 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1721 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1722 mov main.R last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1723 and main.R tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1724 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1725
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1726 cb 01BBB110 bit_hl
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1727 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1728 z80_fetch_hl
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1729 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1730 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1731 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1732 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1733
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1734
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1735 ddcb 01BBBRRR bit_ixd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1736 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1737 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1738 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1739 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1740 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1741 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1742 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1743 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1744
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1745 fdcb 01BBBRRR bit_iyd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1746 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1747 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1748 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1749 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1750 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1751 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations Michael Pavone <pavone@retrodev.com> parents: 1726 diff changeset	1752 and scratch1 tmp tmp
1728 b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1753 update_flags SZH1PN0
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1754
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1755 cb 10BBBRRR res_reg
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1756 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1757 lsl 1 B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1758 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1759 and main.R tmp main.R
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1760
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1761 cb 10BBB110 res_hl
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1762 z80_fetch_hl
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1763 cycles 1
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1764 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1765 lsl 1 B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1766 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1767 and scratch1 tmp scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1768 z80_store_hl
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1769
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1770 z80_res_index
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1771 arg bit 8
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1772 arg tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1773 lsl 1 bit tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1774 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1775 mov wz scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1776 ocall read_8
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1777 cycles 1
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1778 and scratch1 tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1779 mov tmp scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1780 z80_store_index
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1781
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1782 ddcb 10BBB110 res_ixd
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1783 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1784 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1785
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1786 ddcb 10BBBRRR res_ixd_reg
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1787 z80_res_index B main.R
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1788
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1789 fdcb 10BBB110 res_iyd
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1790 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1791 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1792
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1727 diff changeset	1793 fdcb 10BBBRRR res_iyd_reg
1729 bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1794 z80_res_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1795
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1796 cb 11BBBRRR set_reg
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1797 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1798 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1799 or main.R tmp main.R
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1800
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1801 cb 11BBB110 set_hl
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1802 z80_fetch_hl
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1803 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1804 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1805 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1806 or scratch1 tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1807 z80_store_hl
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1808
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1809 z80_set_index
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1810 arg bit 8
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1811 arg tmp 8
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1812 lsl 1 bit tmp
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1813 mov wz scratch1
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1814 ocall read_8
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1815 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1816 or scratch1 tmp tmp
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1817 mov tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1818 z80_store_index
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1819
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1820 ddcb 11BBB110 set_ixd
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1821 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1822 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1823
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1824 ddcb 11BBBRRR set_ixd_reg
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1825 z80_set_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1826
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1827 fdcb 11BBB110 set_iyd
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1828 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1829 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1830
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1831 fdcb 11BBBRRR set_iyd_reg
bd13d017f16f Implemented SET instruction in Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1832 z80_set_index B main.R

Mercurial > repos > blastem

annotate z80.cpu @ 1729:bd13d017f16f