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annotate ym2612.c @ 407:c3abc4ada43d
Add support for logging YM2612 channels to WAVE files
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Sun, 16 Jun 2013 17:57:57 -0700 |
| parents | b1bc1947d949 |
| children | baf4688901f2 |
| rev | line source |
|---|---|
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1 #include <string.h> |
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2 #include <math.h> |
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3 #include <stdio.h> |
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4 #include <stdlib.h> |
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5 #include "ym2612.h" |
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6 #include "render.h" |
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7 #include "wave.h" |
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8 |
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9 //#define DO_DEBUG_PRINT |
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10 #ifdef DO_DEBUG_PRINT |
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11 #define dfprintf fprintf |
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12 #define dfopen(var, fname, mode) var=fopen(fname, mode) |
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13 #else |
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14 #define dfprintf |
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15 #define dfopen(var, fname, mode) |
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16 #endif |
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17 |
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18 #define BUSY_CYCLES 17 |
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19 #define OP_UPDATE_PERIOD 144 |
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20 |
| 362 | 21 enum { |
| 22 REG_TIMERA_HIGH = 0x24, | |
| 23 REG_TIMERA_LOW, | |
| 24 REG_TIMERB, | |
| 25 REG_TIME_CTRL, | |
| 26 REG_KEY_ONOFF, | |
| 27 REG_DAC = 0x2A, | |
| 28 REG_DAC_ENABLE, | |
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29 |
| 362 | 30 REG_DETUNE_MULT = 0x30, |
| 31 REG_TOTAL_LEVEL = 0x40, | |
| 32 REG_ATTACK_KS = 0x50, | |
| 33 REG_DECAY_AM = 0x60, | |
| 34 REG_SUSTAIN_RATE = 0x70, | |
| 35 REG_S_LVL_R_RATE = 0x80, | |
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36 |
| 362 | 37 REG_FNUM_LOW = 0xA0, |
| 38 REG_BLOCK_FNUM_H = 0xA4, | |
| 39 REG_FNUM_LOW_CH3 = 0xA8, | |
| 40 REG_BLOCK_FN_CH3 = 0xAC, | |
| 41 REG_ALG_FEEDBACK = 0xB0, | |
| 42 REG_LR_AMS_PMS = 0xB4 | |
| 43 }; | |
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44 |
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45 #define BIT_TIMERA_ENABLE 0x1 |
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46 #define BIT_TIMERB_ENABLE 0x2 |
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47 #define BIT_TIMERA_OVEREN 0x4 |
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48 #define BIT_TIMERB_OVEREN 0x8 |
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49 #define BIT_TIMERA_RESET 0x10 |
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50 #define BIT_TIMERB_RESET 0x20 |
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51 |
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52 #define BIT_STATUS_TIMERA 0x1 |
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53 #define BIT_STATUS_TIMERB 0x2 |
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54 |
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55 enum { |
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56 PHASE_ATTACK, |
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57 PHASE_DECAY, |
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58 PHASE_SUSTAIN, |
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59 PHASE_RELEASE |
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60 }; |
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61 |
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62 uint8_t did_tbl_init = 0; |
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63 //According to Nemesis, real hardware only uses a 256 entry quarter sine table; however, |
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64 //memory is cheap so using a half sine table will probably save some cycles |
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65 //a full sine table would be nice, but negative numbers don't get along with log2 |
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66 #define SINE_TABLE_SIZE 512 |
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67 uint16_t sine_table[SINE_TABLE_SIZE]; |
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68 //Similar deal here with the power table for log -> linear conversion |
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69 //According to Nemesis, real hardware only uses a 256 entry table for the fractional part |
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70 //and uses the whole part as a shift amount. |
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71 #define POW_TABLE_SIZE (1 << 13) |
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72 uint16_t pow_table[POW_TABLE_SIZE]; |
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73 |
| 362 | 74 uint16_t rate_table_base[] = { |
| 75 //main portion | |
| 76 0,1,0,1,0,1,0,1, | |
| 77 0,1,0,1,1,1,0,1, | |
| 78 0,1,1,1,0,1,1,1, | |
| 79 0,1,1,1,1,1,1,1, | |
| 80 //top end | |
| 81 1,1,1,1,1,1,1,1, | |
| 82 1,1,1,2,1,1,1,2, | |
| 83 1,2,1,2,1,2,1,2, | |
| 84 1,2,2,2,1,2,2,2, | |
| 85 }; | |
| 86 | |
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87 uint16_t rate_table[64*8]; |
| 362 | 88 |
| 89 #define MAX_ENVELOPE 0xFFC | |
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90 #define YM_DIVIDER 2 |
| 374 | 91 #define CYCLE_NEVER 0xFFFFFFFF |
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92 |
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93 uint16_t round_fixed_point(double value, int dec_bits) |
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94 { |
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95 return value * (1 << dec_bits) + 0.5; |
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96 } |
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97 |
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98 FILE * debug_file = NULL; |
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99 uint32_t first_key_on=0; |
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100 |
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101 ym2612_context * log_context = NULL; |
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102 |
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103 void ym_finalize_log() |
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104 { |
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105 for (int i = 0; i < NUM_CHANNELS; i++) { |
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106 if (log_context->channels[i].logfile) { |
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107 wave_finalize(log_context->channels[i].logfile); |
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108 } |
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109 } |
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110 } |
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111 |
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112 void ym_init(ym2612_context * context, uint32_t sample_rate, uint32_t master_clock, uint32_t clock_div, uint32_t sample_limit, uint32_t options) |
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113 { |
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114 dfopen(debug_file, "ym_debug.txt", "w"); |
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115 memset(context, 0, sizeof(*context)); |
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116 context->audio_buffer = malloc(sizeof(*context->audio_buffer) * sample_limit*2); |
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117 context->back_buffer = malloc(sizeof(*context->audio_buffer) * sample_limit*2); |
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118 context->buffer_inc = ((double)sample_rate / (double)master_clock) * clock_div * 6; |
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119 context->clock_inc = clock_div * 6; |
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120 context->sample_limit = sample_limit*2; |
| 374 | 121 context->write_cycle = CYCLE_NEVER; |
| 362 | 122 for (int i = 0; i < NUM_OPERATORS; i++) { |
| 123 context->operators[i].envelope = MAX_ENVELOPE; | |
| 124 context->operators[i].env_phase = PHASE_RELEASE; | |
| 125 } | |
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126 //some games seem to expect that the LR flags start out as 1 |
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127 for (int i = 0; i < NUM_CHANNELS; i++) { |
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128 context->channels[i].lr = 0xC0; |
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129 if (options & YM_OPT_WAVE_LOG) { |
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130 char fname[64]; |
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131 sprintf(fname, "ym_channel_%d.wav", i); |
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132 FILE * f = context->channels[i].logfile = fopen(fname, "wb"); |
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133 if (!f) { |
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134 fprintf(stderr, "Failed to open WAVE log file %s for writing\n", fname); |
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135 continue; |
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136 } |
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137 if (!wave_init(f, sample_rate, 16, 1)) { |
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138 fclose(f); |
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139 context->channels[i].logfile = NULL; |
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140 } |
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141 } |
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142 } |
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143 if (options & YM_OPT_WAVE_LOG) { |
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144 log_context = context; |
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145 atexit(ym_finalize_log); |
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146 } |
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147 if (!did_tbl_init) { |
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148 //populate sine table |
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149 for (int32_t i = 0; i < 512; i++) { |
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150 double sine = sin( ((double)(i*2+1) / SINE_TABLE_SIZE) * M_PI_2 ); |
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151 |
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152 //table stores 4.8 fixed pointed representation of the base 2 log |
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153 sine_table[i] = round_fixed_point(-log2(sine), 8); |
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154 } |
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155 //populate power table |
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156 for (int32_t i = 0; i < POW_TABLE_SIZE; i++) { |
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157 double linear = pow(2, -((double)((i & 0xFF)+1) / 256.0)); |
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158 int32_t tmp = round_fixed_point(linear, 11); |
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159 int32_t shift = (i >> 8) - 2; |
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160 if (shift < 0) { |
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161 tmp <<= 0-shift; |
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162 } else { |
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163 tmp >>= shift; |
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164 } |
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165 pow_table[i] = tmp; |
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166 } |
| 362 | 167 //populate envelope generator rate table, from small base table |
| 168 for (int rate = 0; rate < 64; rate++) { | |
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169 for (int cycle = 0; cycle < 8; cycle++) { |
| 362 | 170 uint16_t value; |
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171 if (rate < 2) { |
| 362 | 172 value = 0; |
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173 } else if (rate >= 60) { |
| 362 | 174 value = 8; |
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175 } else if (rate < 8) { |
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176 value = rate_table_base[((rate & 6) == 6 ? 16 : 0) + cycle]; |
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177 } else if (rate < 48) { |
| 362 | 178 value = rate_table_base[(rate & 0x3) * 8 + cycle]; |
| 179 } else { | |
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180 value = rate_table_base[32 + (rate & 0x3) * 8 + cycle] << ((rate - 48) >> 2); |
| 362 | 181 } |
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182 rate_table[rate * 8 + cycle] = value; |
| 362 | 183 } |
| 184 } | |
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185 } |
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186 } |
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187 |
| 377 | 188 #define YM_VOLUME_DIVIDER 2 |
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189 #define YM_MOD_SHIFT 1 |
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190 |
| 403 | 191 #define TIMER_A_MAX 1023 |
| 192 #define TIMER_B_MAX (255*16) | |
| 193 | |
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194 void ym_run(ym2612_context * context, uint32_t to_cycle) |
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195 { |
| 362 | 196 //printf("Running YM2612 from cycle %d to cycle %d\n", context->current_cycle, to_cycle); |
| 197 //TODO: Fix channel update order OR remap channels in register write | |
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198 for (; context->current_cycle < to_cycle; context->current_cycle += context->clock_inc) { |
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199 //Update timers at beginning of 144 cycle period |
| 403 | 200 if (!context->current_op) { |
| 201 if (context->timer_control & BIT_TIMERA_ENABLE) { | |
| 202 if (context->timer_a != TIMER_A_MAX) { | |
| 203 context->timer_a++; | |
| 204 } else { | |
| 205 if (context->timer_control & BIT_TIMERA_OVEREN) { | |
| 206 context->status |= BIT_STATUS_TIMERA; | |
| 207 } | |
| 208 context->timer_a = context->timer_a_load; | |
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209 } |
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210 } |
| 362 | 211 if (context->timer_control & BIT_TIMERB_ENABLE) { |
| 403 | 212 if (context->timer_b != TIMER_B_MAX) { |
| 213 context->timer_b++; | |
| 214 } else { | |
| 215 if (context->timer_control & BIT_TIMERB_OVEREN) { | |
| 216 context->status |= BIT_STATUS_TIMERB; | |
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217 } |
| 403 | 218 context->timer_b = context->timer_b_load; |
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219 } |
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220 } |
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221 } |
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222 //Update Envelope Generator |
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223 if (!(context->current_op % 3)) { |
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224 uint32_t env_cyc = context->env_counter; |
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225 uint32_t op = context->current_env_op; |
| 362 | 226 ym_operator * operator = context->operators + op; |
| 227 ym_channel * channel = context->channels + op/4; | |
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228 uint8_t rate; |
| 362 | 229 for(;;) { |
| 230 rate = operator->rates[operator->env_phase]; | |
| 231 if (rate) { | |
| 232 uint8_t ks = channel->keycode >> operator->key_scaling;; | |
| 233 rate = rate*2 + ks; | |
| 234 if (rate > 63) { | |
| 235 rate = 63; | |
| 236 } | |
| 237 } | |
| 238 //Deal with "infinite" rates | |
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239 //According to Nemesis this should be handled in key-on instead |
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240 if (rate >= 62 && operator->env_phase == PHASE_ATTACK) { |
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241 operator->env_phase = PHASE_DECAY; |
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242 operator->envelope = 0; |
| 362 | 243 } else { |
| 244 break; | |
| 245 } | |
| 246 } | |
| 247 uint32_t cycle_shift = rate < 0x30 ? ((0x2F - rate) >> 2) : 0; | |
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248 if (first_key_on) { |
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249 dfprintf(debug_file, "Operator: %d, env rate: %d (2*%d+%d), env_cyc: %d, cycle_shift: %d, env_cyc & ((1 << cycle_shift) - 1): %d\n", op, rate, operator->rates[operator->env_phase], channel->keycode >> operator->key_scaling,env_cyc, cycle_shift, env_cyc & ((1 << cycle_shift) - 1)); |
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250 } |
| 362 | 251 if (!(env_cyc & ((1 << cycle_shift) - 1))) { |
| 252 uint32_t update_cycle = env_cyc >> cycle_shift & 0x7; | |
| 253 //envelope value is 10-bits, but it will be used as a 4.8 value | |
| 254 uint16_t envelope_inc = rate_table[rate * 8 + update_cycle] << 2; | |
| 255 if (operator->env_phase == PHASE_ATTACK) { | |
| 256 //this can probably be optimized to a single shift rather than a multiply + shift | |
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257 if (first_key_on) { |
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258 dfprintf(debug_file, "Changing op %d envelope %d by %d(%d * %d) in attack phase\n", op, operator->envelope, (~operator->envelope * envelope_inc) >> 4, ~operator->envelope, envelope_inc); |
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259 } |
| 362 | 260 operator->envelope += (~operator->envelope * envelope_inc) >> 4; |
| 261 operator->envelope &= MAX_ENVELOPE; | |
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262 if (!operator->envelope) { |
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263 operator->envelope = 0; |
| 362 | 264 operator->env_phase = PHASE_DECAY; |
| 265 } | |
| 266 } else { | |
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267 if (first_key_on) { |
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268 dfprintf(debug_file, "Changing op %d envelope %d by %d in %s phase\n", op, operator->envelope, envelope_inc, |
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269 operator->env_phase == PHASE_SUSTAIN ? "sustain" : (operator->env_phase == PHASE_DECAY ? "decay": "release")); |
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270 } |
| 362 | 271 operator->envelope += envelope_inc; |
| 272 //clamp to max attenuation value | |
| 273 if (operator->envelope > MAX_ENVELOPE) { | |
| 274 operator->envelope = MAX_ENVELOPE; | |
| 275 } | |
| 276 if (operator->env_phase == PHASE_DECAY && operator->envelope >= operator->sustain_level) { | |
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277 //operator->envelope = operator->sustain_level; |
| 362 | 278 operator->env_phase = PHASE_SUSTAIN; |
| 279 } | |
| 280 } | |
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281 } |
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282 context->current_env_op++; |
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283 if (context->current_env_op == NUM_OPERATORS) { |
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284 context->current_env_op = 0; |
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285 context->env_counter++; |
| 362 | 286 } |
| 287 } | |
| 288 | |
| 289 //Update Phase Generator | |
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290 uint32_t channel = context->current_op / 4; |
| 362 | 291 if (channel != 5 || !context->dac_enable) { |
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292 uint32_t op = context->current_op; |
| 362 | 293 //printf("updating operator %d of channel %d\n", op, channel); |
| 294 ym_operator * operator = context->operators + op; | |
| 295 ym_channel * chan = context->channels + channel; | |
| 296 //TODO: Modulate phase by LFO if necessary | |
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297 uint16_t phase = operator->phase_counter >> 10 & 0x3FF; |
| 362 | 298 operator->phase_counter += operator->phase_inc; |
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299 int16_t mod = 0; |
| 362 | 300 switch (op % 4) |
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301 { |
| 362 | 302 case 0://Operator 1 |
| 377 | 303 if (chan->feedback) { |
|
378
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304 mod = operator->output >> (9-chan->feedback); |
| 377 | 305 } |
|
359
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306 break; |
| 362 | 307 case 1://Operator 3 |
| 308 switch(chan->algorithm) | |
| 309 { | |
| 310 case 0: | |
| 311 case 2: | |
| 312 //modulate by operator 2 | |
|
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313 mod = context->operators[op+1].output >> YM_MOD_SHIFT; |
| 362 | 314 break; |
| 315 case 1: | |
| 316 //modulate by operator 1+2 | |
|
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317 mod = (context->operators[op-1].output + context->operators[op+1].output) >> YM_MOD_SHIFT; |
| 362 | 318 break; |
| 319 case 5: | |
| 320 //modulate by operator 1 | |
|
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321 mod = context->operators[op-1].output >> YM_MOD_SHIFT; |
| 362 | 322 } |
| 323 break; | |
| 324 case 2://Operator 2 | |
|
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325 if (chan->algorithm != 1 && chan->algorithm != 2 && chan->algorithm != 7) { |
| 362 | 326 //modulate by Operator 1 |
|
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327 mod = context->operators[op-2].output >> YM_MOD_SHIFT; |
| 362 | 328 } |
|
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329 break; |
| 362 | 330 case 3://Operator 4 |
| 331 switch(chan->algorithm) | |
| 332 { | |
| 333 case 0: | |
| 334 case 1: | |
| 335 case 4: | |
| 336 //modulate by operator 3 | |
|
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337 mod = context->operators[op-2].output >> YM_MOD_SHIFT; |
| 362 | 338 break; |
| 339 case 2: | |
| 340 //modulate by operator 1+3 | |
|
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341 mod = (context->operators[op-3].output + context->operators[op-2].output) >> YM_MOD_SHIFT; |
| 362 | 342 break; |
| 343 case 3: | |
| 344 //modulate by operator 2+3 | |
|
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345 mod = (context->operators[op-1].output + context->operators[op-2].output) >> YM_MOD_SHIFT; |
| 362 | 346 break; |
| 347 case 5: | |
| 348 //modulate by operator 1 | |
|
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349 mod = context->operators[op-3].output >> YM_MOD_SHIFT; |
| 362 | 350 break; |
| 351 } | |
|
359
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352 break; |
|
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353 } |
|
370
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354 uint16_t env = operator->envelope + operator->total_level; |
|
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355 if (env > MAX_ENVELOPE) { |
|
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356 env = MAX_ENVELOPE; |
|
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|
357 } |
|
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|
358 if (first_key_on) { |
|
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359 dfprintf(debug_file, "op %d, base phase: %d, mod: %d, sine: %d, out: %d\n", op, phase, mod, sine_table[(phase+mod) & 0x1FF], pow_table[sine_table[phase & 0x1FF] + env]); |
|
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|
360 } |
|
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Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
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|
361 phase += mod; |
|
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|
362 |
|
371
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363 int16_t output = pow_table[sine_table[phase & 0x1FF] + env]; |
|
359
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364 if (phase & 0x200) { |
|
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365 output = -output; |
|
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366 } |
| 362 | 367 operator->output = output; |
|
359
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368 //Update the channel output if we've updated all operators |
|
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369 if (op % 4 == 3) { |
| 362 | 370 if (chan->algorithm < 4) { |
| 371 chan->output = operator->output; | |
| 372 } else if(chan->algorithm == 4) { | |
|
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373 chan->output = operator->output + context->operators[channel * 4 + 2].output; |
|
359
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374 } else { |
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375 output = 0; |
| 362 | 376 for (uint32_t op = ((chan->algorithm == 7) ? 0 : 1) + channel*4; op < (channel+1)*4; op++) { |
| 377 output += context->operators[op].output; | |
|
359
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378 } |
| 362 | 379 chan->output = output; |
|
359
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380 } |
|
370
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381 if (first_key_on) { |
|
371
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382 int16_t value = context->channels[channel].output & 0x3FE0; |
|
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383 if (value & 0x2000) { |
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384 value |= 0xC000; |
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385 } |
|
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386 dfprintf(debug_file, "channel %d output: %d\n", channel, value / YM_VOLUME_DIVIDER); |
|
370
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|
387 } |
|
359
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388 } |
| 362 | 389 //puts("operator update done"); |
|
359
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390 } |
|
364
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|
391 context->current_op++; |
|
380
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392 context->buffer_fraction += context->buffer_inc; |
|
396
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393 if (context->current_op == NUM_OPERATORS) { |
|
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|
394 context->current_op = 0; |
|
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|
395 if (context->buffer_fraction > 1.0) { |
|
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|
396 context->buffer_fraction -= 1.0; |
|
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|
397 context->audio_buffer[context->buffer_pos] = 0; |
|
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|
398 context->audio_buffer[context->buffer_pos + 1] = 0; |
|
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|
399 for (int i = 0; i < NUM_CHANNELS; i++) { |
|
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|
400 int16_t value = context->channels[i].output & 0x3FE0; |
|
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|
401 if (value & 0x2000) { |
|
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|
402 value |= 0xC000; |
|
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|
403 } |
|
407
c3abc4ada43d
Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents:
406
diff
changeset
|
404 if (context->channels[i].logfile) { |
|
c3abc4ada43d
Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
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406
diff
changeset
|
405 fwrite(&value, sizeof(value), 1, context->channels[i].logfile); |
|
c3abc4ada43d
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406
diff
changeset
|
406 } |
|
396
09328dbe6700
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386
diff
changeset
|
407 if (context->channels[i].lr & 0x80) { |
|
09328dbe6700
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386
diff
changeset
|
408 context->audio_buffer[context->buffer_pos] += value / YM_VOLUME_DIVIDER; |
|
09328dbe6700
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|
409 } |
|
09328dbe6700
Fix output of algorithm 4 and make some other minor YM2612 core improvements
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386
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changeset
|
410 if (context->channels[i].lr & 0x40) { |
|
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changeset
|
411 context->audio_buffer[context->buffer_pos+1] += value / YM_VOLUME_DIVIDER; |
|
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|
412 } |
|
380
1c8d74f2ab0b
Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
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|
413 } |
|
396
09328dbe6700
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changeset
|
414 context->buffer_pos += 2; |
|
09328dbe6700
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386
diff
changeset
|
415 if (context->buffer_pos == context->sample_limit) { |
|
09328dbe6700
Fix output of algorithm 4 and make some other minor YM2612 core improvements
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386
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changeset
|
416 render_wait_ym(context); |
|
380
1c8d74f2ab0b
Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
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|
417 } |
|
1c8d74f2ab0b
Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
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|
418 } |
|
364
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|
419 } |
|
288
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Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
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changeset
|
420 } |
|
380
1c8d74f2ab0b
Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
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|
421 if (context->current_cycle >= context->write_cycle + (BUSY_CYCLES * context->clock_inc / 6)) { |
|
288
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|
422 context->status &= 0x7F; |
| 374 | 423 context->write_cycle = CYCLE_NEVER; |
|
288
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|
424 } |
| 362 | 425 //printf("Done running YM2612 at cycle %d\n", context->current_cycle, to_cycle); |
|
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|
426 } |
|
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|
427 |
|
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|
428 void ym_address_write_part1(ym2612_context * context, uint8_t address) |
|
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|
429 { |
|
364
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|
430 //printf("address_write_part1: %X\n", address); |
| 362 | 431 context->selected_reg = address; |
| 432 context->selected_part = 0; | |
|
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|
433 } |
|
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|
434 |
|
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|
435 void ym_address_write_part2(ym2612_context * context, uint8_t address) |
|
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|
436 { |
|
364
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changeset
|
437 //printf("address_write_part2: %X\n", address); |
| 362 | 438 context->selected_reg = address; |
| 439 context->selected_part = 1; | |
| 440 } | |
| 441 | |
| 442 uint8_t fnum_to_keycode[] = { | |
| 443 //F11 = 0 | |
| 444 0,0,0,0,0,0,0,1, | |
| 445 //F11 = 1 | |
| 446 2,3,3,3,3,3,3,3 | |
| 447 }; | |
| 448 | |
| 449 //table courtesy of Nemesis | |
| 450 uint32_t detune_table[][4] = { | |
| 451 {0, 0, 1, 2}, //0 (0x00) | |
| 452 {0, 0, 1, 2}, //1 (0x01) | |
| 453 {0, 0, 1, 2}, //2 (0x02) | |
| 454 {0, 0, 1, 2}, //3 (0x03) | |
| 455 {0, 1, 2, 2}, //4 (0x04) | |
| 456 {0, 1, 2, 3}, //5 (0x05) | |
| 457 {0, 1, 2, 3}, //6 (0x06) | |
| 458 {0, 1, 2, 3}, //7 (0x07) | |
| 459 {0, 1, 2, 4}, //8 (0x08) | |
| 460 {0, 1, 3, 4}, //9 (0x09) | |
| 461 {0, 1, 3, 4}, //10 (0x0A) | |
| 462 {0, 1, 3, 5}, //11 (0x0B) | |
| 463 {0, 2, 4, 5}, //12 (0x0C) | |
| 464 {0, 2, 4, 6}, //13 (0x0D) | |
| 465 {0, 2, 4, 6}, //14 (0x0E) | |
| 466 {0, 2, 5, 7}, //15 (0x0F) | |
| 467 {0, 2, 5, 8}, //16 (0x10) | |
| 468 {0, 3, 6, 8}, //17 (0x11) | |
| 469 {0, 3, 6, 9}, //18 (0x12) | |
| 470 {0, 3, 7,10}, //19 (0x13) | |
| 471 {0, 4, 8,11}, //20 (0x14) | |
| 472 {0, 4, 8,12}, //21 (0x15) | |
| 473 {0, 4, 9,13}, //22 (0x16) | |
| 474 {0, 5,10,14}, //23 (0x17) | |
| 475 {0, 5,11,16}, //24 (0x18) | |
| 476 {0, 6,12,17}, //25 (0x19) | |
| 477 {0, 6,13,19}, //26 (0x1A) | |
| 478 {0, 7,14,20}, //27 (0x1B) | |
| 479 {0, 8,16,22}, //28 (0x1C) | |
| 480 {0, 8,16,22}, //29 (0x1D) | |
| 481 {0, 8,16,22}, //30 (0x1E) | |
| 482 {0, 8,16,22} | |
| 483 }; //31 (0x1F) | |
| 484 | |
| 485 void ym_update_phase_inc(ym2612_context * context, ym_operator * operator, uint32_t op) | |
| 486 { | |
| 487 uint32_t chan_num = op / 4; | |
| 488 //printf("ym_update_phase_inc | channel: %d, op: %d\n", chan_num, op); | |
| 489 //base frequency | |
| 490 ym_channel * channel = context->channels + chan_num; | |
|
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491 uint32_t inc, detune; |
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492 if (chan_num == 2 && context->ch3_mode && (op < (2*4 + 3))) { |
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493 inc = context->ch3_supp[op-2*4].fnum; |
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494 if (!context->ch3_supp[op-2*4].block) { |
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495 inc >>= 1; |
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496 } else { |
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497 inc <<= (context->ch3_supp[op-2*4].block-1); |
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498 } |
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499 //detune |
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500 detune = detune_table[context->ch3_supp[op-2*4].keycode][operator->detune & 0x3]; |
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501 } else { |
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502 inc = channel->fnum; |
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503 if (!channel->block) { |
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504 inc >>= 1; |
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505 } else { |
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506 inc <<= (channel->block-1); |
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507 } |
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508 //detune |
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509 detune = detune_table[channel->keycode][operator->detune & 0x3]; |
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510 } |
| 362 | 511 if (operator->detune & 0x40) { |
| 512 inc -= detune; | |
| 513 //this can underflow, mask to 17-bit result | |
| 514 inc &= 0x1FFFF; | |
| 515 } else { | |
| 516 inc += detune; | |
| 517 } | |
| 518 //multiple | |
| 519 if (operator->multiple) { | |
| 520 inc *= operator->multiple; | |
| 521 } else { | |
| 522 //0.5 | |
| 523 inc >>= 1; | |
|
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524 } |
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525 //printf("phase_inc for operator %d: %d, block: %d, fnum: %d, detune: %d, multiple: %d\n", op, inc, channel->block, channel->fnum, detune, operator->multiple); |
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526 operator->phase_inc = inc; |
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527 } |
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528 |
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529 void ym_data_write(ym2612_context * context, uint8_t value) |
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530 { |
| 362 | 531 if (context->selected_reg < 0x21 || context->selected_reg > 0xB6 || (context->selected_reg < 0x30 && context->selected_part)) { |
| 532 return; | |
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533 } |
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534 dfprintf(debug_file, "write of %X to reg %X in part %d\n", value, context->selected_reg, context->selected_part+1); |
| 362 | 535 if (context->selected_reg < 0x30) { |
| 536 //Shared regs | |
| 537 switch (context->selected_reg) | |
| 538 { | |
| 539 //TODO: Test reg and LFO | |
| 540 case REG_TIMERA_HIGH: | |
| 541 context->timer_a_load &= 0x3; | |
| 542 context->timer_a_load |= value << 2; | |
| 543 break; | |
| 544 case REG_TIMERA_LOW: | |
| 545 context->timer_a_load &= 0xFFFC; | |
| 546 context->timer_a_load |= value & 0x3; | |
| 547 break; | |
| 548 case REG_TIMERB: | |
| 403 | 549 context->timer_b_load = value * 16; |
| 362 | 550 break; |
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551 case REG_TIME_CTRL: { |
| 403 | 552 if (value & BIT_TIMERA_ENABLE && !(context->timer_control & BIT_TIMERA_ENABLE)) { |
| 553 context->timer_a = context->timer_a_load; | |
| 554 } | |
| 555 if (value & BIT_TIMERB_ENABLE && !(context->timer_control & BIT_TIMERB_ENABLE)) { | |
| 556 context->timer_b = context->timer_b_load; | |
| 557 } | |
| 558 context->timer_control = value & 0xF; | |
| 559 if (value & BIT_TIMERA_RESET) { | |
| 560 context->status &= ~BIT_STATUS_TIMERA; | |
| 561 } | |
| 562 if (value & BIT_TIMERB_RESET) { | |
| 563 context->status &= ~BIT_STATUS_TIMERB; | |
| 564 } | |
|
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565 uint8_t old_mode = context->ch3_mode; |
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566 context->ch3_mode = value & 0xC0; |
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567 if (context->ch3_mode != old_mode) { |
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568 ym_update_phase_inc(context, context->operators + 2*4, 2*4); |
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569 ym_update_phase_inc(context, context->operators + 2*4+1, 2*4+1); |
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570 ym_update_phase_inc(context, context->operators + 2*4+2, 2*4+2); |
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571 } |
| 362 | 572 break; |
|
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573 } |
| 362 | 574 case REG_KEY_ONOFF: { |
| 575 uint8_t channel = value & 0x7; | |
|
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576 if (channel != 3 && channel != 7) { |
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577 if (channel > 2) { |
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578 channel--; |
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579 } |
| 362 | 580 for (uint8_t op = channel * 4, bit = 0x10; op < (channel + 1) * 4; op++, bit <<= 1) { |
| 581 if (value & bit) { | |
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582 first_key_on = 1; |
| 362 | 583 //printf("Key On for operator %d in channel %d\n", op, channel); |
| 584 context->operators[op].phase_counter = 0; | |
| 585 context->operators[op].env_phase = PHASE_ATTACK; | |
| 586 context->operators[op].envelope = MAX_ENVELOPE; | |
| 587 } else { | |
| 588 //printf("Key Off for operator %d in channel %d\n", op, channel); | |
| 589 context->operators[op].env_phase = PHASE_RELEASE; | |
| 590 } | |
| 591 } | |
| 592 } | |
| 593 break; | |
| 594 } | |
| 595 case REG_DAC: | |
| 596 if (context->dac_enable) { | |
| 597 context->channels[5].output = (((int16_t)value) - 0x80) << 6; | |
|
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598 //printf("DAC Write %X(%d) @ %d\n", value, context->channels[5].output, context->current_cycle); |
| 362 | 599 } |
| 600 break; | |
| 601 case REG_DAC_ENABLE: | |
|
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602 //printf("DAC Enable: %X\n", value); |
| 362 | 603 context->dac_enable = value & 0x80; |
| 604 break; | |
| 605 } | |
| 606 } else if (context->selected_reg < 0xA0) { | |
| 607 //part | |
| 608 uint8_t op = context->selected_part ? (NUM_OPERATORS/2) : 0; | |
| 609 //channel in part | |
| 610 if ((context->selected_reg & 0x3) != 0x3) { | |
|
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611 op += 4 * (context->selected_reg & 0x3) + ((context->selected_reg & 0xC) / 4); |
| 362 | 612 //printf("write targets operator %d (%d of channel %d)\n", op, op % 4, op / 4); |
| 613 ym_operator * operator = context->operators + op; | |
| 614 switch (context->selected_reg & 0xF0) | |
| 615 { | |
| 616 case REG_DETUNE_MULT: | |
| 617 operator->detune = value >> 4 & 0x7; | |
| 618 operator->multiple = value & 0xF; | |
| 619 ym_update_phase_inc(context, operator, op); | |
| 620 break; | |
| 621 case REG_TOTAL_LEVEL: | |
| 622 operator->total_level = (value & 0x7F) << 5; | |
| 623 break; | |
| 624 case REG_ATTACK_KS: | |
| 376 | 625 operator->key_scaling = 3 - (value >> 6); |
| 362 | 626 operator->rates[PHASE_ATTACK] = value & 0x1F; |
| 627 break; | |
| 628 case REG_DECAY_AM: | |
| 629 //TODO: AM flag for LFO | |
| 630 operator->rates[PHASE_DECAY] = value & 0x1F; | |
| 631 break; | |
| 632 case REG_SUSTAIN_RATE: | |
| 633 operator->rates[PHASE_SUSTAIN] = value & 0x1F; | |
| 634 break; | |
| 635 case REG_S_LVL_R_RATE: | |
| 636 operator->rates[PHASE_RELEASE] = (value & 0xF) << 1 | 1; | |
|
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637 operator->sustain_level = (value & 0xF0) << 4; |
| 362 | 638 break; |
| 639 } | |
| 640 } | |
| 641 } else { | |
| 642 uint8_t channel = context->selected_reg & 0x3; | |
| 643 if (channel != 3) { | |
| 644 if (context->selected_part) { | |
| 645 channel += 3; | |
| 646 } | |
| 647 //printf("write targets channel %d\n", channel); | |
| 648 switch (context->selected_reg & 0xFC) | |
| 649 { | |
| 650 case REG_FNUM_LOW: | |
| 651 context->channels[channel].block = context->channels[channel].block_fnum_latch >> 3 & 0x7; | |
| 652 context->channels[channel].fnum = (context->channels[channel].block_fnum_latch & 0x7) << 8 | value; | |
| 653 context->channels[channel].keycode = context->channels[channel].block << 2 | fnum_to_keycode[context->channels[channel].fnum >> 7]; | |
| 654 ym_update_phase_inc(context, context->operators + channel*4, channel*4); | |
| 655 ym_update_phase_inc(context, context->operators + channel*4+1, channel*4+1); | |
| 656 ym_update_phase_inc(context, context->operators + channel*4+2, channel*4+2); | |
| 657 ym_update_phase_inc(context, context->operators + channel*4+3, channel*4+3); | |
| 658 break; | |
| 659 case REG_BLOCK_FNUM_H:{ | |
| 660 context->channels[channel].block_fnum_latch = value; | |
| 661 break; | |
| 662 } | |
|
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663 case REG_FNUM_LOW_CH3: |
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664 if (channel < 3) { |
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665 context->ch3_supp[channel].block = context->ch3_supp[channel].block_fnum_latch >> 3 & 0x7; |
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666 context->ch3_supp[channel].fnum = (context->ch3_supp[channel].block_fnum_latch & 0x7) << 8 | value; |
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667 context->ch3_supp[channel].keycode = context->ch3_supp[channel].block << 2 | fnum_to_keycode[context->ch3_supp[channel].fnum >> 7]; |
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668 if (context->ch3_mode) { |
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669 ym_update_phase_inc(context, context->operators + 2*4 + channel, 2*4); |
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670 } |
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671 } |
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672 break; |
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673 case REG_BLOCK_FN_CH3: |
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674 if (channel < 3) { |
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675 context->ch3_supp[channel].block_fnum_latch = value; |
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676 } |
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677 break; |
| 362 | 678 case REG_ALG_FEEDBACK: |
| 679 context->channels[channel].algorithm = value & 0x7; | |
| 680 context->channels[channel].feedback = value >> 3 & 0x7; | |
| 681 break; | |
| 682 case REG_LR_AMS_PMS: | |
| 683 context->channels[channel].pms = value & 0x7; | |
| 684 context->channels[channel].ams = value >> 4 & 0x3; | |
| 685 context->channels[channel].lr = value & 0xC0; | |
|
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686 //printf("Write of %X to LR_AMS_PMS reg for channel %d\n", value, channel); |
| 362 | 687 break; |
| 688 } | |
| 689 } | |
| 690 } | |
| 691 | |
| 692 context->write_cycle = context->current_cycle; | |
| 374 | 693 context->status |= 0x80; |
|
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694 } |
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695 |
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696 uint8_t ym_read_status(ym2612_context * context) |
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697 { |
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698 return context->status; |
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699 } |
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a8ee7934a1f8
Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
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