repos/blastem: m68k_to_x86.c annotate

annotate m68k_to_x86.c @ 97:c7185fd840fc

Fix address register indexed addressing (probably)

author	Mike Pavone <pavone@retrodev.com>
date	Thu, 27 Dec 2012 21:32:00 -0800
parents	f894f85cf39d
children	104e257fb93c

rev	line source
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "m68k_to_x86.h"
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3 #include "mem.h"
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4 #include <stdio.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	5 #include <stddef.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	6 #include <stdlib.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	7 #include <string.h>
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	8
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #define BUS 4
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	10 #define PREDEC_PENALTY 2
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define CYCLES RAX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 #define LIMIT RBP
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	13 #define SCRATCH1 RCX
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	14 #define SCRATCH2 RDI
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define CONTEXT RSI
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	16
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define FLAG_N RBX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define FLAG_V BH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define FLAG_Z RDX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define FLAG_C DH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	21
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 typedef struct {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 int32_t disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 uint8_t mode;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 uint8_t base;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 uint8_t index;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 uint8_t cycles;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 } x86_ea;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	29
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	30 void handle_cycle_limit_int();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	31 void m68k_read_word_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	32 void m68k_read_long_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	33 void m68k_read_byte_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	34 void m68k_write_word();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	35 void m68k_write_long_lowfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	36 void m68k_write_long_highfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	37 void m68k_write_byte();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	38 void m68k_save_context();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	39 void m68k_modified_ret_addr();
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	40 void m68k_native_addr();
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	41 void m68k_native_addr_and_sync();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	42 void set_sr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	43 void set_ccr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	44 void get_sr();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	45 void m68k_start_context(uint8_t * addr, m68k_context * context);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	46
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 uint8_t * cycles(uint8_t * dst, uint32_t num)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	49 dst = add_ir(dst, num, CYCLES, SZ_D);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	51
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	52 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	53 {
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	54 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	55 uint8_t * jmp_off = dst+1;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	56 dst = jcc(dst, CC_NC, dst + 7);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	57 dst = mov_ir(dst, address, SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	58 dst = call(dst, (uint8_t *)handle_cycle_limit_int);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	59 *jmp_off = dst - (jmp_off+1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	60 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	61 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	62
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	65 if (op->addr_mode == MODE_REG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 return opts->dregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 if (op->addr_mode == MODE_AREG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 return opts->aregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 return -1;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	73
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	74 //must be called with an m68k_op_info that uses a register
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	75 size_t reg_offset(m68k_op_info *op)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	76 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	77 if (op->addr_mode == MODE_REG) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	78 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	79 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	80 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	81 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	82
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	83 void print_regs_exit(m68k_context * context)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	84 {
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	85 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	86 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	87 printf("d%d: %X\n", i, context->dregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	88 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	89 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	90 printf("a%d: %X\n", i, context->aregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	91 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	92 exit(0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	93 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	94
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	95 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	96 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	97 int8_t reg = native_reg(&(inst->src), opts);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	98 uint8_t sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	99 int32_t dec_amount,inc_amount;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 if (reg >= 0) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	101 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	102 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	103 return out;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	105 switch (inst->src.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	106 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	107 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	108 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	109 //We only get one memory parameter, so if the dst operand is a register in memory,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	110 //we need to copy this to a temp register first
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	111 reg = native_reg(&(inst->dst), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	112 if (reg >= 0 \|\| inst->dst.addr_mode == MODE_UNUSED \|\| (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode == MODE_AREG)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	113 \|\| inst->op == M68K_EXG) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	114
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	115 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	116 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	117 ea->disp = reg_offset(&(inst->src));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	118 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	119 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	120 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	121 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	122 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	123 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	124 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	125 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	126 out = cycles(out, PREDEC_PENALTY);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	127 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	128 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	129 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	130 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	131 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	132 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	133 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	134 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	135 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	136 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	137 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	138 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	139 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	140 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	141 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	142 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	143 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	144 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	145 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	146 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	147 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	148 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	149 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	150 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	151
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	152 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	153 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	154 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	155 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	156 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	157 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	158 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	159 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	160 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	161 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	162 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	163 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	164 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	165 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	166 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	167 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	168 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	169 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	170 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	171 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	172 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	173 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	174 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	175 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	176 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	177 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	178 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	179 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	180 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	181 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	182 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	183 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	184 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	185 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	186 case MODE_AREG_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	187 out = cycles(out, 6);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	188 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	189 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	190 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	191 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	192 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	193 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	194 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	195 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	196 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	197 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	198 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	199 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	200 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	201 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	202 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	203 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	204 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	205 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	206 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	207 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	208 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	209 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	210 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	211 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	212 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	213 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	214 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	215 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	216 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	217 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	218 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	219 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	220 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	221 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	222 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	223 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	224 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	225 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	226 }
97 c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	227 switch (inst->extra.size)
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	228 {
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	229 case OPSIZE_BYTE:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	230 out = call(out, (char *)m68k_read_byte_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	231 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	232 case OPSIZE_WORD:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	233 out = call(out, (char *)m68k_read_word_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	234 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	235 case OPSIZE_LONG:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	236 out = call(out, (char *)m68k_read_long_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	237 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	238 }
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	239 ea->mode = MODE_REG_DIRECT;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	240 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	241 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	242 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	243 out = cycles(out, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	244 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	245 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	246 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	247 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	248 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	249 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	250 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	251 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	252 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	253 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	254 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	255 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	256 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	257 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	258 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	259 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	260 case MODE_PC_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	261 out = cycles(out, 6);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	262 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	263 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	264 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	265 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	266 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	267 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	268 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	269 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	270 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	271 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	272 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	273 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	274 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	275 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	276 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	277 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	278 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	279 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	280 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	281 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	282 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	283 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	284 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	285 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	286 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	287 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	288 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	289 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	290 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	291 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	292 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	293 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	294 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	295 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	296 }
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	297 switch (inst->extra.size)
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	298 {
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	299 case OPSIZE_BYTE:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	300 out = call(out, (char *)m68k_read_byte_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	301 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	302 case OPSIZE_WORD:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	303 out = call(out, (char *)m68k_read_word_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	304 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	305 case OPSIZE_LONG:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	306 out = call(out, (char *)m68k_read_long_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	307 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	308 }
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	309 ea->mode = MODE_REG_DIRECT;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	310 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	311 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	312 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	313 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	314 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	315 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	316 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	317 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	318 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	319 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	320 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	321 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	322 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	323 out = call(out, (char *)m68k_read_byte_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	324 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	325 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	326 out = call(out, (char *)m68k_read_word_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	327 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	328 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	329 out = call(out, (char *)m68k_read_long_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	330 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	331 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	332 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	333 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	334 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	335 case MODE_IMMEDIATE:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	336 case MODE_IMMEDIATE_WORD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	337 if (inst->variant != VAR_QUICK) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	338 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	339 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	340 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	341 ea->disp = inst->src.params.immed;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	342 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	343 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	344 printf("address mode %d not implemented (src)\n", inst->src.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	345 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	346 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	347 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	348 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	349
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	350 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	351 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	352 int8_t reg = native_reg(&(inst->dst), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	353 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	354 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	355 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	356 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	357 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	358 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	359 switch (inst->dst.addr_mode)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	360 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	361 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	362 case MODE_AREG:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	363 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	364 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	365 ea->disp = reg_offset(&(inst->dst));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	366 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	367 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	368 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	369 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	370 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	371 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	372 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	373 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	374 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	375 case MODE_AREG_POSTINC:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	376 if (fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	377 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	378 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	379 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	380 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	381 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	382 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	383 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	384 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	385 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	386 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	387 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	388 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	389 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	390 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	391 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	392 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	393 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	394 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	395 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	396 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	397 //save reg value in SCRATCH2 so we can use it to save the result in memory later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	398 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	399 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	400 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	401 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	402 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	403
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	404 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	405 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	406 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	407 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	408 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	409 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	410 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	411 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	412 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	413 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	414 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	415 case MODE_AREG_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	416 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	417 reg = fake_read ? SCRATCH2 : SCRATCH1;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	418 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	419 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	420 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	421 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	422 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	423 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	424 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	425 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	426 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	427 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	428 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	429 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	430 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	431 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	432 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	433 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	434 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	435 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	436 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	437 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	438 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	439 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	440 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	441 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	442 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	443 case MODE_PC_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	444 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	445 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	446 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	447 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	448 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	449 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	450 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	451 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	452 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	453 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	454 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	455 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	456 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	457 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	458 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	459 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	460 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	461 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	462 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	463 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	464 break;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	465 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	466 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	467 //Add cycles for reading address from instruction stream
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	468 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS2 : BUS) : 0));
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	469 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	470 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	471 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	472 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	473 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	474 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	475 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	476 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	477 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	478 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	479 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	480 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	481 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	482 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	483 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	484 out = pop_r(out, SCRATCH2);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	485 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	486 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	487 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	488 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	489 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	490 printf("address mode %d not implemented (dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	491 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	492 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	493 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	494 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	495
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	496 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	497 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	498 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	499 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	500 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	501 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	502 out = call(out, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	503 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	504 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	505 out = call(out, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	506 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	507 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	508 out = call(out, (char *)m68k_write_long_lowfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	509 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	510 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	511 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	512 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	513 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	514
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	515 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	516 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	517 address &= 0xFFFFFF;
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	518 if (address > 0x400000) {
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	519 printf("get_native_address: %X\n", address);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	520 }
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	521 address /= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	522 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	523 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	524 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	525 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	526 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	527 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	528 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	529 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	530 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	531 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	532
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	533 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	534 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	535 deferred_addr * new_head = malloc(sizeof(deferred_addr));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	536 new_head->next = old_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	537 new_head->address = address & 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	538 new_head->dest = dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	539 return new_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	540 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	541
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	542 void process_deferred(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	543 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	544 deferred_addr * cur = opts->deferred;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	545 deferred_addr **last_next = &(opts->deferred);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	546 while(cur)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	547 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	548 uint8_t * native = get_native_address(opts->native_code_map, cur->address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	549 if (native) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	550 int32_t disp = native - (cur->dest + 4);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	551 uint8_t * out = cur->dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	552 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	553 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	554 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	555 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	556 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	557 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	558 *out = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	559 *last_next = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	560 free(cur);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	561 cur = *last_next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	562 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	563 last_next = &(cur->next);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	564 cur = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	565 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	566 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	567 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	568
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	569 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	570 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	571 address &= 0xFFFFFF;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	572 address/= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	573 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	574 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	575 native_code_map[chunk].base = native_addr;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	576 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	577 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	578 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	579 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	580 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	581 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	582
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	583 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	584 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	585 int8_t reg, flags_reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	586 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	587 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	588 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	589 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	590 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	591 reg = native_reg(&(inst->dst), opts);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	592 //update statically set flags
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	593 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	594 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	595
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	596 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	597 flags_reg = src.base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	598 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	599 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	600 flags_reg = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	601 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	602 dst = mov_ir(dst, src.disp, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	603 src.mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	604 flags_reg = src.base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	605 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	606 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	607 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	608 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	609 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	610 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	611 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	612 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	613 dst = mov_rr(dst, src.base, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	614 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	615 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	616 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	617 dst = mov_ir(dst, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	618 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	619 } else if(src.mode == MODE_REG_DIRECT) {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	620 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	621 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	622 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	623 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	624 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	625 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	626 dst = setcc_r(dst, CC_S, FLAG_N);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	627 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	628 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	629 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	630 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	631 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	632 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	633 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	634 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	635 case MODE_AREG_INDIRECT:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	636 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	637 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	638 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	639 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	640 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	641 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	642 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	643 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	644 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	645 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	646 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	647 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	648 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	649 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	650 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	651 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	652 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	653 dst = setcc_r(dst, CC_S, FLAG_N);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	654 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	655 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	656 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	657 dst = call(dst, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	658 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	659 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	660 dst = call(dst, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	661 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	662 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	663 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	664 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	665 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	666 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	667 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	668 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	669 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	670 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	671 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	672 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	673 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	674 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	675 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	676 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	677 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	678 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	679 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	680 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	681 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	682 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	683 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	684 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	685 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	686 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	687 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	688 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	689 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	690 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	691 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	692 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	693 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	694 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	695 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	696 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	697 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	698 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	699 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	700 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	701 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	702 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	703 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	704 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	705 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	706 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	707 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	708 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	709 dst = cycles(dst, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	710 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	711 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	712 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	713 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	714 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	715 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	716 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	717 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	718 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	719 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	720 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	721 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	722 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	723 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	724 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	725 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	726 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	727 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	728 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	729 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	730 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	731 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	732 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	733 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	734 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	735 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	736 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	737 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	738 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	739 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	740 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	741 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	742 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	743 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	744 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	745 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	746 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	747 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	748 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	749 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	750 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	751 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	752 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	753 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	754 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	755 dst = setcc_r(dst, CC_S, FLAG_N);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	756 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	757 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	758 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	759 dst = call(dst, (char *)m68k_write_byte);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	760 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	761 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	762 dst = call(dst, (char *)m68k_write_word);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	763 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	764 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	765 dst = call(dst, (char *)m68k_write_long_highfirst);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	766 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	767 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	768 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	769 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	770 printf("address mode %d not implemented (move dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	771 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	772 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	773
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	774 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	775 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	776 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	777 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	778
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	779 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	780 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	781 int8_t bit,reg;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	782 uint8_t early_cycles;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	783 if(inst->src.addr_mode == MODE_REG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	784 //reg to mem
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	785 early_cycles = 8;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	786 int8_t dir;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	787 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	788 reg = 15;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	789 dir = -1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	790 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	791 reg = 0;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	792 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	793 switch (inst->dst.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	794 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	795 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	796 case MODE_AREG_PREDEC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	797 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	798 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	799 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	800 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	801 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	802 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	803 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	804 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	805 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	806 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	807 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	808 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	809 default:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	810 printf("address mode %d not implemented (movem dst)\n", inst->dst.addr_mode);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	811 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	812 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	813 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	814 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	815 if (inst->src.params.immed & (1 << bit)) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	816 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	817 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	818 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	819 dst = push_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	820 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	821 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	822 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	823 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	824 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	825 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	826 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	827 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	828 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	829 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	830 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	831 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	832 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	833 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	834 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	835 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	836 dst = call(dst, (uint8_t *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	837 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	838 dst = pop_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	839 if (inst->dst.addr_mode != MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	840 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	841 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	842 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	843 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	844 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	845 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	846 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	847 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	848 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	849 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	850 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	851 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	852 //mem to reg
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	853 early_cycles = 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	854 switch (inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	855 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	856 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	857 case MODE_AREG_POSTINC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	858 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	859 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	860 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	861 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	862 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	863 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	864 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	865 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	866 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	867 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	868 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	869 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	870 default:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	871 printf("address mode %d not implemented (movem src)\n", inst->src.addr_mode);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	872 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	873 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	874 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	875 for(reg = 0; reg < 16; reg ++) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	876 if (inst->dst.params.immed & (1 << reg)) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	877 dst = push_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	878 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	879 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	880 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	881 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	882 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	883 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	884 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	885 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	886 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	887 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	888 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	889 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	890 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	891 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	892 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	893 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	894 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	895 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	896 dst = pop_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	897 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	898 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	899 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	900 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	901 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	902 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	903 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	904 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	905 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	906 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	907 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	908 //prefetch
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	909 dst = cycles(dst, 4);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	910 return dst;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	911 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	912
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	913 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	914 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	915 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	916 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	917 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	918 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	919 int8_t reg = native_reg(&(inst->dst), opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	920 if (reg >= 0) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	921 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	922 return xor_rr(dst, reg, reg, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	923 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	924 x86_ea dst_op;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	925 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	926 if (dst_op.mode == MODE_REG_DIRECT) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	927 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	928 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	929 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	930 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	931 dst = m68k_save_result(inst, dst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	932 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	933 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	934
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	935 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	936 {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	937 x86_ea dst_op;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	938 uint8_t dst_size = inst->extra.size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	939 inst->extra.size--;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	940 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	941 if (dst_op.mode == MODE_REG_DIRECT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	942 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	943 dst = cmp_ir(dst, 0, dst_op.base, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	944 } else {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	945 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	946 dst = cmp_ir(dst, 0, SCRATCH1, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	947 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	948 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	949 inst->extra.size = dst_size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	950 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	951 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	952 dst = setcc_r(dst, CC_Z, FLAG_Z);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	953 dst = setcc_r(dst, CC_S, FLAG_N);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	954 //M68K EXT only operates on registers so no need for a call to save result here
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	955 return dst;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	956 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	957
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	958 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	959 {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	960 int8_t dst_reg = native_reg(&(inst->dst), opts);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	961 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	962 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	963 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	964 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	965 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	966 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	967 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	968 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	969 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	970 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	971 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	972 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	973 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	974 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	975 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	976 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	977 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	978 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	979 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	980 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	981 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	982 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	983 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	984 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	985 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	986 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	987 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	988 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	989 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	990 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	991 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	992 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	993 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	994 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	995 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	996 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	997 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	998 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	999 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1000 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1001 if (dst_reg >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1002 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1003 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1004 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1005 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1006 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1007 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1008 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1009 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1010 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1011 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1012 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1013 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1014 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1015 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1016 default:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1017 printf("address mode %d not implemented (lea src)\n", inst->src.addr_mode);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1018 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1019 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1020 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1021 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1022
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1023 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1024 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1025 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1026 uint32_t after = inst->address + 2;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1027 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1028 dst = cycles(dst, 10);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1029 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1030 dst = push_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1031 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1032 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1033 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1034 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1035 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1036 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1037 //dummy address to be replaced later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1038 dest_addr = dst + 5;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1039 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1040 dst = call(dst, (char *)dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1041 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1042 dst = pop_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1043 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1044 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1045
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1046 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1047 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1048 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1049 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1050 uint32_t after = inst->address + 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1051 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1052 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1053 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1054 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1055 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1056 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1057 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1058 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1059 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1060 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1061 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1062 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1063 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1064 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1065 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1066 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1067 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1068 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1069 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1070 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1071 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1072 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1073 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1074 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1075 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1076 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1077 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1078 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1079 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1080 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1081 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1082 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1083 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1084 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1085 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1086 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1087 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1088 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1089 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1090 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1091 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1092 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1093 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1094 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1095 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1096 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1097 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1098 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1099 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1100 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1101 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1102 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1103 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1104 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1105 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1106 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1107 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1108 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1109 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1110 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1111
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1112 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1113 {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1114 uint8_t * dest_addr;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1115 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1116 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1117 case MODE_AREG_INDIRECT:
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1118 dst = cycles(dst, BUS*2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1119 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1120 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1121 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1122 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1123 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1124 dst = call(dst, (uint8_t *)m68k_native_addr);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1125 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1126 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1127 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1128 dst = cycles(dst, 10);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1129 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1130 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1131 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1132 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1133 dest_addr = dst + 256;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1134 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1135 dst = jmp(dst, dest_addr);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1136 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1137 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1138 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1139 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1140 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1141 if (!dest_addr) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1142 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1143 //dummy address to be replaced later, make sure it generates a 4-byte displacement
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1144 dest_addr = dst + 256;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1145 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1146 dst = jmp(dst, dest_addr);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1147 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1148 default:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1149 printf("address mode %d not yet supported (jmp)\n", inst->src.addr_mode);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1150 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1151 return dst;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1152 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1153
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1154 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1155 {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1156 uint8_t * dest_addr;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1157 uint32_t after;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1158 switch(inst->src.addr_mode)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1159 {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1160 case MODE_AREG_INDIRECT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1161 dst = cycles(dst, BUS*2);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1162 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1163 dst = push_r(dst, SCRATCH1);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1164 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1165 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1166 dst = call(dst, (char *)m68k_write_long_highfirst);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1167 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1168 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1169 } else {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1170 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1171 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1172 dst = call(dst, (uint8_t *)m68k_native_addr);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1173 dst = call_r(dst, SCRATCH1);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1174 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1175 dst = pop_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1176 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1177 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1178 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1179 dst = cycles(dst, 10);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1180 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1181 dst = push_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1182 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1183 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1184 dst = call(dst, (char *)m68k_write_long_highfirst);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1185 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1186 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1187 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1188 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1189 dest_addr = dst + 5;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1190 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1191 dst = call(dst, (char *)dest_addr);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1192 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1193 dst = pop_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1194 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1195 case MODE_ABSOLUTE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1196 case MODE_ABSOLUTE_SHORT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1197 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1198 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1199 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1200 dst = push_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1201 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1202 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1203 dst = call(dst, (char *)m68k_write_long_highfirst);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1204 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1205 if (!dest_addr) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1206 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1207 //dummy address to be replaced later, make sure it generates a 4-byte displacement
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1208 dest_addr = dst + 5;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1209 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1210 dst = call(dst, (char *)dest_addr);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1211 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1212 dst = pop_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1213 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1214 default:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1215 printf("address mode %d not yet supported (jsr)\n", inst->src.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1216 }
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1217 return dst;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1218 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1219
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1220 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1221 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1222 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1223 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1224 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1225 dst = call(dst, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1226 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1227 dst = jcc(dst, CC_NZ, dst+3);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1228 dst = retn(dst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1229 dst = jmp(dst, (char *)m68k_modified_ret_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1230 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1231 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1232
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1233 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1234 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1235 //best case duration
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1236 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1237 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1238 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1239 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1240 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1241 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1242 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1243 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1244 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1245 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1246 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1247 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1248 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1249 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1250 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1251 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1252 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1253 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1254 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1255 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1256 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1257 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1258 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1259 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1260 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1261 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1262 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1263 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1264 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1265 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1266 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1267 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1268 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1269 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1270 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1271 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1272 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1273 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1274 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1275 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1276 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1277 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1278 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1279 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1280 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1281 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1282 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1283 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1284 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1285 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1286 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1287 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1288 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1289 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1290 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1291 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1292 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1293 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1294 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1295 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1296 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1297 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1298 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1299 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1300 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1301 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1302 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1303 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1304 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1305 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1306 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1307 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1308 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1309 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1310 }
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1311 return dst;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1312 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1313
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1314 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1315 {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1316 int8_t reg = native_reg(&(inst->src), opts);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1317 //compensate for displacement word
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1318 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1319 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1320 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1321 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1322 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1323 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1324 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1325 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1326 dst = call(dst, (char *)m68k_write_long_highfirst);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1327 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1328 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1329 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1330 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1331 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1332 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1333 //prefetch
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1334 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1335 return dst;
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1336 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1337
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1338 typedef uint8_t * (shift_ir_t)(uint8_t out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1339 typedef uint8_t * (shift_irdisp8_t)(uint8_t out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1340 typedef uint8_t * (shift_clr_t)(uint8_t out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1341 typedef uint8_t * (shift_clrdisp8_t)(uint8_t out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1342
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1343 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea src_op, x86_ea dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1344 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1345 uint8_t * end_off = NULL;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1346 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1347 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1348 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1349 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1350 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1351 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1352 if (src_op->mode == MODE_IMMED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1353 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1354 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1355 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1356 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1357 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1358 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1359 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1360 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1361 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1362 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1363 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1364 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1365 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1366 dst = and_ir(dst, 63, RCX, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1367 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1368 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1369 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1370 //x86 shifts modulo 32 for operand sizes less than 64-bits
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1371 //but M68K shifts modulo 64, so we need to check for large shifts here
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1372 dst = cmp_ir(dst, 32, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1373 uint8_t * norm_shift_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1374 dst = jcc(dst, CC_L, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1375 if (special) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1376 if (inst->extra.size == OPSIZE_LONG) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1377 uint8_t * neq_32_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1378 dst = jcc(dst, CC_NZ, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1379
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1380 //set the carry bit to the lsb
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1381 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1382 dst = special(dst, 1, dst_op->base, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1383 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1384 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1385 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1386 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1387 dst = jmp(dst, dst+4);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1388 *neq_32_off = dst - (neq_32_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1389 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1390 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1391 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1392 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1393 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1394 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1395 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1396 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1397 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1398 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1399 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1400 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1401 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1402 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1403 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1404 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1405 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1406
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1407 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1408 end_off = dst+1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1409 dst = jmp(dst, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1410 *norm_shift_off = dst - (norm_shift_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1411 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1412 dst = shift_clr(dst, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1413 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1414 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1415 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1416
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1417 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1418
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1419 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1420 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1421 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1422 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1423 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1424 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1425 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1426 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1427 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1428 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1429 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1430 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1431 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1432 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1433 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1434 }
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	1435 return dst;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1436 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1437
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1438 #define BIT_SUPERVISOR 5
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1439
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1440 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1441 {
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1442 uint8_t * end_off;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1443 map_native_address(opts->native_code_map, inst->address, dst);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1444 dst = check_cycles_int(dst, inst->address);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1445 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1446 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1447 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1448 return translate_m68k_lea(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1449 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1450 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1451 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1452 return translate_m68k_bcc(dst, inst, opts);
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1453 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1454 return translate_m68k_jmp(dst, inst, opts);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1455 } else if(inst->op == M68K_JSR) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1456 return translate_m68k_jsr(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1457 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1458 return translate_m68k_rts(dst, inst, opts);
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1459 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1460 return translate_m68k_dbcc(dst, inst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1461 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1462 return translate_m68k_clr(dst, inst, opts);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1463 } else if(inst->op == M68K_MOVEM) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1464 return translate_m68k_movem(dst, inst, opts);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1465 } else if(inst->op == M68K_LINK) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1466 return translate_m68k_link(dst, inst, opts);
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1467 } else if(inst->op == M68K_EXT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1468 return translate_m68k_ext(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1469 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1470 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1471 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1472 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1473 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1474 if (inst->dst.addr_mode != MODE_UNUSED) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1475 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1476 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1477 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1478 {
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1479 //case M68K_ABCD:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1480 // break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1481 case M68K_ADD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1482 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1483 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1484 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1485 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1486 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1487 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1488 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1489 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1490 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1491 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1492 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1493 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1494 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1495 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1496 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1497 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1498 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1499 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1500 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1501 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1502 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1503 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1504 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1505 //case M68K_ADDX:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1506 // break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1507 case M68K_AND:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1508 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1509 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1510 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1511 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1512 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1513 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1514 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1515 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1516 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1517 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1518 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1519 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1520 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1521 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1522 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1523 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1524 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1525 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1526 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1527 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1528 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1529 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1530 case M68K_ANDI_CCR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1531 case M68K_ANDI_SR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1532 dst = cycles(dst, 20);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1533 //TODO: If ANDI to SR, trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1534 if (!(inst->src.params.immed & 0x1)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1535 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1536 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1537 if (!(inst->src.params.immed & 0x2)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1538 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1539 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1540 if (!(inst->src.params.immed & 0x4)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1541 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1542 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1543 if (!(inst->src.params.immed & 0x8)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1544 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1545 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1546 if (!(inst->src.params.immed & 0x10)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1547 dst = mov_irind(dst, 0, CONTEXT, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1548 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1549 if (inst->op == M68K_ANDI_SR) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1550 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1551 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1552 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1553 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1554 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1555 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1556 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1557 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1558 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1559 case M68K_ASL:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1560 case M68K_LSL:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1561 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1562 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1563 case M68K_ASR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1564 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1565 break;
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1566 case M68K_LSR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1567 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1568 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1569 /*case M68K_BCHG:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1570 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1571 case M68K_BSET:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1572 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1573 case M68K_BTST:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1574 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
67 534eb4976423 Fix BTST Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	1575 if (src_op.mode == MODE_IMMED) {
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1576 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1577 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1578 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1579 if (dst_op.mode == MODE_REG_DIRECT) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1580 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1581 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1582 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1583 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1584 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1585 if (src_op.mode == MODE_REG_DISPLACE8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1586 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1587 dst = push_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1588 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1589 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1590 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1591 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1592 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1593 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1594 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1595 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1596 dst = and_ir(dst, 0x7, src_op.base, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1597 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1598 if (dst_op.mode == MODE_REG_DIRECT) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1599 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1600 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1601 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1602 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1603 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1604 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1605 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1606 dst = setcc_r(dst, CC_NC, FLAG_Z);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1607 if (src_op.base == SCRATCH2) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1608 dst = pop_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1609 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1610 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1611 /*case M68K_CHK:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1612 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1613 case M68K_CMP:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1614 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1615 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1616 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1617 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1618 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1619 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1620 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1621 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1622 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1623 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1624 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1625 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1626 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1627 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1628 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1629 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1630 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1631 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1632 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1633 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1634 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1635 /*case M68K_DIVS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1636 case M68K_DIVU:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1637 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1638 case M68K_EOR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1639 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1640 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1641 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1642 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1643 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1644 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1645 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1646 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1647 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1648 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1649 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1650 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1651 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1652 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1653 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1654 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1655 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1656 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1657 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1658 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1659 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1660 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1661 /*case M68K_EORI_CCR:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1662 case M68K_EORI_SR:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1663 case M68K_EXG:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1664 dst = cycles(dst, 6);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1665 if (dst_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1666 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1667 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1668 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1669 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1670 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1671 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1672 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1673 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1674 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1675 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1676 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1677 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1678 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1679 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1680 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1681 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1682 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1683 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1684 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1685 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1686 //case M68K_EXT:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1687 // break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1688 case M68K_ILLEGAL:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1689 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1690 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1691 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1692 break;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1693 /*case M68K_MOVE_FROM_SR:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1694 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1695 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1696 case M68K_MOVE_SR:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1697 //TODO: Privilege check for MOVE to SR
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1698 if (src_op.mode == MODE_IMMED) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1699 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1700 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1701 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1702 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1703 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1704 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1705 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1706 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1707 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1708 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1709 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1710 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1711 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1712 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1713 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1714 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1715 if (src_op.base != SCRATCH1) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1716 if (src_op.mode == MODE_REG_DIRECT) {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1717 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1718 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1719 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1720 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1721 }
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1722 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr));
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1723 dst = cycles(dst, 12);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1724
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1725 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1726 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1727 case M68K_MOVE_USP:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1728 dst = cycles(dst, BUS);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1729 //TODO: Trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1730 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1731 if (inst->src.addr_mode == MODE_UNUSED) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1732 if (dst_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1733 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1734 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1735 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1736 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1737 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1738 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1739 if (src_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1740 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1741 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1742 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1743 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1744 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1745 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1746 break;
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1747 /*case M68K_MOVEP:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1748 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1749 case M68K_MULU:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1750 case M68K_NBCD:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1751 case M68K_NEG:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1752 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1753 dst = neg_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1754 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1755 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1756 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1757 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1758 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1759 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1760 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1761 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1762 break;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1763 /*case M68K_NEGX:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1764 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1765 case M68K_NOP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1766 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1767 break;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1768 case M68K_NOT:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1769 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1770 dst = not_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1771 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1772 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1773 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1774 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1775 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1776 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1777 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1778 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1779 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1780 case M68K_OR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1781 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1782 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1783 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1784 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1785 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1786 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1787 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1788 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1789 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1790 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1791 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1792 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1793 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1794 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1795 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1796 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1797 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1798 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1799 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1800 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1801 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1802 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1803 /*case M68K_ORI_CCR:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1804 case M68K_ORI_SR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1805 case M68K_PEA:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1806 case M68K_RESET:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1807 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1808 case M68K_ROR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1809 case M68K_ROXL:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1810 case M68K_ROXR:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1811 case M68K_RTE:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1812 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1813 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1814 dst = push_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1815 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1816 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1817 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1818 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1819 dst = call(dst, (uint8_t *)set_sr);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1820 dst = pop_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1821 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1822 end_off = dst+1;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1823 dst = jcc(dst, CC_NC, dst+2);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1824 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1825 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1826 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1827 *end_off = dst - (end_off+1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1828 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1829 dst = jmp_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1830 break;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1831 /*case M68K_RTR:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1832 case M68K_SBCD:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1833 case M68K_SCC:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1834 case M68K_STOP:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1835 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1836 case M68K_SUB:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1837 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1838 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1839 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1840 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1841 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1842 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1843 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1844 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1845 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1846 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1847 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1848 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1849 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1850 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1851 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1852 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1853 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1854 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1855 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1856 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1857 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1858 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1859 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1860 //case M68K_SUBX:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1861 // break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1862 case M68K_SWAP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1863 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1864 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1865 dst = rol_ir(dst, 16, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1866 } else{
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1867 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1868 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1869 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1870 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1871 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1872 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1873 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1874 /*case M68K_TAS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1875 case M68K_TRAP:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1876 case M68K_TRAPV:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1877 case M68K_TST:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1878 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1879 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1880 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1881 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1882 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1883 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1884 dst = setcc_r(dst, CC_C, FLAG_C);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1885 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1886 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1887 dst = setcc_r(dst, CC_O, FLAG_V);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1888 break;
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1889 case M68K_UNLK:
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1890 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1891 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1892 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1893 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1894 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1895 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1896 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1897 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1898 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1899 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1900 } else {
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1901 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1902 }
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1903 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1904 break;
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1905 /*case M68K_INVALID:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1906 break;*/
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1907 default:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1908 printf("instruction %d not yet implemented\n", inst->op);
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	1909 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1910 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1911 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1912 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1913
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1914 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1915 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1916 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1917 x86_68k_options * opts = context->options;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1918 uint8_t * dst = opts->cur_code;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1919 uint8_t * dst_end = opts->code_end;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1920 if(get_native_address(opts->native_code_map, address)) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1921 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1922 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1923 char disbuf[1024];
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1924 uint16_t encoded, next;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1925 if ((address & 0xFFFFFF) < 0x400000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1926 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1927 } else if ((address & 0xFFFFFF) > 0xE00000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1928 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1929 } else {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1930 printf("attempt to translate non-memory address: %X\n", address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1931 exit(1);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1932 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1933 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1934 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1935 if (dst_end-dst < 128) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1936 puts("out of code memory");
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1937 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1938 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1939 next = m68k_decode(encoded, &instbuf, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1940 address += (next-encoded)*2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1941 encoded = next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1942 m68k_disasm(&instbuf, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1943 printf("%X: %s\n", instbuf.address, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1944 dst = translate_m68k(dst, &instbuf, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1945 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1946 process_deferred(opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1947 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1948 address = opts->deferred->address;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1949 encoded = context->mem_pointers[0] + address/2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1950 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1951 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1952 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1953 } while(encoded != NULL);
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1954 opts->cur_code = dst;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1955 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1956 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1957
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1958 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address)
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1959 {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1960 address &= 0xFFFFFF;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1961 uint8_t * ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1962 if (!ret) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1963 translate_m68k_stream(address, context);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1964 ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1965 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1966 return ret;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1967 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1968
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1969 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1970 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1971 uint8_t * addr = get_native_address(context->native_code_map, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1972 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1973 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1974
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1975 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1976 {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1977 //TODO: Make this actually use the normal read functions
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1978 context->aregs[7] = context->mem_pointers[0][0] << 16 \| context->mem_pointers[0][1];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1979 uint32_t address = context->mem_pointers[0][2] << 16 \| context->mem_pointers[0][3];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1980 start_68k_context(context, address);
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1981 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1982
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1983 void init_x86_68k_opts(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1984 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1985 opts->flags = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1986 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1987 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1988 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1989 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1990 opts->dregs[2] = R12;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1991 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1992 opts->aregs[1] = R14;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1993 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1994 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1995 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1996 opts->deferred = NULL;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1997 size_t size = 1024 * 1024;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1998 opts->cur_code = alloc_code(&size);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	1999 opts->code_end = opts->cur_code + size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2000 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2001
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2002 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2003 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2004 memset(context, 0, sizeof(m68k_context));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2005 context->native_code_map = native_code_map;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2006 context->options = opts;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2007 context->int_cycle = 0xFFFFFFFF;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2008 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2009

Mercurial > repos > blastem

annotate m68k_to_x86.c @ 97:c7185fd840fc