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annotate svp.cpu @ 1621:ca158bc091f9

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Implement program ROM reads
author Michael Pavone <pavone@retrodev.com>
date Sat, 06 Oct 2018 17:33:15 -0700
parents a172f97d873f
children 4bb2c8b78b4a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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1 info
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2 prefix svp_
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3 opcode_size 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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4 body svp_run_op
1618
5dbc453cd345 Getting SVP core closer to compiling
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parents: 1617
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5 header svp.h
1620
a172f97d873f Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents: 1619
diff changeset
6 include svp_util.c
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7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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8 regs
1621
ca158bc091f9 Implement program ROM reads
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parents: 1620
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9 internal 16 scratch2 x y pad0 st pad1 pc
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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10 a 32
1621
ca158bc091f9 Implement program ROM reads
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11 scratch1 32
ca158bc091f9 Implement program ROM reads
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parents: 1620
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12 rom ptr16
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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13 stack 16 stack0 stack1 stack2 stack3 stack4 stack5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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14 stackidx 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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15 p 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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16 external 16 pm0 pm1 pm2 xst pm4 ext5 pmc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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17 pointers0 8 r0 r1 r2 r3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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18 pointers1 8 r4 r5 r6 r7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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19 iram 16 1024
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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20 ram0 16 256
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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21 ram1 16 256
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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22 zflag 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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23 nflag 8
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24 rpl 16
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25
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26 flags
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27 register st
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28 Z 13 zero zflag
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29 N 15 sign nflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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30 R 0-2 none rpl
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31
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32 svp_pop
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33 mov stack.stackidx dst
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34 add 1 stackidx stackidx
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35 switch stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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36 case 6
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37 mov 0 stackidx
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38 end
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39
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40 svp_push
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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41 arg src 16
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0e8438a4c76f Clean up warnings from -1 case
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42 sub 1 stackidx stackidx
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43 switch stackidx
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0e8438a4c76f Clean up warnings from -1 case
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44 case 0xFF
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45 mov 5 stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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46 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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47 mov src stack.stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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48
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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49 svp_ram_read
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50 arg mode 16
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51 arg banki 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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52 arg regi 16
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53 local idx 16
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54
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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55 switch banki
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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56 case 0
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57 meta bank ram0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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58 meta reg pointers0.regi
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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59
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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60 default
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61 meta bank ram1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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62 meta reg pointers1.regi
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63 end
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64
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65 mov reg idx
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66 switch mode
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67 case 0
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68 meta modestr ""
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69
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70 case 1
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71 meta modestr +!
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72 add 1 reg reg
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73
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74 case 2
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75 #loop decremenet
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76 meta modestr -
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c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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77
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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78 if rpl
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5dbc453cd345 Getting SVP core closer to compiling
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79 local tmp 16
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80 mov reg tmp
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81 lsl 1 rpl rpl
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82 sub 1 rpl rpl
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83 local mask 16
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84 not rpl mask
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85 and reg mask reg
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86 sub 1 tmp tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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87 and rpl tmp tmp
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88 or tmp reg reg
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c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents: 1613
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89 else
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents: 1613
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90 sub 1 reg reg
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents: 1613
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91 end
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92
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93 case 3
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94 #loop increment
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95 meta modestr +
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96
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97 and 7 st rpl
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c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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98 if rpl
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99 local tmp 16
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100 mov reg tmp
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101 lsl 1 rpl rpl
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102 sub 1 rpl rpl
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103 local mask 16
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104 not rpl mask
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105 and reg mask reg
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106 add 1 tmp tmp
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107 and rpl tmp tmp
1618
5dbc453cd345 Getting SVP core closer to compiling
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108 or tmp reg reg
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c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents: 1613
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109 else
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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parents: 1613
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110 sub 1 reg reg
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111 end
1617
5e04f9f8bd85 Add missing end in svp_ram_read. Fix alu_ram_indirect
Michael Pavone <pavone@retrodev.com>
parents: 1615
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112 end
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113
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114 and 255 idx idx
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115 meta val bank.idx
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116
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117 svp_read_ext
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118 arg regidxr 16
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119 switch regidxr
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120 case 7
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121 meta val a
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122
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123 default
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124 #TODO: PMAR stuff
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125 meta val external.regidxr
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126 end
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127
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128 svp_write_ext
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129 arg regidxw 16
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130 switch regidxw
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131 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
132 and 0xFFFF0000 a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
133 or src a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
134
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
135 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136 #TODO: PMAR stuff
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137 mov src external.regidxw
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
138 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
139
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
140 svp_alu_op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141 arg P 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
142 arg param 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 switch P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145 case 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 dis "sub %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 sub param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
150 dis "cmp %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 cmp param a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153 case 4
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154 dis "add %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 add param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
156
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
157 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
158 dis "and %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
159 and param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 dis "or %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163 or param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 dis "eor %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 xor param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 svp_check_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172 arg fval 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 arg cond 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 local invert 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 switch cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176 case 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177 meta flag 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 meta flag zflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
181
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
182 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
183 meta flag nflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
184
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
185 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 meta flag 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
187 end
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
188
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
189 if fval
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
190 meta istrue flag
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
191
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
192 else
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 lnot flag invert
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
194 meta istrue invert
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 PPP0000000000000 alu_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
201 meta name "-"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202 svp_alu_op P 0xFFFF0000
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204 PPP0000000000RRR alu_r
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 lsl internal.R 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209 meta name internal.R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212 PPP0000000000011 alu_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 svp_alu_op P a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 PPP0000000000101 alu_stack
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 svp_pop
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
223 meta name "stack"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 PPP0000000000111 alu_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 meta name p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 svp_alu_op P p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 PPP0000000001RRR alu_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 svp_read_ext R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 meta name val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
241 PPP0001B0000MMRR alu_ram
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 svp_ram_read M B R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 switch P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 case 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 dis "sub (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 sub tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 dis "cmp (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 cmp tmp a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257 case 4
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 dis "add (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 add tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 dis "and (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 and tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266 dis "or (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 dis "eor (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 xor tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
276 PPP0101B0000MMRR alu_ram_indirect
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
277 invalid P 0
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
278 invalid P 2
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
279 svp_ram_read M B R
1617
5e04f9f8bd85 Add missing end in svp_ram_read. Fix alu_ram_indirect
Michael Pavone <pavone@retrodev.com>
parents: 1615
diff changeset
280 svp_prog_ram_read val
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
281 local tmp 32
1617
5e04f9f8bd85 Add missing end in svp_ram_read. Fix alu_ram_indirect
Michael Pavone <pavone@retrodev.com>
parents: 1615
diff changeset
282 lsl scratch1 16 tmp
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
283
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
284 switch P
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
285 case 1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
286 dis "sub ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
287 sub tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
288
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
289 case 3
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
290 dis "cmp ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
291 cmp tmp a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
292
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
293 case 4
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
294 dis "add ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
295 add tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
296
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
297 case 5
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
298 dis "and ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
299 and tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
300
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
301 case 6
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
302 dis "or ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
303 or tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
304
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
305 case 7
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
306 dis "eor ((%s%s))" reg modestr
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
307 xor tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
308 end
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
309
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
310 update_flags ZN
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
311
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 PPP0000000001111 alu_al
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 lsl a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 meta name al
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
321 PPP0011JAAAAAAAA alu_ram_direct
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
322 invalid P 0
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
323 invalid P 2
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
324 if J
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
325 meta src ram1.A
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
326 else
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
327 meta src ram0.A
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
328 end
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
329 svp_alu_op P src
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
330
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
331 PPP0010000000000 alu_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
332 invalid P 0
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
333 invalid P 2
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
334 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
335 svp_alu_op P scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
336
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 1001000FCCCC0OOO cond_mod
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 svp_check_cond F C
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
339 if istrue
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
340
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 switch O
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 case 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 asr a 1 a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347 lsl a 1 a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 neg a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 abs a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 update_flags N
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 end
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
358 end
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 000000000DDD0SSS ld_int_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 dis "ld %s, %s" internal.D internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 mov internal.S internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
364 000000000DDD0101 ld_int_stack
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
365 dis "ld %s, stack" internal.D
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 meta dst internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
369 0000000000110101 ld_a_stack
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
370 dis "ld a, stack"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 lsl tmp 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
378 0000000001110101 ld_p_stack
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
379 dis "ld p, stack"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 lsl tmp 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
387 0000000001010SSS ld_stack_int
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
388 dis "ld stack, %s" internal.S
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 svp_push internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
391 0000000001010011 ld_stack_a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
392 dis "ld stack, a"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 svp_push tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
397 0000000001010111 ld_stack_p
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
398 dis "ld stack, p"
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 svp_push tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 0000000000000000 ld_n1_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 #nop?
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 dis "ld -, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 0000000000000SSS ld_n1_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 #nop?
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 dis "nop??"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 0000000000110111 ld_a_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 dis "ld a, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 mov p a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 0000000001110011 ld_p_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 dis "ld p, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 mov a p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 0000000000110011 ld_a_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 dis "ld a, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 mov a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 0000000001110111 ld_p_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 dis "ld p, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 mov p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 000000000DDD0111 ld_int_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 mov tmp internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 dis "ld %s, p" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 000000000DDD0111 ld_int_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 mov tmp internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 dis "ld %s, a" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 0000000001110SSS ld_p_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 lsl internal.S 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 mov tmp p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 dis "ld p, %s" internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 0000000000110SSS ld_a_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 lsl internal.S 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 mov tmp a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 dis "ld a, %s" internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 000000000DDD0000 ld_int_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 dis "ld %s, -" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 mov 0xFFFF internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 0000000000110000 ld_a_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 dis "ld a, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 or 0xFFFF0000 a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 0000000001110000 ld_p_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 dis "ld p, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 or 0xFFFF0000 p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 000000000DDD1SSS ld_int_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 dis "ld %s, %s" internal.D val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 mov val internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 0000000000111SSS ld_a_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 dis "ld a, %s" val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 0000000001111SSS ld_p_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480 dis "ld p, %s" val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 000000001DDD0SSS ld_ext_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 meta src internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 dis "ld al, %s" src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 dis "ld %s, %s" external.D src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 000000001DDD0011 ld_ext_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 meta src tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 dis "ld al, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 dis "ld %s, a" external.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 000000001DDD0111 ld_ext_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 meta src tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 dis "ld al, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 dis "ld %s, p" external.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 000000001DDD1SSS ld_ext_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 meta src val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 dis "ld al, %s" src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 dis "ld %s, %s" external.D src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 0000001B0DDDMMPP ld_int_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 dis "ld %s, (%s%s)" internal.D reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 mov val internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 0000001B0011MMPP ld_a_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 dis "ld a, (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 0000001B0111MMPP ld_p_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 dis "ld p, (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
556 0000001B0101MMPP ld_stack_ram
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 svp_ram_read M B P
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
558 dis "ld stack, (%s%s)" reg modestr
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559 svp_push val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
561 000010000DDD0000 ld_int_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
562 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
563 dis "ld %s, %X" internal.D scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
564 mov scratch1 internal.D
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
565
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
566 0000100000000000 ld_n1_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
567 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
568 dis "ld -, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
569
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
570 0000100000110000 ld_a_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
571 local tmp 32
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
572 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
573 dis "ld a, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
574 lsl 16 scratch1 tmp
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
575 and 0xFFFF a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
576 or tmp a a
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
577
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
578 0000100001010000 ld_stack_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
579 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
580 dis "ld stack, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
581 svp_push scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
582
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
583 0000100001110000 ld_p_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
584 local tmp 32
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
585 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
586 dis "ld p, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
587 lsl 16 scratch1 tmp
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
588 and 0xFFFF p p
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
589 or tmp p p
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
590
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
591 000010001DDD0000 ld_ext_immed
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
592 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
593 dis "ld %s, %X", external.D, scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
594 meta src scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
595 svp_write_ext D
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
596 switch D
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
597 case 7
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
598 dis "ld al, %X" scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
599
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
600 default
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
601 dis "ld %s, %X" external.D scratch1
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
602 end
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
603
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 0100100FCCCC0000 call_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 svp_check_cond F C
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 svp_op_fetch
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
608 if istrue
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 svp_push pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 mov scratch1 pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 0100110FCCCC0000 bra_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 svp_check_cond F C
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 svp_op_fetch
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
616 if istrue
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 mov scratch1 pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 end
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
619
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
620 svp_prog_ram_read
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
621 arg src 16
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 cycles 1
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
623 cmp 1024 src
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625 if >=U
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
626 add src src scratch1
1621
ca158bc091f9 Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents: 1620
diff changeset
627 ocall prog_read_16
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629 else
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
630 mov iram.src scratch1
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 end
1615
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
632
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
633 svp_op_fetch
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents: 1614
diff changeset
634 svp_prog_ram_read pc
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 add 1 pc pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 svp_run_op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 svp_op_fetch
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 dispatch scratch1